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RENESAS Microcontroller Units (MCUs/MPUs/SOCs), VFBGA-100. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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DA14697-00000HR2

RENESAS · Microcontroller Units (MCUs/MPUs/SOCs) · VFBGA-100

DA14697-00000HR2 from RENESAS, in a VFBGA-100. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
A1	QSPIF_CLK	output	OUTPUT. QSPI Flash clock.
A2	QSPIF_D0	bidirectional	INPUT/OUTPUT. QSPI Flash I/O data 0.
A3	P0_10	bidirectional	General-purpose I/O (4.8 mA, I-PU at reset) with alternate function M33_SWDIO, the Arm Cortex-M33 JTAG/SWD data I/O signal.
A4	P0_12	bidirectional	General-purpose I/O (4.8 mA, I-PU at reset) with alternate functions CMAC_SWDIO (Arm Cortex-M0+ JTAG data I/O) and XTAL32M (32 MHz XTAL oscillator clock output).
A5	VSUP_RF	power_in	Radio supply voltage input; connect to V14 externally and provide a 10 µF decoupling capacitor.
A6	PSUB	power_in	RF ground.
A7	RFIOM	power_in	RF ground for the RFIOP radio port.
A8	RFIOP	passive	RF input/output with 50 Ω impedance.
A9	RFIOM2	power_in	RF ground.
A10	PSUB_RF	power_in	RF ground.
B1	QSPIF_CS	output	OUTPUT. QSPI Flash chip select (active LOW); the output is HIGH in default and reset states and no pull-up resistor is required.
B2	QSPIF_D3	bidirectional	INPUT/OUTPUT. QSPI Flash I/O data 3.
B3	P0_11	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function M33_SWCLK, the Arm Cortex-M33 JTAG clock input.
B4	P0_13	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions CMAC_SWCLK (Arm Cortex-M0+ JTAG clock input) and RC32M (RC32M clock output, square wave).
B5	P0_09	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions GPADC_3 and SDADC_3 analog inputs, PG4_4, and UART Boot TX output.
B6	P0_08	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions GPADC_2 and SDADC_2 analog inputs, PG4_3, and UART Boot RX input.
B7	ESDN	power_in	RF ground.
B8	RSTn	input	Reset input, active LOW.
B9	P0_07	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function NTC Input, the analog feedback input for the battery NTC.
B10	P0_06	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function SDADC_GND, the analog input for the ΣΔ ADC reference ground.
C1	QSPIF_D2	bidirectional	INPUT/OUTPUT. QSPI Flash I/O data 2.
C2	QSPIF_D1	bidirectional	INPUT/OUTPUT. QSPI Flash I/O data 1.
C3	P0_24	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions PG1_4 (Pattern Generator 1, output 4) and LCD_TE (LCD tearing effect input).
C4	P0_21	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function PG1_3 (Pattern Generator 1, output 3).
C5	P0_20	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function PG2_4 (Pattern Generator 2, output 4).
C6	P0_19	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function PG2_3 (Pattern Generator 2, output 3).
C7	P0_18	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function PG2_2 (Pattern Generator 2, output 2).
C8	P0_17	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions PG2_1 (Pattern Generator 2, output 1) and RC32k (32 kHz RC clock output, square wave).
C9	P0_16	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions SDADC_REF (ΣΔ ADC reference voltage input) and RCX (RCX clock output, square wave).
C10	GND_RF2	power_in	RF ground.
D1	P0_05	bidirectional	General-purpose I/O (4/8/12/16 mA, I-PD at reset) with alternate function QSPIR_CLK (QSPI RAM clock output) and PG3_3; usable as GPIO only at 1.8 V because it is a QSPI pad.
D2	P0_00	bidirectional	General-purpose I/O (4/8/12/16 mA, I-PD at reset) with alternate functions QSPIR_D0 (QSPI RAM data I/O 0) and PG3_4; usable as GPIO only at 1.8 V because it is a QSPI pad.
D3	P0_31	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions PG1_2 (Pattern Generator 1, output 2) and LCD_XRST (LCD reset for horizontal and vertical driver).
D4	P0_30	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions PG1_1 (Pattern Generator 1, output 1), LCD_HST and PLCD_HSYNC.
D5	P0_29	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions PG0_4 (Pattern Generator 0, output 4), LCD_HCK and PLCD_CLK.
D6	P0_28	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions PG0_3 (Pattern Generator 0, output 3), LCD_VST and PLCD_VSYNC.
D7	P0_27	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions PG0_2 (Pattern Generator 0, output 2), LCD_ENB and PLCD_ENAB.
D8	P0_26	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions PG0_1 (Pattern Generator 0, output 1) and LCD_VCK (LCD shift clock for vertical driver).
D9	P0_25	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions GPADC_1 and SDADC_1 analog inputs.
D10	GND_RF1	power_in	RF ground.
E1	P0_04	bidirectional	General-purpose I/O (4/8/12/16 mA, I-PU at reset) with alternate functions QSPIR_CS (QSPI RAM chip select, active LOW) and PG3_1; usable as GPIO only at 1.8 V because it is a QSPI pad.
E2	P0_03	bidirectional	General-purpose I/O (4/8/12/16 mA, I-PD at reset) with alternate functions QSPIR_D3 (QSPI RAM data I/O 3) and PG3_2; usable as GPIO only at 1.8 V because it is a QSPI pad.
E3	VSSIOQ	power_in	QSPI ground.
E4	P1_05	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_GREEN1 (LCD green image data output, bit 1).
E5	P1_04	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_GREEN0 (LCD green image data output, bit 0).
E6	P1_03	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_BLUE1 (LCD blue image data output, bit 1).
E7	P1_02	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function LCD_BLUE0 (LCD blue image data output, bit 0).
E8	P1_01	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function Timer.PWM, a timer/PWM output available in Sleep mode.
E9	P1_00	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function NTC Supply, the power supply output for the battery NTC sensor.
E10	XTAL32M_GND	power_in	Analog ground input of the 32 MHz XTAL oscillator.
F1	P0_02	bidirectional	General-purpose I/O (4/8/12/16 mA, I-PD at reset) with alternate functions QSPIR_D2 (QSPI RAM data I/O 2) and PG4_1; usable as GPIO only at 1.8 V because it is a QSPI pad.
F2	P0_01	bidirectional	General-purpose I/O (4/8/12/16 mA, I-PD at reset) with alternate functions QSPIR_D1 (QSPI RAM data I/O 1) and PG4_2; usable as GPIO only at 1.8 V because it is a QSPI pad.
F3	VSSD4	power_in	Digital ground.
F4	VSSD3	power_in	Digital ground.
F5	AVS1	power_in	Analog ground.
F6	P1_08	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_RED1 (LCD red image data output, bit 1).
F7	P1_07	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_RED0 (LCD red image data output, bit 0).
F8	P1_06	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function Timer2.PWM, the Timer2/PWM2 output available in Sleep mode.
F9	XTAL32Mp	passive	Crystal input for the 32 MHz XTAL oscillator.
F10	XTAL32Mm	passive	Crystal output for the 32 MHz XTAL oscillator.
G1	V18F	power_out	1.8 V power rail with maximum current 50 mA; requires a 0.1 µF decoupling capacitor and must be connected to V18P externally.
G2	V18P	power_out	1.8 V power rail with maximum current 50 mA; requires a 22 µF decoupling capacitor.
G3	VSSD1	power_in	Digital ground.
G4	VSSD2	power_in	Digital ground.
G5	AVS2	power_in	Analog ground.
G6	P1_11	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_XFRP (LCD liquid crystal driving signal, 62.5 Hz inverted).
G7	P1_10	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions LCD_VCOM/LCD_FRP combined output (62.5 Hz) and LCD_EXTCOMIN (1 Hz COM inversion signal input).
G8	P1_09	bidirectional	General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions GPADC_0 and SDADC_0 analog inputs.
G9	XTAL32M_GND	power_in	Analog ground input of the 32 MHz XTAL oscillator.
G10	XTAL32M_GND	power_in	Analog ground input of the 32 MHz XTAL oscillator.
H1	V14	power_out	1.4 V power rail output; requires a 10 µF decoupling capacitor.
H2	V18	power_out	1.8 V power rail with maximum current 50 mA; requires a 22 µF decoupling capacitor.
H3	P1_17	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions LCD_HST and PLCD_HSYNC (LCD start signal for horizontal driver / column pointer reset).
H4	P1_16	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions LCD_HCK and PLCD_CLK (LCD horizontal shift clock / parallel LCD clock).
H5	P1_15	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions LCD_VST and PLCD_VSYNC (LCD vertical start / row pointer reset).
H6	P1_14	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions SDADC_4 analog input, LCD_ENB and PLCD_ENAB.
H7	P1_13	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions GPADC_4 analog input and LCD_VCK (LCD vertical shift clock).
H8	P1_12	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function GPADC_5, the general-purpose ADC channel 5 analog input.
H9	P0_22	passive	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function XTAL32km, the analog output of the 32.768 kHz XTAL oscillator.
H10	P0_23	passive	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions XTAL32kp (analog input of the 32.768 kHz crystal oscillator) and a digital input for an external 32 kHz clock (square wave).
J1	LY	passive	Connection for the external DC-DC converter inductor.
J2	V12	power_out	1.2 V power rail output; requires a 10 µF decoupling capacitor.
J3	HDRV GND	power_in	Haptic driver ground.
J4	HDRVP	output	Positive haptic driver differential output.
J5	VBUS	power_in	USB bus voltage input (VBUS) that is also the battery charge voltage input; absolute maximum 6.5 V and recommended range 4.2 V to 5.75 V.
J6	V30	power_out	3.0 V power rail with maximum current 150 mA; requires a 4.7 µF decoupling capacitor.
J7	P1_21	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions SDADC_6 analog input and LCD_XRST (LCD reset for horizontal and vertical driver).
J8	P1_20	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function SDADC_5, the ΣΔ ADC channel 5 analog input.
J9	P1_19	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function GPADC_7, the general-purpose ADC channel 7 analog input.
J10	P1_18	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate function GPADC_6, the general-purpose ADC channel 6 analog input.
K1	LX	passive	Connection for the external DC-DC converter inductor.
K2	VBAT2	power_in	Battery connection 2 for the DC-DC converter supply; recommended supply range 2.4 V to 4.75 V.
K3	BUCK GND	power_in	DC-DC converter ground.
K4	HDRVM	output	Negative haptic driver differential output.
K5	VBAT1	power_in	Battery connection 1 for the LDO supply; recommended supply range 2.4 V to 4.75 V.
K6	P0_14	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset, no state retention in power down) with alternate functions USBp (USB Full Speed D+) and XTAL32k (XTAL32k clock output, square wave).
K7	P0_15	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset, no state retention in power down) with alternate functions USBm (USB Full Speed D-) and DIVN (DIVN clock output, square wave).
K8	P1_22	bidirectional	General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions SDADC_7 analog input and LCD_TE (LCD tearing effect input).
K9	LED2	output	LED 2 driver output, open drain, 20 mA maximum.
K10	LED1	output	LED 1 driver output, open drain, 20 mA maximum.

Key specifications

Parameter	Value
Manufacturer	RENESAS
Package	VFBGA-100
Category	Single Chip Microcomputer/Microcontroller
Pins	100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Limiting voltage on a pin	VPIN_LIM_DEF	-0.1		3.6	V	Default, unless otherwise specified	65
Limiting battery supply voltage	VBAT_LIM	0		6	V	Pin VBAT	65
Limiting bus supply voltage	VBUS_LIM	0		6.5	V	Pin VBUS	65
Limiting voltage on a pin	VPIN_LIM_3V0	0		3.45	V	3.0 V I/O pins	65
Limiting voltage on a pin	VPIN_LIM_1V8	0		1.98	V	1.8 V I/O pins	65
Electrostatic discharge voltage (Human Body Model)	VESD_HBM_BGA100			2200	V	VFBGA100 package	65
Electrostatic discharge voltage (Charged Device Model)	VESD_CDM_BGA100			500	V	VFBGA100 package	65
Storage temperature	TSTG	-50		150	°C		65
Power supply rise time	tR_SUP			30	ms		65
Battery supply voltage	VBAT	2.4		4.75	V	Pin VBAT1 and VBAT2	65
Bus supply voltage	VBUS	4.2		5.75	V	Pin VBUS	65
Voltage on a pin	VPIN_3V0	0		3	V	3.0 V I/O pins	65
Voltage on a pin	VPIN_1V8	0		1.8	V	1.8 V I/O pins	65
Ambient temperature	TA	-40		85	°C		65
Thermal resistance (junction to ambient)	RθJA_P2_HR		48.8		ºC/W	VFBGA100 package. JEDEC PCB, 0.1W+0.3W Power map	69
LOW level input current with pull-up	IIL_PU_RSTN	-75		-25	μA	Pin RESETn, VI = 0.0 V	69
Bandgap reference voltage from GPADC reference buffer	VBG_REF	1.14	1.2	1.26	V		69
Internal bandgap reference trim test current	IBG_IREF_CUR_TRIM	13	15	16	μA		69
Reset voltage	VRST_VDD_sleep	0.67	0.7	0.73	V	BOD_LVL_VDD_RET = 0x6F	69
Reset voltage	VRST_VDD	1.02	1.05	1.08	V	BOD_LVL_VDD_ON = 0xA7	69
Reset voltage	VRST_V14	1.21	1.25	1.29	V	BOD_LVL_V14 = 0xC7	69
Reset voltage	VRST_V18P	1.61	1.65	1.69	V	BOD_LVL_V18P = 0x107	69
Reset voltage	VRST_V30	1.91	1.95	1.99	V	BOD_LVL_V30 = 0x137	69
Reset voltage	VRST_VBAT	2.24	2.3	2.36	V	BOD_LVL_VBAT = 0xF4	70
Gain error without calibration	EG	-3		3	%	Trimmed bandgap	70
Gain error after calibration	EG_CALIBRATED	-1		1	%	Trimmed bandgap & Gain Error + Offset correction applied	70
Offset error without calibration	EOFS	-20		20	LSB	Trimmed bandgap; LSB wrt 10bit accuracy	70
Offset error after calibration	EOFS_CALIBRATED	-7		4	LSB	Trimmed bandgap & Gain Error + Offset correction applied; LSB wrt 10bit accuracy	70
Gain error of the 3x attenuator	EG_ATTN3x	-4		1	%	Trimmed bandgap & GPADC Gain Error + Offset correction applied	70
Integral non-linearity	INL	-2		2	LSB	LSB wrt 10bit accuracy	70
Differential non-linearity	DNL	-2		2	LSB	LSB wrt 10bit accuracy	70
Gain error	EG_ext_ref	-0.25		0.25	%	Using external voltage reference 1.2 V	71
Integral non-linearity	INL_ext_ref	-4		4	LSB	LSB wrt 14b accuracy	71
Differential non-linearity	DNL_ext_ref	-4		4	LSB	LSB wrt 14b accuracy	71
Offset error	EOFS_ext_ref	-2		2	LSB	LSB wrt 14b accuracy. Using external voltage reference 1.2 V	71
VDD1V2 Output Voltage	VO_1V2_0	0.85	0.9	0.95	V	VDD_LEVEL = 0	72
VDD1V2 Output Voltage	VO_1V2_1	0.95	1	1.05	V	VDD_LEVEL = 1	72
VDD1V2 Output Voltage	VO_1V2_2	1.05	1.1	1.15	V	VDD_LEVEL = 2	72
VDD1V2 Output Voltage	VO_1V2_3	1.15	1.2	1.25	V	VDD_LEVEL = 3	72
VDD1V4 Output Voltage	VO_1V4_0	1.15	1.2	1.25	V	V14_LEVEL = 0	72
VDD1V4 Output Voltage	VO_1V4_1	1.2	1.25	1.3	V	V14_LEVEL = 1	72
VDD1V4 Output Voltage	VO_1V4_2	1.25	1.3	1.35	V	V14_LEVEL = 2	72
VDD1V4 Output Voltage	VO_1V4_3	1.3	1.35	1.4	V	V14_LEVEL = 3	72
VDD1V4 Output voltage	VO_1V4_4	1.35	1.4	1.45	V	V14_LEVEL = 4	72
VDD1V4 Output Voltage	VO_1V4_5	1.4	1.45	1.5	V	V14_LEVEL = 5	72
VDD1V4 Output Voltage	VO_1V4_6	1.45	1.5	1.55	V	V14_LEVEL = 6	72
VDD1V4 Output Voltage	VO_1V4_7	1.5	1.55	1.6	V	V14_LEVEL = 7	72
VDD1V8 Output Voltage	VO_1V8_0	1.1	1.2	1.25	V	V18_LEVEL = 0	72
VDD1V8 Output Voltage	VO_1V8_1	1.7	1.8	1.9	V	V18 LEVEL = 1	72
VDD1V8P Output Voltage	VO_1V8P	1.7	1.8	1.9	V		72
LDO output voltage	VLDO_1v8_0	1.14	1.2	1.25	V		74
LDO output voltage	VLDO_1v8_1	1.7	1.8	1.9	V		74
LDO output voltage	VLDO_CORE_0	0.85	0.9	0.95	V	V30 = 3.0 V; ILOAD = 1 mA	76
LDO output voltage	VLDO_CORE_1	0.95	1	1.05	V	V30 = 3.0 V; ILOAD = 1 mA	76
LDO output voltage	VLDO_CORE_2	1.04	1.1	1.16	V	V30 = 3.0 V; ILOAD = 1 mA	76
LDO output voltage	VLDO_CORE_3	1.14	1.2	1.26	V	V30 = 3.0 V; ILOAD = 1 mA	76

CAD (KiCad official)

Symbol: DA14697-00000HR2
Footprint: Package_BGA:VFBGA-100_7.0x7.0mm_Layout10x10_P0.65mm
3D model: VFBGA-100 (KiCad packages3D, STEP)
3D model files: da14697-00000hr2-etched.step / da14697-00000hr2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); da14697-00000hr2.step / da14697-00000hr2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: RENESAS datasheet (757 pp, sha256 078a98fd8552338d, retrieved 2026-10-30, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# DA14697-00000HR2

**RENESAS** · Microcontroller Units (MCUs/MPUs/SOCs) · VFBGA-100

DA14697-00000HR2 from RENESAS, in a VFBGA-100. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| A1 | QSPIF_CLK | output | OUTPUT. QSPI Flash clock. |
| A2 | QSPIF_D0 | bidirectional | INPUT/OUTPUT. QSPI Flash I/O data 0. |
| A3 | P0_10 | bidirectional | General-purpose I/O (4.8 mA, I-PU at reset) with alternate function M33_SWDIO, the Arm Cortex-M33 JTAG/SWD data I/O signal. |
| A4 | P0_12 | bidirectional | General-purpose I/O (4.8 mA, I-PU at reset) with alternate functions CMAC_SWDIO (Arm Cortex-M0+ JTAG data I/O) and XTAL32M (32 MHz XTAL oscillator clock output). |
| A5 | VSUP_RF | power_in | Radio supply voltage input; connect to V14 externally and provide a 10 µF decoupling capacitor. |
| A6 | PSUB | power_in | RF ground. |
| A7 | RFIOM | power_in | RF ground for the RFIOP radio port. |
| A8 | RFIOP | passive | RF input/output with 50 Ω impedance. |
| A9 | RFIOM2 | power_in | RF ground. |
| A10 | PSUB_RF | power_in | RF ground. |
| B1 | QSPIF_CS | output | OUTPUT. QSPI Flash chip select (active LOW); the output is HIGH in default and reset states and no pull-up resistor is required. |
| B2 | QSPIF_D3 | bidirectional | INPUT/OUTPUT. QSPI Flash I/O data 3. |
| B3 | P0_11 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function M33_SWCLK, the Arm Cortex-M33 JTAG clock input. |
| B4 | P0_13 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions CMAC_SWCLK (Arm Cortex-M0+ JTAG clock input) and RC32M (RC32M clock output, square wave). |
| B5 | P0_09 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions GPADC_3 and SDADC_3 analog inputs, PG4_4, and UART Boot TX output. |
| B6 | P0_08 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions GPADC_2 and SDADC_2 analog inputs, PG4_3, and UART Boot RX input. |
| B7 | ESDN | power_in | RF ground. |
| B8 | RSTn | input | Reset input, active LOW. |
| B9 | P0_07 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function NTC Input, the analog feedback input for the battery NTC. |
| B10 | P0_06 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function SDADC_GND, the analog input for the ΣΔ ADC reference ground. |
| C1 | QSPIF_D2 | bidirectional | INPUT/OUTPUT. QSPI Flash I/O data 2. |
| C2 | QSPIF_D1 | bidirectional | INPUT/OUTPUT. QSPI Flash I/O data 1. |
| C3 | P0_24 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions PG1_4 (Pattern Generator 1, output 4) and LCD_TE (LCD tearing effect input). |
| C4 | P0_21 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function PG1_3 (Pattern Generator 1, output 3). |
| C5 | P0_20 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function PG2_4 (Pattern Generator 2, output 4). |
| C6 | P0_19 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function PG2_3 (Pattern Generator 2, output 3). |
| C7 | P0_18 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function PG2_2 (Pattern Generator 2, output 2). |
| C8 | P0_17 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions PG2_1 (Pattern Generator 2, output 1) and RC32k (32 kHz RC clock output, square wave). |
| C9 | P0_16 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions SDADC_REF (ΣΔ ADC reference voltage input) and RCX (RCX clock output, square wave). |
| C10 | GND_RF2 | power_in | RF ground. |
| D1 | P0_05 | bidirectional | General-purpose I/O (4/8/12/16 mA, I-PD at reset) with alternate function QSPIR_CLK (QSPI RAM clock output) and PG3_3; usable as GPIO only at 1.8 V because it is a QSPI pad. |
| D2 | P0_00 | bidirectional | General-purpose I/O (4/8/12/16 mA, I-PD at reset) with alternate functions QSPIR_D0 (QSPI RAM data I/O 0) and PG3_4; usable as GPIO only at 1.8 V because it is a QSPI pad. |
| D3 | P0_31 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions PG1_2 (Pattern Generator 1, output 2) and LCD_XRST (LCD reset for horizontal and vertical driver). |
| D4 | P0_30 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions PG1_1 (Pattern Generator 1, output 1), LCD_HST and PLCD_HSYNC. |
| D5 | P0_29 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions PG0_4 (Pattern Generator 0, output 4), LCD_HCK and PLCD_CLK. |
| D6 | P0_28 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions PG0_3 (Pattern Generator 0, output 3), LCD_VST and PLCD_VSYNC. |
| D7 | P0_27 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions PG0_2 (Pattern Generator 0, output 2), LCD_ENB and PLCD_ENAB. |
| D8 | P0_26 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions PG0_1 (Pattern Generator 0, output 1) and LCD_VCK (LCD shift clock for vertical driver). |
| D9 | P0_25 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions GPADC_1 and SDADC_1 analog inputs. |
| D10 | GND_RF1 | power_in | RF ground. |
| E1 | P0_04 | bidirectional | General-purpose I/O (4/8/12/16 mA, I-PU at reset) with alternate functions QSPIR_CS (QSPI RAM chip select, active LOW) and PG3_1; usable as GPIO only at 1.8 V because it is a QSPI pad. |
| E2 | P0_03 | bidirectional | General-purpose I/O (4/8/12/16 mA, I-PD at reset) with alternate functions QSPIR_D3 (QSPI RAM data I/O 3) and PG3_2; usable as GPIO only at 1.8 V because it is a QSPI pad. |
| E3 | VSSIOQ | power_in | QSPI ground. |
| E4 | P1_05 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_GREEN1 (LCD green image data output, bit 1). |
| E5 | P1_04 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_GREEN0 (LCD green image data output, bit 0). |
| E6 | P1_03 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_BLUE1 (LCD blue image data output, bit 1). |
| E7 | P1_02 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function LCD_BLUE0 (LCD blue image data output, bit 0). |
| E8 | P1_01 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function Timer.PWM, a timer/PWM output available in Sleep mode. |
| E9 | P1_00 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function NTC Supply, the power supply output for the battery NTC sensor. |
| E10 | XTAL32M_GND | power_in | Analog ground input of the 32 MHz XTAL oscillator. |
| F1 | P0_02 | bidirectional | General-purpose I/O (4/8/12/16 mA, I-PD at reset) with alternate functions QSPIR_D2 (QSPI RAM data I/O 2) and PG4_1; usable as GPIO only at 1.8 V because it is a QSPI pad. |
| F2 | P0_01 | bidirectional | General-purpose I/O (4/8/12/16 mA, I-PD at reset) with alternate functions QSPIR_D1 (QSPI RAM data I/O 1) and PG4_2; usable as GPIO only at 1.8 V because it is a QSPI pad. |
| F3 | VSSD4 | power_in | Digital ground. |
| F4 | VSSD3 | power_in | Digital ground. |
| F5 | AVS1 | power_in | Analog ground. |
| F6 | P1_08 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_RED1 (LCD red image data output, bit 1). |
| F7 | P1_07 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_RED0 (LCD red image data output, bit 0). |
| F8 | P1_06 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate function Timer2.PWM, the Timer2/PWM2 output available in Sleep mode. |
| F9 | XTAL32Mp | passive | Crystal input for the 32 MHz XTAL oscillator. |
| F10 | XTAL32Mm | passive | Crystal output for the 32 MHz XTAL oscillator. |
| G1 | V18F | power_out | 1.8 V power rail with maximum current 50 mA; requires a 0.1 µF decoupling capacitor and must be connected to V18P externally. |
| G2 | V18P | power_out | 1.8 V power rail with maximum current 50 mA; requires a 22 µF decoupling capacitor. |
| G3 | VSSD1 | power_in | Digital ground. |
| G4 | VSSD2 | power_in | Digital ground. |
| G5 | AVS2 | power_in | Analog ground. |
| G6 | P1_11 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function LCD_XFRP (LCD liquid crystal driving signal, 62.5 Hz inverted). |
| G7 | P1_10 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions LCD_VCOM/LCD_FRP combined output (62.5 Hz) and LCD_EXTCOMIN (1 Hz COM inversion signal input). |
| G8 | P1_09 | bidirectional | General-purpose I/O (4.8 mA / 0.15 mA reduced drive, I-PD at reset) with alternate functions GPADC_0 and SDADC_0 analog inputs. |
| G9 | XTAL32M_GND | power_in | Analog ground input of the 32 MHz XTAL oscillator. |
| G10 | XTAL32M_GND | power_in | Analog ground input of the 32 MHz XTAL oscillator. |
| H1 | V14 | power_out | 1.4 V power rail output; requires a 10 µF decoupling capacitor. |
| H2 | V18 | power_out | 1.8 V power rail with maximum current 50 mA; requires a 22 µF decoupling capacitor. |
| H3 | P1_17 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions LCD_HST and PLCD_HSYNC (LCD start signal for horizontal driver / column pointer reset). |
| H4 | P1_16 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions LCD_HCK and PLCD_CLK (LCD horizontal shift clock / parallel LCD clock). |
| H5 | P1_15 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions LCD_VST and PLCD_VSYNC (LCD vertical start / row pointer reset). |
| H6 | P1_14 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions SDADC_4 analog input, LCD_ENB and PLCD_ENAB. |
| H7 | P1_13 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions GPADC_4 analog input and LCD_VCK (LCD vertical shift clock). |
| H8 | P1_12 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function GPADC_5, the general-purpose ADC channel 5 analog input. |
| H9 | P0_22 | passive | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function XTAL32km, the analog output of the 32.768 kHz XTAL oscillator. |
| H10 | P0_23 | passive | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions XTAL32kp (analog input of the 32.768 kHz crystal oscillator) and a digital input for an external 32 kHz clock (square wave). |
| J1 | LY | passive | Connection for the external DC-DC converter inductor. |
| J2 | V12 | power_out | 1.2 V power rail output; requires a 10 µF decoupling capacitor. |
| J3 | HDRV GND | power_in | Haptic driver ground. |
| J4 | HDRVP | output | Positive haptic driver differential output. |
| J5 | VBUS | power_in | USB bus voltage input (VBUS) that is also the battery charge voltage input; absolute maximum 6.5 V and recommended range 4.2 V to 5.75 V. |
| J6 | V30 | power_out | 3.0 V power rail with maximum current 150 mA; requires a 4.7 µF decoupling capacitor. |
| J7 | P1_21 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions SDADC_6 analog input and LCD_XRST (LCD reset for horizontal and vertical driver). |
| J8 | P1_20 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function SDADC_5, the ΣΔ ADC channel 5 analog input. |
| J9 | P1_19 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function GPADC_7, the general-purpose ADC channel 7 analog input. |
| J10 | P1_18 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate function GPADC_6, the general-purpose ADC channel 6 analog input. |
| K1 | LX | passive | Connection for the external DC-DC converter inductor. |
| K2 | VBAT2 | power_in | Battery connection 2 for the DC-DC converter supply; recommended supply range 2.4 V to 4.75 V. |
| K3 | BUCK GND | power_in | DC-DC converter ground. |
| K4 | HDRVM | output | Negative haptic driver differential output. |
| K5 | VBAT1 | power_in | Battery connection 1 for the LDO supply; recommended supply range 2.4 V to 4.75 V. |
| K6 | P0_14 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset, no state retention in power down) with alternate functions USBp (USB Full Speed D+) and XTAL32k (XTAL32k clock output, square wave). |
| K7 | P0_15 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset, no state retention in power down) with alternate functions USBm (USB Full Speed D-) and DIVN (DIVN clock output, square wave). |
| K8 | P1_22 | bidirectional | General-purpose I/O (4.8 mA, I-PD at reset) with alternate functions SDADC_7 analog input and LCD_TE (LCD tearing effect input). |
| K9 | LED2 | output | LED 2 driver output, open drain, 20 mA maximum. |
| K10 | LED1 | output | LED 1 driver output, open drain, 20 mA maximum. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | RENESAS |
| Package | VFBGA-100 |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 100 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Limiting voltage on a pin | VPIN_LIM_DEF | -0.1 |  | 3.6 | V | Default, unless otherwise specified | 65 |
| Limiting battery supply voltage | VBAT_LIM | 0 |  | 6 | V | Pin VBAT | 65 |
| Limiting bus supply voltage | VBUS_LIM | 0 |  | 6.5 | V | Pin VBUS | 65 |
| Limiting voltage on a pin | VPIN_LIM_3V0 | 0 |  | 3.45 | V | 3.0 V I/O pins | 65 |
| Limiting voltage on a pin | VPIN_LIM_1V8 | 0 |  | 1.98 | V | 1.8 V I/O pins | 65 |
| Electrostatic discharge voltage (Human Body Model) | VESD_HBM_BGA100 |  |  | 2200 | V | VFBGA100 package | 65 |
| Electrostatic discharge voltage (Charged Device Model) | VESD_CDM_BGA100 |  |  | 500 | V | VFBGA100 package | 65 |
| Storage temperature | TSTG | -50 |  | 150 | °C |  | 65 |
| Power supply rise time | tR_SUP |  |  | 30 | ms |  | 65 |
| Battery supply voltage | VBAT | 2.4 |  | 4.75 | V | Pin VBAT1 and VBAT2 | 65 |
| Bus supply voltage | VBUS | 4.2 |  | 5.75 | V | Pin VBUS | 65 |
| Voltage on a pin | VPIN_3V0 | 0 |  | 3 | V | 3.0 V I/O pins | 65 |
| Voltage on a pin | VPIN_1V8 | 0 |  | 1.8 | V | 1.8 V I/O pins | 65 |
| Ambient temperature | TA | -40 |  | 85 | °C |  | 65 |
| Thermal resistance (junction to ambient) | RθJA_P2_HR |  | 48.8 |  | ºC/W | VFBGA100 package. JEDEC PCB, 0.1W+0.3W Power map | 69 |
| LOW level input current with pull-up | IIL_PU_RSTN | -75 |  | -25 | μA | Pin RESETn, VI = 0.0 V | 69 |
| Bandgap reference voltage from GPADC reference buffer | VBG_REF | 1.14 | 1.2 | 1.26 | V |  | 69 |
| Internal bandgap reference trim test current | IBG_IREF_CUR_TRIM | 13 | 15 | 16 | μA |  | 69 |
| Reset voltage | VRST_VDD_sleep | 0.67 | 0.7 | 0.73 | V | BOD_LVL_VDD_RET = 0x6F | 69 |
| Reset voltage | VRST_VDD | 1.02 | 1.05 | 1.08 | V | BOD_LVL_VDD_ON = 0xA7 | 69 |
| Reset voltage | VRST_V14 | 1.21 | 1.25 | 1.29 | V | BOD_LVL_V14 = 0xC7 | 69 |
| Reset voltage | VRST_V18P | 1.61 | 1.65 | 1.69 | V | BOD_LVL_V18P = 0x107 | 69 |
| Reset voltage | VRST_V30 | 1.91 | 1.95 | 1.99 | V | BOD_LVL_V30 = 0x137 | 69 |
| Reset voltage | VRST_VBAT | 2.24 | 2.3 | 2.36 | V | BOD_LVL_VBAT = 0xF4 | 70 |
| Gain error without calibration | EG | -3 |  | 3 | % | Trimmed bandgap | 70 |
| Gain error after calibration | EG_CALIBRATED | -1 |  | 1 | % | Trimmed bandgap & Gain Error + Offset correction applied | 70 |
| Offset error without calibration | EOFS | -20 |  | 20 | LSB | Trimmed bandgap; LSB wrt 10bit accuracy | 70 |
| Offset error after calibration | EOFS_CALIBRATED | -7 |  | 4 | LSB | Trimmed bandgap & Gain Error + Offset correction applied; LSB wrt 10bit accuracy | 70 |
| Gain error of the 3x attenuator | EG_ATTN3x | -4 |  | 1 | % | Trimmed bandgap & GPADC Gain Error + Offset correction applied | 70 |
| Integral non-linearity | INL | -2 |  | 2 | LSB | LSB wrt 10bit accuracy | 70 |
| Differential non-linearity | DNL | -2 |  | 2 | LSB | LSB wrt 10bit accuracy | 70 |
| Gain error | EG_ext_ref | -0.25 |  | 0.25 | % | Using external voltage reference 1.2 V | 71 |
| Integral non-linearity | INL_ext_ref | -4 |  | 4 | LSB | LSB wrt 14b accuracy | 71 |
| Differential non-linearity | DNL_ext_ref | -4 |  | 4 | LSB | LSB wrt 14b accuracy | 71 |
| Offset error | EOFS_ext_ref | -2 |  | 2 | LSB | LSB wrt 14b accuracy. Using external voltage reference 1.2 V | 71 |
| VDD1V2 Output Voltage | VO_1V2_0 | 0.85 | 0.9 | 0.95 | V | VDD_LEVEL = 0 | 72 |
| VDD1V2 Output Voltage | VO_1V2_1 | 0.95 | 1 | 1.05 | V | VDD_LEVEL = 1 | 72 |
| VDD1V2 Output Voltage | VO_1V2_2 | 1.05 | 1.1 | 1.15 | V | VDD_LEVEL = 2 | 72 |
| VDD1V2 Output Voltage | VO_1V2_3 | 1.15 | 1.2 | 1.25 | V | VDD_LEVEL = 3 | 72 |
| VDD1V4 Output Voltage | VO_1V4_0 | 1.15 | 1.2 | 1.25 | V | V14_LEVEL = 0 | 72 |
| VDD1V4 Output Voltage | VO_1V4_1 | 1.2 | 1.25 | 1.3 | V | V14_LEVEL = 1 | 72 |
| VDD1V4 Output Voltage | VO_1V4_2 | 1.25 | 1.3 | 1.35 | V | V14_LEVEL = 2 | 72 |
| VDD1V4 Output Voltage | VO_1V4_3 | 1.3 | 1.35 | 1.4 | V | V14_LEVEL = 3 | 72 |
| VDD1V4 Output voltage | VO_1V4_4 | 1.35 | 1.4 | 1.45 | V | V14_LEVEL = 4 | 72 |
| VDD1V4 Output Voltage | VO_1V4_5 | 1.4 | 1.45 | 1.5 | V | V14_LEVEL = 5 | 72 |
| VDD1V4 Output Voltage | VO_1V4_6 | 1.45 | 1.5 | 1.55 | V | V14_LEVEL = 6 | 72 |
| VDD1V4 Output Voltage | VO_1V4_7 | 1.5 | 1.55 | 1.6 | V | V14_LEVEL = 7 | 72 |
| VDD1V8 Output Voltage | VO_1V8_0 | 1.1 | 1.2 | 1.25 | V | V18_LEVEL = 0 | 72 |
| VDD1V8 Output Voltage | VO_1V8_1 | 1.7 | 1.8 | 1.9 | V | V18 LEVEL = 1 | 72 |
| VDD1V8P Output Voltage | VO_1V8P | 1.7 | 1.8 | 1.9 | V |  | 72 |
| LDO output voltage | VLDO_1v8_0 | 1.14 | 1.2 | 1.25 | V |  | 74 |
| LDO output voltage | VLDO_1v8_1 | 1.7 | 1.8 | 1.9 | V |  | 74 |
| LDO output voltage | VLDO_CORE_0 | 0.85 | 0.9 | 0.95 | V | V30 = 3.0 V; ILOAD = 1 mA | 76 |
| LDO output voltage | VLDO_CORE_1 | 0.95 | 1 | 1.05 | V | V30 = 3.0 V; ILOAD = 1 mA | 76 |
| LDO output voltage | VLDO_CORE_2 | 1.04 | 1.1 | 1.16 | V | V30 = 3.0 V; ILOAD = 1 mA | 76 |
| LDO output voltage | VLDO_CORE_3 | 1.14 | 1.2 | 1.26 | V | V30 = 3.0 V; ILOAD = 1 mA | 76 |

## CAD (KiCad official)

- Symbol: `DA14697-00000HR2`
- Footprint: `Package_BGA:VFBGA-100_7.0x7.0mm_Layout10x10_P0.65mm`
- 3D model: VFBGA-100 (KiCad packages3D, STEP)
- 3D model files: `da14697-00000hr2-etched.step` / `da14697-00000hr2-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `da14697-00000hr2.step` / `da14697-00000hr2.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [RENESAS datasheet](docs/da14697-00000hr2-datasheet.pdf) (757 pp, sha256 `078a98fd8552338d`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/da14697-00000hr2-datasheet.pdf)

DA14697-00000HR2

Verified DA14697-00000HR2

Verification log 1 record

DA14697-00000HR2

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance