component
D706TF
Public Made by Adomby adom
Silicore(芯谷) , SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownD706TF
Silicore(芯谷) · IC · SOP-8
D706TF from Silicore(芯谷), in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | MR | input | Active-LOW manual reset input that triggers a reset pulse, with a 250µA pull-up (MR = 0V pull-up current 100 to 250 to 600 µA), VIH min 2.0 V and VIL max 0.8 V. |
| 2 | VCC | power_in | +5V power supply input; operating voltage range 1.2 V to 5.5 V, and absolute maximum supply voltage is -0.3 V to +6.0 V. |
| 3 | GND | power_in | Ground reference for all signals. |
| 4 | PFI | input | Power-fail voltage monitor input; PFO goes low when PFI is below 1.25 V (1.20 to 1.30 V threshold), and PFI should be connected to ground or VCC when not used. |
| 5 | PFO | output | Active-LOW power-fail output that sinks current when PFI is below 1.25 V, with VOL max 0.4 V at 3.2 mA sink. |
| 6 | WDI | input | Watchdog input that controls the internal watchdog timer; transitions as short as 50 ns clear the timer, and the input threshold is VIH 3.5 V and VIL 0.8 V at VCC = 5 V. |
| 7 | RESET | output | Active-LOW reset output that stays low while VCC is below the reset threshold (3.08 V for D706T) and remains low for the reset pulse width after VCC rises above the threshold or MR goes high. |
| 8 | WDO | output | Watchdog output that pulls LOW when the 1.6 s watchdog timer times out and stays low while VCC is below the reset threshold, returning HIGH without delay once VCC exceeds the threshold. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Silicore(芯谷) |
| Package | SOP-8 |
| Category | |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating voltage range | Vcc | 1.2 | 5.5 | V | D706/T/S | 4 | |
| Supply current | Icc | 75 | 140 | µA | D706/T/S | 4 | |
| RESET threshold | VRT | 2.98 | 3.08 | 3.15 | V | D706T | 4 |
| RESET pulse width | tRS | 140 | 200 | 280 | ms | 4 | |
| MR pulse width | tMR | 0.15 | µs | 4 | |||
| MR to RESET out delay | tMD | 0.25 | µs | 4 | |||
| MR input threshold high | VIH | 2 | V | 4 | |||
| MR input threshold low | VIL | 0.8 | V | 4 | |||
| MR pull-up current | 100 | 250 | 600 | µA | MR =0V | 4 | |
| RESET output voltage (low) | 0.4 | V | ISINK =3.2mA | 4 | |||
| RESET output voltage (low) at low Vcc | 0.3 | V | D706/T/S, Vcc=1.2 V, ISINK =100µA | 4 | |||
| Watchdog timeout period | tWD | 1 | 1.6 | 2.25 | s | D706/T/S | 4 |
| WDI pulse width | tWP | 50 | ns | VIL =0.4V, VIH =0.8Vcc | 4 | ||
| WDI input threshold high | VIH | 3.5 | V | D706/T/S, Vcc=5V | 4 | ||
| WDI input threshold low | VIL | 0.8 | V | 4 | |||
| WDI input current (WDI=Vcc) | 50 | 150 | µA | D706/T/S, WDI=Vcc | 4 | ||
| WDI input current (WDI=0V) | -150 | -50 | µA | D706/T/S, WDI=0V | 4 | ||
| WDO output voltage (low) | 0.4 | V | D706/T/S, ISINK =1.2mA | 4 | |||
| PFI input threshold | 1.2 | 1.25 | 1.3 | V | Vcc=5V | 4 | |
| PFI input current | -25 | 0.01 | 25 | nA | 4 | ||
| PFO output voltage (low) | 0.4 | V | ISINK =3.2mA | 4 | |||
| Supply voltage | -0.3 | 6 | V | 3 | |||
| All other inputs | -0.3 | V | 3 | ||||
| Input current at Vcc and GND | 20 | mA | 3 | ||||
| Output current (all outputs) | 20 | mA | 3 | ||||
| Rate of rise at Vcc | 100 | V/µs | 3 | ||||
| SOP power dissipation | 470 | mW | Derate 5.9mW/℃ above 70℃ | 3 | |||
| Operating temperature range | 0 | 70 | ℃ | 3 | |||
| Storage temperature range | -65 | 150 | ℃ | 3 | |||
| Lead temperature (soldering, 10 sec) | 300 | ℃ | Soldering, 10 sec | 3 | |||
| RESET threshold hysteresis | 40 | mV | 4 |
CAD (KiCad official)
- Symbol:
D706TF - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
d706tf-etched.step/d706tf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);d706tf.step/d706tf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Silicore(芯谷) datasheet (12 pp, sha256
446c69db8a7c2a24, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).