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D5V0P4URL6SO-7

Diodes Incorporated · ESD And Surge Protection (TVS/ESD) · SOT-26

D5V0P4URL6SO-7 from Diodes Incorporated, in a SOT-26. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 I/O1 passive ESD-protected I/O channel 1 for a high-speed line, clamped to VSS with a typical 2.4pF channel capacitance.
2 VSS power_in Common ground reference for all four TVS channels, to which I/O pins clamp (reverse working voltage 3.3V max, I/O to VSS).
3 I/O2 passive ESD-protected I/O channel 2 for a high-speed line, clamped to VSS with a typical 2.4pF channel capacitance.
4 I/O3 passive ESD-protected I/O channel 3 for a high-speed line, clamped to VSS with a typical 2.4pF channel capacitance.
5 N/A unconnected Not used; labeled N/A on the device schematic and has no internal connection shown.
6 I/O4 passive ESD-protected I/O channel 4 for a high-speed line, clamped to VSS with a typical 2.4pF channel capacitance.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-26
Category Circuit Protection
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Reverse Working Voltage VRWM 3.3 V IR=1mA, I/O to VSS 2
Reverse Current IR 1 μA VR = 3.3V, I/O to VSS 2
Reverse Breakdown Voltage VBR 4.5 8 V IR = 1mA, I/O to VSS 2
Forward Clamping Voltage VF 0.8 1.2 V IF = 15mA, VSS to I/O 2
Reverse Clamping Voltage VC 6 V IPP = 5A, I/O to VSS, 8/20µs 2
ESD Clamping Voltage VESD 7.5 V TLP, 12A, tP = 100ns, I/O to VSS 2
Dynamic Reverse Resistance RDIF-R 0.15 Ω TLP, 12A, tP = 100ns, I/O to VSS 2
Channel Input Capacitance CI/O 2.4 3 pF VI/O = 1.65V, VSS = 0V, f = 1MHz 2
Delta Channel Input Capacitance CI/OMAX-CI/OMIN 0.04 pF CI/OMAX-CI/OMIN 2
Peak Pulse Current, per IEC 61000-4-5 IPP 20 A I/O to VSS, 8/20µs 2
Peak Pulse Power, per IEC 61000-4-5 PPP 180 W I/O to VSS, 8/20µs 2
ESD Protection, Contact Discharge, per IEC 61000-4-2 VESD_CONTACT 30 kV I/O to VSS 2
ESD Protection, Air Discharge, per IEC 61000-4-2 VESD_AIR 30 kV I/O to VSS 2
Storage Temperature TSTG -55 150 °C 2
Operating Temperature TOP -55 85 °C 2
Power Dissipation PD 300 mW Typical, device mounted on FR-4 PCB pad layout (2oz copper) 2
Thermal Resistance, Junction to Ambient RθJA 417 °C/W Typical, device mounted on FR-4 PCB pad layout (2oz copper) 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin  Terminal Connections: See Schematic  Terminals, Finish, Matte Tin Pleated Leadframe. 1

CAD (KiCad official)

  • Symbol: D5V0P4URL6SO-7
  • Footprint: Package_TO_SOT_SMD:SOT-23-6
  • 3D model: SOT-26 (KiCad packages3D, STEP)
  • 3D model files: d5v0p4url6so-7-etched.step / d5v0p4url6so-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); d5v0p4url6so-7.step / d5v0p4url6so-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (5 pp, sha256 8fdf8d024c55e83e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF