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Contents

README

markdown

D3V3M1U2S9-7

Diodes Incorporated · ESD Protection Devices · SOD-923

D3V3M1U2S9-7 from Diodes Incorporated, in a SOD-923. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CATHODE passive Pin 1 is the cathode side, marked by the line on the package outline, and the device clamps ESD transients per IEC 61000-4-2 at ±30 kV contact and ±30 kV air with a 3.3 V reverse standoff voltage.
2 ANODE passive Pin 2 is the opposite terminal of this unidirectional TVS, with a channel input capacitance of 70 pF typical and 80 pF maximum at VR = 0 V, f = 1 MHz.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOD-923
Category TVS/Fuse/Board Level Protection
Pins 2

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Reverse Standoff Voltage VRWM 3.3 V 2
Channel Leakage Current IRM 2 μA VRWM = 3.3V 2
Clamping Voltage, IEC 61000-4-5 VCL 8 V IPP = 1A, tp = 8/20μS 2
Clamping Voltage, IEC 61000-4-5 VCL 10 V IPP = 12A, tp = 8/20μS 2
Breakdown Voltage VBR 5 V IR = 1mA 2
Channel Input Capacitance CT 70 80 pF VR = 0V, f = 1MHz 2
Peak Pulse Power Dissipation PPP 120 W 8/20µs, Figure 3 1
Peak Pulse Current IPP 12 A 8/20µs, Figure 3 1
ESD Protection, Contact Discharge VESD_Contact -30 30 kV IEC 61000-4-2 Standard 1
ESD Protection, Air Discharge VESD_Air -30 30 kV IEC 61000-4-2 Standard 1
Package Power Dissipation PD 250 mW Note 5: FR-4 PCB, 2oz copper, pad layout AP02001 2
Thermal Resistance, Junction to Ambient RJA 500 °C/W Note 5: FR-4 PCB, 2oz copper, pad layout AP02001 2
Operating and Storage Temperature Range TJ, TSTG -65 150 °C 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin  Terminals: Matte Tin Finish Annealed over Alloy 42 Leadframe (Lead Free Plating). Solderable per MIL-STD-202, Method 208 1

CAD (KiCad official)

  • Symbol: D3V3M1U2S9-7
  • Footprint: Diode_SMD:D_SOD-923
  • 3D model: SOD-923 (KiCad packages3D, STEP)
  • 3D model files: d3v3m1u2s9-7-etched.step / d3v3m1u2s9-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); d3v3m1u2s9-7.step / d3v3m1u2s9-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (5 pp, sha256 709ce5f8394a1f02, retrieved 2026-10-21, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF