component

D3V3F4U6S-7

Public Made by Adom

by adom

Diodes Incorporated ESD And Surge Protection (TVS/ESD), SOT-363. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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D3V3F4U6S-7

Diodes Incorporated · ESD And Surge Protection (TVS/ESD) · SOT-363

D3V3F4U6S-7 from Diodes Incorporated, in a SOT-363. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CH1 passive ESD-protected channel 1 input for high-speed data lines, with 0.85pF typical channel capacitance.
2 VN power_in Negative (ground) reference pin of the TVS array; leakage and capacitance are measured from the other pins to pin 2.
3 CH2 passive ESD-protected channel 2 input for high-speed data lines, with 0.85pF typical channel capacitance.
4 CH3 passive ESD-protected channel 3 input for high-speed data lines, with 0.85pF typical channel capacitance.
5 VP passive Positive reference pin of the TVS array, connected to the internal TVS diode, with a reverse working voltage of 3.3V maximum.
6 CH4 passive ESD-protected channel 4 input for high-speed data lines, with 0.85pF typical channel capacitance.

Key specifications

Parameter Value
Manufacturer Diodes Incorporated
Package SOT-363
Category Circuit Protection
Pins 6

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Reverse Working Voltage VRWM 3.3 V 2
Reverse Current IR 200 nA VR = 3.3V 2
Reverse Breakdown Voltage VBR 6 V IR = 1mA 2
Forward Voltage VF 0.6 0.8 0.95 V IF = 8mA 2
Capacitance CT 0.85 1.2 pF VR = 1.65V, f = 1MHz 2
Peak Pulse Current IPP 5 A 8/20µs, Per Figure 3 2
ESD Protection, Contact Discharge VESD_Contact -8 8 kV Standard IEC 61000-4-2 2
ESD Protection, Air Discharge VESD_Air -15 15 kV Standard IEC 61000-4-2 2
Power Dissipation PD 200 mW Note 5 (FR-4 PCB pad layout, 2oz copper) 2
Operating and Storage Temperature Range TJ, TSTG -55 150 °C 2
Thermal Resistance, Junction to Ambient RθJA 625 °C/W Note 5 (FR-4 PCB pad layout, 2oz copper) 2
Reverse Clamping Voltage, Positive Transients VCL1 10 V IPP = 1A, tp = 8/20μs 2
Reverse Clamping Voltage, Negative Transients VCL2 -1.7 V IPP = -1A, tp = 8/20μs 2
Dynamic Resistance RDYN 0.9 IR = 1A, tp = 8/20μs 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts tin  Terminals: Matte Tin Finish annealed over Alloy 42 leadframe (Lead Free Plating) solderable per MIL-STD-202, Method 208 1

CAD (KiCad official)

  • Symbol: D3V3F4U6S-7
  • Footprint: Package_TO_SOT_SMD:SOT-363_SC-70-6
  • 3D model: SOT-363 (KiCad packages3D, STEP)
  • 3D model files: d3v3f4u6s-7-etched.step / d3v3f4u6s-7-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); d3v3f4u6s-7.step / d3v3f4u6s-7.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Diodes Incorporated datasheet (4 pp, sha256 af7ef219ca3ddf6a, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF