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D3121F

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by adom

Silicore Isolation Amplifiers, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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docs d3121f: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
viewers d3121f: viewers · Ray
d3121f-etched.fit.json d3121f: re-etch, flat white mark read from pin 1 (service-occt 1.4.0) + chip hero · Ray
d3121f-etched.glb d3121f: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body with… · Ray
d3121f-etched.step d3121f: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body with… · Ray
d3121f.glb Publish 0.1.0 · Ray
d3121f.kicad_mod Publish 0.1.0 · Ray
d3121f.kicad_sym Publish 0.1.0 · Ray
d3121f.lbr Publish 0.1.0 · Ray
d3121f.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json d3121f: white body in tscircuit (pre-1.8 etch structure under an assembly instance); Ray 2026-10-19: black IC body with… · Ray
README.md d3121f: specified limits as data (metadata.characteristics, 16 rows from the datasheet) · Ray

D3121F

Silicore · Isolation Amplifiers · SOP-8

D3121F from Silicore, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT1 output Channel 1 audio output. AC-coupled (typ. 4.7 uF) to the downstream power amplifier stage. Output is inverted with unity voltage gain (Gv = -0.04 dB typical) relative to IN1.
2 Vm1 passive Channel 1 mid-bias / ripple-filter node. An external electrolytic capacitor (typ. 22 uF) is connected from this pin to GND to set the internal bias reference and stabilize ripple rejection. The Vm1:Vm2 external cap ratio should be kept at 2:1 for stable ripple rejection.
3 IN1 input Channel 1 audio signal input from the tape deck / tuner. AC-coupled through an external electrolytic capacitor (typ. 4.7 uF). Input resistance RIN = 55 kΩ typical (44-66 kΩ).
4 GND power_in Signal / device ground reference. Connected to the car-body / chassis ground at the source-end (tape deck / tuner) side, exploiting the on-chip op-amp CMRR to cancel body-noise voltage between the two ground references.
5 IN2 input Channel 2 audio signal input from the tape deck / tuner. AC-coupled through an external electrolytic capacitor (typ. 4.7 uF). Input resistance RIN = 55 kΩ typical (44-66 kΩ).
6 Vm2 passive Channel 2 mid-bias / ripple-filter node. An external electrolytic capacitor (typ. 10 uF) is connected from this pin to GND. The Vm1:Vm2 external cap ratio should be kept at 2:1 (e.g. 22 uF : 10 uF) for stable ripple rejection.
7 OUT2 output Channel 2 audio output. AC-coupled (typ. 4.7 uF) to the downstream power amplifier stage. Output is inverted with unity voltage gain (Gv = -0.04 dB typical) relative to IN2.
8 Vcc power_in Positive supply voltage. Recommended operating range 4-18 V (typ. 12 V); absolute maximum 18 V. Quiescent current IQ = 9 mA typ. (5.6-14 mA). Bypass with a 47 Ω series resistor and 220 uF electrolytic per the test/application circuit.

Key specifications

Parameter Value
Manufacturer Silicore
Package SOP-8
Category Op-amp/Cmp
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • D3121FF
  • D3121F
  • D3121FN

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage Vcc 18 V 3
Power dissipation (D3121F) PD 450 mW Ta=25C; reduce 4.5mW per C above 25C 3
Operating temperature Topr -30 85 C 3
Storage temperature Tstg -55 125 C 3
Supply voltage Vcc 4 12 18 V Ta=25C 3
Quiescent current IQ 5.6 9 14 mA VIN=0Vrms 3
Output noise voltage VNO 3.5 8 μVrms BPF=20Hz～20KHz 3
Voltage gain GV -1.5 -0.04 1.5 dB Vo=-10dBm,Rg=0Ω 3
Maximum output voltage VOM 1.8 2 Vrms THD=0.1%,Vcc=8V 3
Total harmonic distortion THD 0.002 0.02 % Vo=0.7Vrms 3
Common mode rejection ratio CMRR 41 57 dB 3
Common mode voltage VCM 2.5 3.75 Vrms Vcc=8V,CMRR=40dB 3
Ripple rejection ratio RR 72 80 dB fRR=100Hz, Rg=0Ω, VRR=-10dBm 3
Input resistance RIN 44 55 66 KΩ 3
Channel separation CS 82 dB VIN=-10dBm, Rg=1.8KΩ/OPEN 3
Slew rate SR 2 V/μs 3

CAD (KiCad official)

  • Symbol: D3121F
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: d3121f-etched.step / d3121f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); d3121f.step / d3121f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Silicore datasheet (None pp, sha256 c9d5278c4698f7d7, retrieved 2026-08-17, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF