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D1302F

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Silicore(芯谷) Real Time Clocks, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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D1302F

Silicore(芯谷) · Real Time Clocks · SOP-8

D1302F from Silicore(芯谷), in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC2 power_in Primary supply pin in the dual-supply configuration (recommended supply 2.0V to 5.5V); the D1302 runs from the larger of VCC1 or VCC2, and VCC2 powers the device when it is more than 0.2V above VCC1.
2 X1 passive Connection for a standard 32.768kHz quartz crystal with a specified load capacitance of 6pF; when the device is driven by an external 32.768kHz oscillator, this pin receives the oscillator signal.
3 X2 passive Second connection for the 32.768kHz quartz crystal; it is left floating when the device is driven by an external 32.768kHz oscillator.
4 GND power_in Ground reference for the device.
5 RST input Reset input that must be driven high during any read or write and is not to be driven high while SCLK is at logic 1; it has a 40kΩ internal pull-down and a low level terminates all transfers and tri-states I/O.
6 I/O bidirectional Bidirectional data pin for the 3-wire serial interface, with a 40kΩ internal pull-down resistor.
7 SCLK input Serial clock input that synchronizes data movement on the serial interface, with a 40kΩ internal pull-down resistor; it must be at logic 0 when RST is driven high.
8 VCC1 power_in Backup supply for low-power operation and battery backup that maintains time and date when VCC2 is absent; a trickle-charge source connects here, and UL recognition covers protection against reverse charging current with a lithium battery.

Key specifications

Parameter Value
Manufacturer Silicore(芯谷)
Package SOP-8
Category Clock/Timing
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage VCC1, VCC2 2 5.5 V 3
Logic 1 Input VIH 2 V 3
Logic 0 Input VIL -0.3 0.3 V VCC=2.0V 3
Logic 0 Input VIL -0.3 0.8 V VCC=5.0V 3
Input Leakage ILI 500 μA 4
I/O Leakage ILO 500 μA 4
Logic 1 Output VOH 1.6 V IOH = -0.4mA, VCC =2.0V 4
Logic 1 Output VOH 2.4 V IOH = -1.0mA, VCC =5V 4
Logic 0 Output VOL 0.4 V IOL = 1.5mA, VCC =2.0V 4
Active Supply Current (VCC1) ICC1A 0.4 mA VCC =2.0V 4
Active Supply Current (VCC1) ICC1A 1.2 mA VCC=5V 4
Timekeeping Current (OSC On) (VCC1) ICC1T 0.3 μA VCC =2.0V 4
Timekeeping Current (OSC On) (VCC1) ICC1T 1 μA VCC =5V 4
Standby Current (OSC Off) (VCC1) ICC1S 100 nA VCC=2.0V 4
Standby Current (OSC Off) (VCC1) ICC1S 200 nA IND 4
Active Supply Current (VCC2) ICC2A 0.425 mA VCC2 =2.0V 4
Active Supply Current (VCC2) ICC2A 1.28 mA VCC2 =5.0V 4
Timekeeping Current (OSC On) (VCC2) ICC2T 25.3 μA VCC2 =2.0V 4
Timekeeping Current (OSC On) (VCC2) ICC2T 81 μA VCC2 =5.0V 4
Standby Current (OSC Off) (VCC2) ICC2S 25 μA VCC2 =2.0V 4
Standby Current (OSC Off) (VCC2) ICC2S 80 μA VCC2 =5.0V 4
Data to CLK Setup tDC 200 ns VCC=2.0V 5
Data to CLK Setup tDC 50 ns VCC=5V 5
CLK to Data Hold tCDH 280 ns VCC=2.0V 5
CLK to Data Hold tCDH 70 ns VCC=5V 5
CLK to Data Delay tCDD 800 ns VCC=2.0V 5
CLK to Data Delay tCDD 200 ns VCC=5V 5
CLK Low Time tCL 1000 ns VCC=2.0V 5
CLK Low Time tCL 250 ns VCC=5V 5
CLK High Time tCH 1000 ns VCC=2.0V 5
CLK High Time tCH 250 ns VCC=5V 5
CLK Frequency tCLK 0.5 MHz VCC=2.0V 5
CLK Frequency tCLK 2 MHz VCC=5V 5
CLK Rise and Fall tR , tF 2000 ns VCC=2.0V 5
CLK Rise and Fall tR , tF 500 ns VCC=5V 5
RST to CLK Setup tCC 4 μs VCC=2.0V 5
RST to CLK Setup tCC 1 μs VCC=5V 5
CLK to RST Hold tCCH 240 ns VCC=2.0V 5
CLK to RST Hold tCCH 60 ns VCC=5V 5
RST Inactive Time tCWH 4 μs VCC=2.0V 5
RST Inactive Time tCWH 1 μs VCC=5V 5
RST to I/O High-Z tCDZ 280 ns VCC=2.0V 5
RST to I/O High-Z tCDZ 70 ns VCC=5V 5
SCLK to I/O High-Z tCCZ 280 ns VCC=2.0V 5
SCLK to I/O High-Z tCCZ 70 ns VCC=5V 5
Voltage on Any Pin Relative to Ground Vpin -0.5 7 V 3
Storage Temperature Tstg -55 125 ℃ 3
Soldering Temperature (10Sec) Tjm 260 ℃ 10 s 3
Optional Temperature Range Topr -40 85 ℃ 3

CAD (KiCad official)

  • Symbol: D1302F
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: d1302f-etched.step / d1302f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); d1302f.step / d1302f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Silicore(芯谷) datasheet (14 pp, sha256 08e40c1575476bb7, retrieved 2026-11-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF