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CYW20721B2KUMLGT

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Infineon Technologies RF Transceiver ICs, QFN-40(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CYW20721B2KUMLGT

Infineon Technologies · RF Transceiver ICs · QFN-40(5x5)

CYW20721B2KUMLGT from Infineon Technologies, in a QFN-40(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P28 bidirectional GPIO P28 with A/D converter input 11 and 16 mA sink current; supermux-programmable to the alternate functions in Tables 6 and 7.
2 P29 bidirectional GPIO P29 with A/D converter input 10 and 16 mA sink current; supermux-programmable to the alternate functions in Tables 6 and 7.
3 P0 bidirectional GPIO P0 that also serves as keyboard scan input KSI0 and A/D converter input 29; supermux I/O functions as defined in Table 6.
4 P1 bidirectional GPIO P1 that also serves as keyboard scan input KSI1 and A/D converter input 28; supermux I/O functions as defined in Table 6.
5 P34 bidirectional GPIO P34 with A/D converter input 5; supermux I/O functions as defined in Table 6.
6 P38 bidirectional GPIO P38 with A/D converter input 1; supermux I/O functions as defined in Table 6.
7 P26 bidirectional GPIO P26 with 16 mA sink current; supermux I/O functions as defined in Table 6.
8 P25 bidirectional GPIO P25; supermux I/O functions as defined in Table 6.
9 P33 bidirectional GPIO P33 with A/D converter input 6; supermux I/O functions as defined in Table 6.
10 RST_N input Active-low system reset input with internal pull-up resistor; I/O power domain VDDO.
11 JTAG_SEL passive Reserved Arm JTAG debug mode control; connect to GND for all applications.
12 SR_VLX power_out Core buck regulator output.
13 SR_VDDBAT3V power_in Core buck input supply.
14 RFLDO_VDDOUT power_out RF LDO output.
15 RFLDO_VDDIN power_in RF LDO input.
16 DIGLDO_VDDIN power_in Internal digital LDO input.
17 BT_PAVDD power_in PA supply.
18 BT_RF passive RF antenna port.
19 BT_IFVDD1P2 power_in IFPLL power supply (1.2 V domain).
20 BT_VCOVDD1P2 power_in VCO supply (1.2 V domain).
21 BT_PLLVDD1P2 power_in RFPLL and crystal oscillator supply (1.2 V domain).
22 BT_XTALI input Crystal oscillator input; the XTAL must have an accuracy of ±20 ppm per the Bluetooth specification and two external load capacitors are required, selected per the XTAL (see Figure 2).
23 BT_XTALO output Crystal oscillator output.
24 BT_HOST_WAKE output Signal from the CYW20721 to the host indicating that the Bluetooth device requires attention; I/O power domain VDDO.
25 BT_VDDO power_in I/O pad power supply; I/O power domain VDDO.
26 Reserved unconnected Reserved; leave unconnected.
27 BT_UART_RXD input UART serial input; serial data input for the HCI UART interface, I/O power domain VDDO.
28 BT_UART_TXD output UART serial output; serial data output for the HCI UART interface, with pull-up (PU) on the I/O power domain VDDO.
29 BT_UART_RTS_N output Request to send (RTS) for the HCI UART interface, with pull-up (PU); leave unconnected if not used.
30 BT_UART_CTS_N input Clear to send (CTS) for the HCI UART interface, with pull-up (PU); leave unconnected if not used.
31 XTALO_32K output Low-power oscillator output; I/O power domain VDDO.
32 XTALI_32K / P15 input Low-power oscillator input (XTALI_32K) that is shared with GPIO P15 (A/D converter input 20); P15 should not be driven high externally while the part is held in reset.
33 P16 bidirectional GPIO P16 with A/D converter input 19; supermux I/O functions as defined in Table 6.
34 P2 bidirectional GPIO P2 with keyboard scan input KSI2; supermux I/O functions as defined in Table 6.
35 P4 bidirectional GPIO P4 with keyboard scan input KSI4; supermux I/O functions as defined in Table 6.
36 P6 bidirectional GPIO P6 with keyboard scan input KSI6; supermux I/O functions as defined in Table 6.
37 P7 bidirectional GPIO P7 with keyboard scan input KSI7; supermux I/O functions as defined in Table 6.
38 P17 bidirectional GPIO P17 with A/D converter input 18; supermux I/O functions as defined in Table 6.
39 VDDO power_in LHL pad power supply; can be tied to BT_VDDO.
40 P10 bidirectional GPIO P10 with keyboard scan output KSO2 and A/D converter input 25; supermux I/O functions as defined in Table 6.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package QFN-40(5x5)
Category Radio Frequency Chip/Antenna
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Maximum Junction Temperature 125 °C 29
VDD IO (BT_VDDO, VDDO_0) -0.5 3.795 V 29
VDD RF (BT_IFVDD1p2, BT_PLLVDD1p2, BT_VCOVDD1p2, BT_PAVDD) -0.5 1.38 V 29
VDDBAT3V/SR_VDDBAT3V -0.5 3.795 V 29
DIGLDO_VDDIN1P5 -0.5 1.65 V 29
RFLDO_VDDIN1P5 -0.5 1.5 V 29
MIC_AVDD -0.5 3.795 V 29
BT_RF 0 dBm 29
ESD Tolerance HBM -2000 2000 V 29
ESD Tolerance CDM -500 500 V 29
Operating Temperature -30 85 °C 29
Storage Temperature -40 150 °C 29
VDDIO (BT_VDDO, VDDO_0) 1.76 3 3.63 V 29
VDDBAT3V/SR_VDDBAT3V 1.76 3 3.63 V 29
MIC_AVDD 1.76 3 3.63 V 29
Input supply voltage (Core Buck Regulator) 1.76 3 3.63 V DC, VBAT DC voltage range inclusive of disturbances 30
CBUCK output current 65 mA Low Power Operation Mode (LPOM) only 30
Output voltage range (Core Buck) 1.2 1.26 1.5 V Programmable, 30mV/step default = 1.2 V (bits = 0000) 30
Output voltage DC accuracy (Core Buck) -4 4 % Includes load and line regulation 30
Input supply voltage ramp-up time 40 μs 0 to 3.3 V 30
Input low voltage VIL 0.8 V VDDO = 3 V 31
Input high voltage VIH 2.4 V VDDO = 3 V 31
Input low voltage VIL 0.4 V VDDO = 1.8 V 31
Input high voltage VIH 1.4 V VDDO = 1.8 V 31
Output low voltage VOL 0.45 V 31
Input low current IIL 1 μA 31
Input high current IIH 1 μA 31
Input capacitance CIN 0.4 pF 31
Output low current IOL 8 mA VDDO = 3 V, VOL = 0.5 V 31
Output low current IOL 4 mA VDDO = 1.8 V, VOL = 0.5 V 31
Output high current IOH 8 mA VDDO = 3 V, VOH = 2.55 V 31
Output high current IOH 4 mA VDDO = 1.8 V, VOH = 1.35 V 31
Current consumption ITOT 2 3 mA 31
ADC absolute error 5 % Includes gain error, offset and distortion. Without factory calibration. 31
ADC absolute error 2 % Includes gain error, offset and distortion. After factory calibration. 31
ENOB 12 13 Bit For audio application 31
ENOB 10 Bit For static measurement 31
ADC input full scale FS 1.8 3.6 V For static measurement 31
MIC PGA gain range 0 42 dB 31
MIC PGA gain error -1 1 dB Includes part-to-part gain variation 32
Passband gain flatness -0.5 0.5 dB PGA and ADC, 100 Hz-4 kHz 32
GPIO input voltage 3.6 V Always lower than avddBAT 32
RX frequency range 2402 2480 MHz 33
Maximum input -20 dBm All data rates 33
Bluetooth, interferer signal level -39 dBm BDR GFSK 0.1% BER 34
Spurious Emissions 30 MHz to 1 GHz -57 dBm 34
Spurious Emissions 1 GHz to 12.75 GHz -55 dBm 34
20 dB bandwidth 930 1000 kHz 34
Initial carrier frequency tolerance -75 75 kHz 34
Frequency drift (DH1 packet) -25 25 kHz DH1 packet 34
Average deviation in payload 140 175 kHz sequence used is 00001111 34
Maximum deviation in payload 115 kHz sequence used is 10101010 34
Mod Char: Delta F1 average (LE) 225 255 275 kHz N/A 35
Mod Char: Delta F2 max (LE) 99.9 % N/A 35
Adjacent Channel Power /M, N/ = 2 -20 dBm 34
HCI UART combined baud rate error -5 5 % Combined baud rate error of the two devices 8
UART delay, UART_CTS_N low to UART_TXD valid 1.5 Bit periods 36
UART setup, UART_CTS_N high before midpoint of stop bit 0.67 Bit periods 36
Time from master assert SPI_CSN to first clock edge 45 ns SPI Mode 0 and 2 37
RESET_N release after VDDO supply stabilization 35 ms Released only after VDDO supply voltage level has been stabilized 6

CAD (KiCad official)

  • Symbol: CYW20721B2KUMLGT
  • Footprint: Package_DFN_QFN:QFN-40-1EP_5x5mm_P0.4mm_EP3.6x3.6mm
  • 3D model: QFN-40(5x5) (KiCad packages3D, STEP)
  • 3D model files: cyw20721b2kumlgt-etched.step / cyw20721b2kumlgt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cyw20721b2kumlgt.step / cyw20721b2kumlgt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (47 pp, sha256 b8098c691c998147, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF