component
CYUSB3014-BZXI
Public Made by Adomby adom
Cypress Semicon CYPRESS, BGA-121. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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Publish 0.1.0
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README.md+196cyusb3014-bzxi-etched.glbcyusb3014-bzxi-hero.glbcyusb3014-bzxi-hero.overlay.json+1657cyusb3014-bzxi.glbcyusb3014-bzxi.kicad_mod+1037cyusb3014-bzxi.kicad_sym+497cyusb3014-bzxi.lbr+466cyusb3014-bzxi.step+3134docs/cyusb3014-bzxi-datasheet.pdfdocs/hero.pngpackage.json+871page.json+877viewers/footprint.html+1viewers/symbol.html+1README.mdadded+196@@ -0,0 +1,196 @@+# CYUSB3014-BZXI++**Cypress Semicon** · CYPRESS · BGA-121++CYUSB3014-BZXI from Cypress Semicon, in a BGA-121. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| A1 | U3VSSQ | power_in | Ground return for the USB 3.0 transceiver supply domain (U3RXVDDQ/U3TXVDDQ), shown on the 121-ball BGA map. |+| A2 | U3RXVDDQ | power_in | USB 3.0 receive-side supply input; the datasheet requires a bypass capacitor on this pin. |+| A3 | SSRXM | input | USB 3.0 SuperSpeed receive differential input, negative (SSRX-). |+| A4 | SSRXP | input | USB 3.0 SuperSpeed receive differential input, positive (SSRX+). |+| A5 | SSTXP | output | USB 3.0 SuperSpeed transmit differential output, positive (SSTX+). |+| A6 | SSTXM | output | USB 3.0 SuperSpeed transmit differential output, negative (SSTX-). |+| A7 | AVDD | power_in | Analog supply for the crystal oscillator/PLL domain (XTALIN and XTALOUT are in the AVDD domain). |+| A8 | VSS | power_in | Ground. |+| A9 | DP | bidirectional | USB 2.0 D+ data line. |+| A10 | DM | bidirectional | USB 2.0 D- data line. |+| A11 | NC | unconnected | No connect. |+| B1 | VIO4 | power_in | I/O supply for the VIO4 domain (GPIO[53] to GPIO[57]). |+| B2 | FSLC[0] | input | Clock input frequency select bit 0 (FSLC[0]), CVDDQ domain. |+| B3 | R_USB3 | passive | Precision resistor pin for USB 3.0: connect a 200 ohm ±1% resistor between this pin and GND. |+| B4 | FSLC[1] | input | Clock input frequency select bit 1 (FSLC[1]), CVDDQ domain. |+| B5 | U3TXVDDQ | power_in | USB 3.0 transmit-side supply input; the datasheet requires a bypass capacitor on this pin. |+| B6 | CVDDQ | power_in | Supply for the clock and reset input domain (FSLC[2:0], CLKIN). |+| B7 | AVSS | power_in | Analog ground. |+| B8 | VSS | power_in | Ground. |+| B9 | VSS | power_in | Ground. |+| B10 | VDD | power_in | Core power supply (core operates at 1.2 V). |+| B11 | TRST# | input | JTAG test reset, active low, with a fixed 50-kohm internal pull-up. |+| C1 | GPIO[54] | bidirectional | VIO4 GPIO; UART_CTS or SPI_SSN, I2S_CLK in the I2S+GPIO configuration, otherwise GPIO. |+| C2 | GPIO[55] | bidirectional | VIO4 GPIO; UART_TX or SPI_MISO, I2S_SD in the I2S+GPIO configuration, otherwise GPIO. |+| C3 | VDD | power_in | Core power supply (core operates at 1.2 V). |+| C4 | GPIO[57] | bidirectional | VIO4 GPIO; I2S_MCLK in the UART+SPI+I2S and I2S+GPIO configurations, otherwise GPIO. |+| C5 | RESET# | input | Hard reset input, active low; its assertion wakes the device from low-power modes. |+| C6 | XTALIN | passive | Crystal input (AVDD domain); a 19.2-MHz crystal may be used, or a clock may be supplied on CLKIN instead. |+| C7 | XTALOUT | passive | Crystal output (AVDD domain). |+| C8 | R_USB2 | passive | Precision resistor pin for USB 2.0: connect a 6.04 kohm ±1% resistor between this pin and GND. |+| C9 | OTG_ID | input | USB OTG ID input; an impedance change on this pin is a wakeup source from suspend. |+| C10 | TDO | output | JTAG test data output. |+| C11 | VIO5 | power_in | I/O supply for the VIO5 domain (I2C_GPIO[58], I2C_GPIO[59], O[60]). |+| D1 | GPIO[50] | bidirectional | VIO3 GPIO; I2S_CLK in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO. |+| D2 | GPIO[51] | bidirectional | VIO3 GPIO; I2S_SD in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO. |+| D3 | GPIO[52] | bidirectional | VIO3 GPIO; I2S_WS in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO. |+| D4 | GPIO[53] | bidirectional | VIO4 GPIO; UART_RTS or SPI_SCK depending on configuration, otherwise GPIO. |+| D5 | GPIO[56] | bidirectional | VIO4 GPIO; UART_RX or SPI_MOSI, I2S_WS in the I2S+GPIO configuration, otherwise GPIO. |+| D6 | CLKIN_32 | input | 32-kHz watchdog timer clock input. |+| D7 | CLKIN | input | External clock input (CVDDQ domain), alternative to the crystal; selectable 19.2, 26, 38.4 or 52 MHz. |+| D8 | VSS | power_in | Ground. |+| D9 | I2C_GPIO[58] | bidirectional | I2C / GPIO pin in the VIO5 domain; I2C operation at 1.2 V to 3.3 V. |+| D10 | I2C_GPIO[59] | bidirectional | I2C / GPIO pin in the VIO5 domain; I2C operation at 1.2 V to 3.3 V. |+| D11 | O[60] | output | Output pin O[60] in the VIO5 domain. |+| E1 | GPIO[47] | bidirectional | VIO3 GPIO; DQ[29] in the 32-bit data bus configuration, UART_CTS in the UART configurations, otherwise GPIO. |+| E2 | VSS | power_in | Ground. |+| E3 | VIO3 | power_in | I/O supply for the VIO3 domain (GPIO[46] to GPIO[52]). |+| E4 | GPIO[49] | bidirectional | VIO3 GPIO; DQ[31] in the 32-bit data bus configuration, UART_RX in the UART configurations, otherwise GPIO. |+| E5 | GPIO[48] | bidirectional | VIO3 GPIO; DQ[30] in the 32-bit data bus configuration, UART_TX in the UART configurations, otherwise GPIO. |+| E6 | FSLC[2] | input | Clock input frequency select bit 2 (FSLC[2]), CVDDQ domain. |+| E7 | TDI | input | JTAG test data input, with a fixed 50-kohm internal pull-up. |+| E8 | TMS | input | JTAG test mode select, with a fixed 50-kohm internal pull-up. |+| E9 | VDD | power_in | Core power supply (core operates at 1.2 V). |+| E10 | VBATT | power_in | USB battery-power supply input (VBATT). |+| E11 | VBUS | power_in | USB VBUS supply/detect input; VBUS detection is a wakeup source. |+| F1 | VIO2 | power_in | I/O supply for the VIO2 domain (GPIO[33] to GPIO[45]). |+| F2 | GPIO[45] | bidirectional | VIO2 GPIO; GPIO function in all interface configurations. |+| F3 | GPIO[44] | bidirectional | VIO2 GPIO; DQ[27] in the 32-bit data bus configuration, otherwise GPIO. |+| F4 | GPIO[41] | bidirectional | VIO2 GPIO; DQ[24] in the 32-bit data bus configuration, otherwise GPIO. |+| F5 | GPIO[46] | bidirectional | VIO3 GPIO; DQ[28] in the 32-bit data bus configuration, UART_RTS in the UART configurations, otherwise GPIO. |+| F6 | TCK | input | JTAG test clock, with a fixed 10-kohm internal pull-down. |+| F7 | GPIO[2] | bidirectional | VIO1 GPIF II pin; DQ[2] (Slave FIFO data). |+| F8 | GPIO[5] | bidirectional | VIO1 GPIF II pin; DQ[5] (Slave FIFO data). |+| F9 | GPIO[1] | bidirectional | VIO1 GPIF II pin; DQ[1] (Slave FIFO data). |+| F10 | GPIO[0] | bidirectional | VIO1 GPIF II pin; DQ[0] (Slave FIFO data). |+| F11 | VDD | power_in | Core power supply (core operates at 1.2 V). |+| G1 | VSS | power_in | Ground. |+| G2 | GPIO[42] | bidirectional | VIO2 GPIO; DQ[25] in the 32-bit data bus configuration, otherwise GPIO. |+| G3 | GPIO[43] | bidirectional | VIO2 GPIO; DQ[26] in the 32-bit data bus configuration, otherwise GPIO. |+| G4 | GPIO[30] | bidirectional | VIO1 GPIF II pin; PMODE[0] mode-select input. |+| G5 | GPIO[25] | bidirectional | VIO1 GPIF II pin; CTL[8], GPIO in Slave FIFO mode. |+| G6 | GPIO[22] | bidirectional | VIO1 GPIF II pin; CTL[5], FLAGB in Slave FIFO mode. |+| G7 | GPIO[21] | bidirectional | VIO1 GPIF II pin; CTL[4], FLAGA in Slave FIFO mode. |+| G8 | GPIO[15] | bidirectional | VIO1 GPIF II pin; DQ[15] (Slave FIFO data). |+| G9 | GPIO[4] | bidirectional | VIO1 GPIF II pin; DQ[4] (Slave FIFO data). |+| G10 | GPIO[3] | bidirectional | VIO1 GPIF II pin; DQ[3] (Slave FIFO data). |+| G11 | VSS | power_in | Ground. |+| H1 | VDD | power_in | Core power supply (core operates at 1.2 V). |+| H2 | GPIO[39] | bidirectional | VIO2 GPIO; DQ[22] in the 32-bit data bus configuration, otherwise GPIO. |+| H3 | GPIO[40] | bidirectional | VIO2 GPIO; DQ[23] in the 32-bit data bus configuration, otherwise GPIO. |+| H4 | GPIO[31] | bidirectional | VIO1 GPIF II pin; PMODE[1] mode-select input. |+| H5 | GPIO[29] | bidirectional | VIO1 GPIF II pin; CTL[12], A0 in Slave FIFO mode. |+| H6 | GPIO[26] | bidirectional | VIO1 GPIF II pin; CTL[9], GPIO in Slave FIFO mode. |+| H7 | GPIO[20] | bidirectional | VIO1 GPIF II pin; CTL[3], SLRD# in Slave FIFO mode. |+| H8 | GPIO[24] | bidirectional | VIO1 GPIF II pin; CTL[7], PKTEND# in Slave FIFO mode. |+| H9 | GPIO[7] | bidirectional | VIO1 GPIF II pin; DQ[7] (Slave FIFO data). |+| H10 | GPIO[6] | bidirectional | VIO1 GPIF II pin; DQ[6] (Slave FIFO data). |+| H11 | VIO1 | power_in | I/O supply for the VIO1 domain (GPIF II); the datasheet states it cannot be turned off if GPIF II is used. |+| J1 | GPIO[38] | bidirectional | VIO2 GPIO; DQ[21] in the 32-bit data bus configuration, otherwise GPIO. |+| J2 | GPIO[36] | bidirectional | VIO2 GPIO; DQ[19] in the 32-bit data bus configuration, otherwise GPIO. |+| J3 | GPIO[37] | bidirectional | VIO2 GPIO; DQ[20] in the 32-bit data bus configuration, otherwise GPIO. |+| J4 | GPIO[34] | bidirectional | VIO2 GPIO; DQ[17] in the 32-bit data bus configuration, otherwise GPIO. |+| J5 | GPIO[28] | bidirectional | VIO1 GPIF II pin; CTL[11], A1 in Slave FIFO mode. |+| J6 | GPIO[16] | bidirectional | VIO1 GPIF II pin; PCLK, CLK in Slave FIFO mode. |+| J7 | GPIO[19] | bidirectional | VIO1 GPIF II pin; CTL[2], SLOE# in Slave FIFO mode. |+| J8 | GPIO[14] | bidirectional | VIO1 GPIF II pin; DQ[14] (Slave FIFO data). |+| J9 | GPIO[9] | bidirectional | VIO1 GPIF II pin; DQ[9] (Slave FIFO data). |+| J10 | GPIO[8] | bidirectional | VIO1 GPIF II pin; DQ[8] (Slave FIFO data). |+| J11 | VDD | power_in | Core power supply (core operates at 1.2 V). |+| K1 | GPIO[35] | bidirectional | VIO2 GPIO; DQ[18] in the 32-bit data bus configuration, otherwise GPIO. |+| K2 | GPIO[33] | bidirectional | VIO2 GPIO; DQ[16] in the 32-bit data bus configuration, otherwise GPIO. |+| K3 | VSS | power_in | Ground. |+| K4 | VSS | power_in | Ground. |+| K5 | GPIO[27] | bidirectional | VIO1 GPIF II pin; CTL[10], GPIO in Slave FIFO mode. |+| K6 | GPIO[23] | bidirectional | VIO1 GPIF II pin; CTL[6], GPIO in Slave FIFO mode. |+| K7 | GPIO[18] | bidirectional | VIO1 GPIF II pin; CTL[1], SLWR# in Slave FIFO mode. |+| K8 | GPIO[17] | bidirectional | VIO1 GPIF II pin; CTL[0], SLCS# in Slave FIFO mode. |+| K9 | GPIO[13] | bidirectional | VIO1 GPIF II pin; DQ[13] (Slave FIFO data). |+| K10 | GPIO[12] | bidirectional | VIO1 GPIF II pin; DQ[12] (Slave FIFO data). |+| K11 | GPIO[10] | bidirectional | VIO1 GPIF II pin; DQ[10] (Slave FIFO data). |+| L1 | VSS | power_in | Ground. |+| L2 | VSS | power_in | Ground. |+| L3 | VSS | power_in | Ground. |+| L4 | GPIO[32] | bidirectional | VIO1 GPIF II pin; PMODE[2] mode-select input. |+| L5 | VDD | power_in | Core power supply (core operates at 1.2 V). |+| L6 | VSS | power_in | Ground. |+| L7 | VDD | power_in | Core power supply (core operates at 1.2 V). |+| L8 | INT# | bidirectional | VIO1 pin INT#/CTL[15]; CTL[15] in Slave FIFO mode and not usable as a GPIO. |+| L9 | VIO1 | power_in | I/O supply for the VIO1 domain (GPIF II); the datasheet states it cannot be turned off if GPIF II is used. |+| L10 | GPIO[11] | bidirectional | VIO1 GPIF II pin; DQ[11] (Slave FIFO data). |+| L11 | VSS | power_in | Ground. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Cypress Semicon |+| Package | BGA-121 |+| Category | Embedded Processors & Controllers |+| Pins | 121 |++## Electrical characteristics++Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).++| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |+|---|---|---|---|---|---|---|---|+| Storage temperature | | -65 | | 150 | °C | | 19 |+| Ambient temperature with power supplied (Industrial) | | -40 | | 85 | °C | Industrial | 19 |+| Supply voltage VDD, AVDDQ | VDD, AVDDQ | | | 1.25 | V | Supply voltage to ground potential | 19 |+| Supply voltage VIO1-VIO5 | VIO1, VIO2, VIO3, VIO4, VIO5 | | | 3.6 | V | Supply voltage to ground potential | 19 |+| Supply voltage U3TXVDDQ, U3RXVDDQ | U3TXVDDQ, U3RXVDDQ | | | 1.25 | V | Supply voltage to ground potential | 19 |+| ESD protection HBM | | -2.2 | | 2.2 | kV | HBM based on JESD22-A114 | 19 |+| Latch-up current | | 200 | | | mA | > 200 mA | 19 |+| Maximum output short-circuit current | | | | -100 | mA | All I/O configurations, Vout = 0 V | 19 |+| Ambient temperature under bias (Industrial) | TA | -40 | | 85 | °C | Industrial | 19 |+| Supply voltage VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ | VDD | 1.15 | | 1.25 | V | | 19 |+| VBATT supply voltage | VBATT | 3.2 | | 6 | V | | 19 |+| VIO1-VIO4, CVDDQ supply voltage | VIO1, VIO2, VIO3, VIO4, CVDDQ | 1.7 | | 3.6 | V | | 19 |+| VIO5 supply voltage | VIO5 | 1.15 | | 3.6 | V | | 19 |+| Core voltage supply | VDD | 1.15 | | 1.25 | V | 1.2-V typical | 19 |+| Analog voltage supply | AVDD | 1.15 | | 1.25 | V | 1.2-V typical | 19 |+| GPIF II I/O power supply domain | VIO1 | 1.7 | | 3.6 | V | 1.8-, 2.5-, and 3.3-V typical | 19 |+| IO2 power supply domain | VIO2 | 1.7 | | 3.6 | V | 1.8-, 2.5-, and 3.3-V typical | 19 |+| IO3 power supply domain | VIO3 | 1.7 | | 3.6 | V | 1.8-, 2.5-, and 3.3-V typical | 19 |+| UART/SPI/I2S power supply domain | VIO4 | 1.7 | | 3.6 | V | 1.8-, 2.5-, and 3.3-V typical | 19 |+| USB voltage supply | VBATT | 3.2 | | 6 | V | 3.7-V typical | 19 |+| USB voltage supply | VBUS | 4 | | 6 | V | 5-V typical | 19 |+| USB 3.0 1.2-V supply | U3TXVDDQ | 1.15 | | 1.25 | V | 1.2-V typical. A 22-µF bypass capacitor is required | 19 |+| Clock voltage supply | CVDDQ | 1.7 | | 3.6 | V | 1.8-, 3.3-V typical | 19 |+| I2C and JTAG voltage supply | VIO5 | 1.15 | | 3.6 | V | 1.2-, 1.8-, 2.5-, and 3.3-V typical | 19 |+| Input leakage current for all pins except SSTXP/SSXM/SSRXP/SSRXM | IIX | -1 | | 1 | µA | All I/O signals held at VDDQ | 20 |+| Output High-Z leakage current for all pins except SSTXP/SSXM/SSRXP/SSRXM | IOZ | -1 | | 1 | µA | All I/O signals held at VDDQ | 20 |+| Core and analog voltage operating current | ICC Core | | | 200 | mA | Total current through AVDD, VDD | 20 |+| USB voltage supply operating current | ICC USB | | | 60 | mA | | 20 |+| Voltage ramp rate on core and I/O supplies | VRAMP | 0.2 | | 50 | V/ms | Voltage ramp must be monotonic | 20 |+| Noise level permitted on VDD and I/O supplies | VN | | | 100 | mV | Max p-p noise level permitted on all supplies except AVDD | 20 |+| Noise level permitted on AVDD supply | VN_AVDD | | | 20 | mV | Max p-p noise level permitted on AVDD | 20 |+| GPIO current source and sink | ISS | | | 20 | mA | Rating for quarter drive strength | 20 |++## CAD (KiCad official)++- Symbol: `CYUSB3014-BZXI`+- Footprint: `Package_BGA:BGA-121_9.0x9.0mm_Layout11x11_P0.8mm_Ball0.4mm_Pad0.35mm_NSMD`+- 3D model: BGA-121 (KiCad packages3D, STEP)+- 3D model files: `cyusb3014-bzxi-etched.step` / `cyusb3014-bzxi-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cyusb3014-bzxi.step` / `cyusb3014-bzxi.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Cypress Semicon datasheet](docs/cyusb3014-bzxi-datasheet.pdf) (52 pp, sha256 `87a3bd0918148fc2`, retrieved 2026-10-22, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/cyusb3014-bzxi-datasheet.pdf)
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cyusb3014-bzxi.glbadded⋯ 1 unchanged line ⋯
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length="middle" direction="pas"/>+ <pin name="R_USB2" x="-17.78" y="2.54" length="middle" direction="pas"/>+ <pin name="OTG_ID" x="-17.78" y="0" length="middle" direction="in"/>+ <pin name="TDO" x="-17.78" y="-2.54" length="middle" direction="out"/>+ <pin name="VIO5" x="-17.78" y="-5.08" length="middle" direction="pwr"/>+ <pin name="GPIO_50" x="-17.78" y="-7.62" length="middle" direction="io"/>+ <pin name="GPIO_51" x="-17.78" y="-10.16" length="middle" direction="io"/>+ <pin name="GPIO_52" x="-17.78" y="-12.7" length="middle" direction="io"/>+ <pin name="GPIO_53" x="-17.78" y="-15.24" length="middle" direction="io"/>+ <pin name="GPIO_56" x="-17.78" y="-17.78" length="middle" direction="io"/>+ <pin name="CLKIN_32" x="-17.78" y="-20.32" length="middle" direction="in"/>+ <pin name="CLKIN" x="-17.78" y="-22.86" length="middle" direction="in"/>+ <pin name="VSS@4" x="-17.78" y="-25.4" length="middle" direction="pwr"/>+ <pin name="I2C_GPIO_58" x="-17.78" y="-27.94" length="middle" direction="io"/>+ <pin name="I2C_GPIO_59" x="-17.78" y="-30.48" length="middle" direction="io"/>+ <pin name="O_60" x="-17.78" y="-33.02" length="middle" direction="out"/>+ <pin name="GPIO_47" x="-17.78" y="-35.56" length="middle" direction="io"/>+ <pin name="VSS@5" x="-17.78" y="-38.1" length="middle" direction="pwr"/>+ <pin name="VIO3" x="-17.78" y="-40.64" length="middle" direction="pwr"/>+ <pin name="GPIO_49" x="-17.78" y="-43.18" length="middle" direction="io"/>+ <pin name="GPIO_48" x="-17.78" y="-45.72" length="middle" direction="io"/>+ <pin name="FSLC_2" x="-17.78" y="-48.26" length="middle" direction="in"/>+ <pin name="TDI" x="-17.78" y="-50.8" length="middle" direction="in"/>+ <pin name="TMS" x="-17.78" y="-53.34" length="middle" direction="in"/>+ <pin name="VDD@3" x="-17.78" y="-55.88" length="middle" direction="pwr"/>+ <pin name="VBATT" x="-17.78" y="-58.42" length="middle" direction="pwr"/>+ <pin name="VBUS" x="-17.78" y="-60.96" length="middle" direction="pwr"/>+ <pin name="VIO2" x="-17.78" y="-63.5" length="middle" direction="pwr"/>+ <pin name="GPIO_45" x="-17.78" y="-66.04" length="middle" direction="io"/>+ <pin name="GPIO_44" x="-17.78" y="-68.58" length="middle" direction="io"/>+ <pin name="GPIO_41" x="-17.78" y="-71.12" length="middle" direction="io"/>+ <pin name="GPIO_46" x="-17.78" y="-73.66" length="middle" direction="io"/>+ <pin name="TCK" x="-17.78" y="-76.2" length="middle" direction="in"/>+ <pin name="VSS@6" x="17.78" y="73.66" length="middle" direction="pwr" rot="R180"/>+ <pin name="GPIO_11" x="17.78" y="71.12" length="middle" direction="io" rot="R180"/>+ <pin name="VIO1" x="17.78" y="68.58" length="middle" direction="pwr" rot="R180"/>+ <pin name="INT#" x="17.78" y="66.04" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@4" x="17.78" y="63.5" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@7" x="17.78" y="60.96" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@5" x="17.78" y="58.42" length="middle" direction="pwr" rot="R180"/>+ <pin name="GPIO_32" x="17.78" y="55.88" length="middle" direction="io" rot="R180"/>+ <pin name="VSS@8" x="17.78" y="53.34" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@9" x="17.78" y="50.8" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@10" x="17.78" y="48.26" length="middle" direction="pwr" rot="R180"/>+ <pin name="GPIO_10" x="17.78" y="45.72" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_12" x="17.78" y="43.18" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_13" x="17.78" y="40.64" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_17" x="17.78" y="38.1" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_18" x="17.78" y="35.56" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_23" x="17.78" y="33.02" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_27" x="17.78" y="30.48" length="middle" direction="io" rot="R180"/>+ <pin name="VSS@11" x="17.78" y="27.94" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@12" x="17.78" y="25.4" length="middle" direction="pwr" rot="R180"/>+ <pin name="GPIO_33" x="17.78" y="22.86" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_35" x="17.78" y="20.32" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@6" x="17.78" y="17.78" length="middle" direction="pwr" rot="R180"/>+ <pin name="GPIO_8" x="17.78" y="15.24" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_9" x="17.78" y="12.7" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_14" x="17.78" y="10.16" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_19" x="17.78" y="7.62" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_16" x="17.78" y="5.08" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_28" x="17.78" y="2.54" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_34" x="17.78" y="0" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_37" x="17.78" y="-2.54" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_36" x="17.78" y="-5.08" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_38" x="17.78" y="-7.62" length="middle" direction="io" rot="R180"/>+ <pin name="VIO1@2" x="17.78" y="-10.16" length="middle" direction="pwr" rot="R180"/>+ <pin name="GPIO_6" x="17.78" y="-12.7" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_7" x="17.78" y="-15.24" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_24" x="17.78" y="-17.78" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_20" x="17.78" y="-20.32" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_26" x="17.78" y="-22.86" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_29" x="17.78" y="-25.4" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_31" x="17.78" y="-27.94" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_40" x="17.78" y="-30.48" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_39" x="17.78" y="-33.02" length="middle" direction="io" rot="R180"/>+ <pin name="VDD@7" x="17.78" y="-35.56" length="middle" direction="pwr" rot="R180"/>+ <pin name="VSS@13" x="17.78" y="-38.1" length="middle" direction="pwr" rot="R180"/>+ <pin name="GPIO_3" x="17.78" y="-40.64" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_4" x="17.78" y="-43.18" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_15" x="17.78" y="-45.72" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_21" x="17.78" y="-48.26" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_22" x="17.78" y="-50.8" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_25" x="17.78" y="-53.34" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_30" x="17.78" y="-55.88" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_43" x="17.78" y="-58.42" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_42" x="17.78" y="-60.96" length="middle" direction="io" rot="R180"/>+ <pin name="VSS@14" x="17.78" y="-63.5" length="middle" direction="pwr" rot="R180"/>+ <pin name="VDD@8" x="17.78" y="-66.04" length="middle" direction="pwr" rot="R180"/>+ <pin name="GPIO_0" x="17.78" y="-68.58" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_1" x="17.78" y="-71.12" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_5" x="17.78" y="-73.66" length="middle" direction="io" rot="R180"/>+ <pin name="GPIO_2" x="17.78" y="-76.2" length="middle" direction="io" rot="R180"/>+</symbol>+</symbols>+<devicesets>+<deviceset name="CYUSB3014-BZXI" prefix="U">+ <description></description>+ <gates>+ <gate name="G$1" symbol="CYUSB3014-BZXI" x="0" y="0"/>+ </gates>+ <devices>+ <device name="" package="BGA-121_9.0x9.0mm_Layout11x11_P0.8mm_Ball0.4mm_Pad0.35mm_NSMD">+ <connects>+ <connect gate="G$1" pin="U3VSSQ" pad="A1"/>+ <connect gate="G$1" pin="U3RXVDDQ" pad="A2"/>+ <connect gate="G$1" pin="SSRXM" pad="A3"/>+ <connect gate="G$1" pin="SSRXP" pad="A4"/>+ <connect gate="G$1" pin="SSTXP" pad="A5"/>+ <connect gate="G$1" pin="SSTXM" pad="A6"/>+ <connect gate="G$1" pin="AVDD" pad="A7"/>+ <connect gate="G$1" pin="VSS" pad="A8"/>+ <connect gate="G$1" pin="DP" pad="A9"/>+ <connect gate="G$1" pin="DM" pad="A10"/>+ <connect gate="G$1" pin="NC" pad="A11"/>+ <connect gate="G$1" pin="VIO4" pad="B1"/>+ <connect gate="G$1" pin="FSLC_0" pad="B2"/>+ <connect gate="G$1" pin="R_USB3" pad="B3"/>+ <connect gate="G$1" pin="FSLC_1" pad="B4"/>+ <connect gate="G$1" pin="U3TXVDDQ" pad="B5"/>+ <connect gate="G$1" pin="CVDDQ" pad="B6"/>+ <connect gate="G$1" pin="AVSS" pad="B7"/>+ <connect gate="G$1" pin="VSS@2" pad="B8"/>+ <connect gate="G$1" pin="VSS@3" pad="B9"/>+ <connect gate="G$1" pin="VDD" pad="B10"/>+ <connect gate="G$1" pin="TRST#" pad="B11"/>+ <connect gate="G$1" pin="GPIO_54" pad="C1"/>+ <connect gate="G$1" pin="GPIO_55" pad="C2"/>+ <connect gate="G$1" pin="VDD@2" pad="C3"/>+ <connect gate="G$1" pin="GPIO_57" pad="C4"/>+ <connect gate="G$1" pin="RESET#" pad="C5"/>+ <connect gate="G$1" pin="XTALIN" pad="C6"/>+ <connect gate="G$1" pin="XTALOUT" pad="C7"/>+ <connect gate="G$1" pin="R_USB2" pad="C8"/>+ <connect gate="G$1" pin="OTG_ID" pad="C9"/>+ <connect gate="G$1" pin="TDO" pad="C10"/>+ <connect gate="G$1" pin="VIO5" pad="C11"/>+ <connect gate="G$1" pin="GPIO_50" pad="D1"/>+ <connect gate="G$1" pin="GPIO_51" pad="D2"/>+ <connect gate="G$1" pin="GPIO_52" pad="D3"/>+ <connect gate="G$1" pin="GPIO_53" pad="D4"/>+ <connect gate="G$1" pin="GPIO_56" pad="D5"/>+ <connect gate="G$1" pin="CLKIN_32" pad="D6"/>+ <connect gate="G$1" pin="CLKIN" pad="D7"/>+ <connect gate="G$1" pin="VSS@4" pad="D8"/>+ <connect gate="G$1" pin="I2C_GPIO_58" pad="D9"/>+ <connect gate="G$1" pin="I2C_GPIO_59" pad="D10"/>+ <connect gate="G$1" pin="O_60" pad="D11"/>+ <connect gate="G$1" pin="GPIO_47" pad="E1"/>+ <connect gate="G$1" pin="VSS@5" pad="E2"/>+ <connect gate="G$1" pin="VIO3" pad="E3"/>+ <connect gate="G$1" pin="GPIO_49" pad="E4"/>+ <connect gate="G$1" pin="GPIO_48" pad="E5"/>+ <connect gate="G$1" pin="FSLC_2" pad="E6"/>+ <connect gate="G$1" pin="TDI" pad="E7"/>+ <connect gate="G$1" pin="TMS" pad="E8"/>+ <connect gate="G$1" pin="VDD@3" pad="E9"/>+ <connect gate="G$1" pin="VBATT" pad="E10"/>+ <connect gate="G$1" pin="VBUS" pad="E11"/>+ <connect gate="G$1" pin="VIO2" pad="F1"/>+ <connect gate="G$1" pin="GPIO_45" pad="F2"/>+ <connect gate="G$1" pin="GPIO_44" pad="F3"/>+ <connect gate="G$1" pin="GPIO_41" pad="F4"/>+ <connect gate="G$1" pin="GPIO_46" pad="F5"/>+ <connect gate="G$1" pin="TCK" pad="F6"/>+ <connect gate="G$1" pin="VSS@6" pad="L11"/>+ <connect gate="G$1" pin="GPIO_11" pad="L10"/>+ <connect gate="G$1" pin="VIO1" pad="L9"/>+ <connect gate="G$1" pin="INT#" pad="L8"/>+ <connect gate="G$1" pin="VDD@4" pad="L7"/>+ <connect gate="G$1" pin="VSS@7" pad="L6"/>+ <connect gate="G$1" pin="VDD@5" pad="L5"/>+ <connect gate="G$1" pin="GPIO_32" pad="L4"/>+ <connect gate="G$1" pin="VSS@8" pad="L3"/>+ <connect gate="G$1" pin="VSS@9" pad="L2"/>+ <connect gate="G$1" pin="VSS@10" pad="L1"/>+ <connect gate="G$1" pin="GPIO_10" pad="K11"/>+ <connect gate="G$1" pin="GPIO_12" pad="K10"/>+ <connect gate="G$1" pin="GPIO_13" pad="K9"/>+ <connect gate="G$1" pin="GPIO_17" pad="K8"/>+ <connect gate="G$1" pin="GPIO_18" pad="K7"/>+ <connect gate="G$1" pin="GPIO_23" pad="K6"/>+ <connect gate="G$1" pin="GPIO_27" pad="K5"/>+ <connect gate="G$1" pin="VSS@11" pad="K4"/>+ <connect gate="G$1" pin="VSS@12" pad="K3"/>+ <connect gate="G$1" pin="GPIO_33" pad="K2"/>+ <connect gate="G$1" pin="GPIO_35" pad="K1"/>+ <connect gate="G$1" pin="VDD@6" pad="J11"/>+ <connect gate="G$1" pin="GPIO_8" pad="J10"/>+ <connect gate="G$1" pin="GPIO_9" pad="J9"/>+ <connect gate="G$1" pin="GPIO_14" pad="J8"/>+ <connect gate="G$1" pin="GPIO_19" pad="J7"/>+ <connect gate="G$1" pin="GPIO_16" pad="J6"/>+ <connect gate="G$1" pin="GPIO_28" pad="J5"/>+ <connect gate="G$1" pin="GPIO_34" pad="J4"/>+ <connect gate="G$1" pin="GPIO_37" pad="J3"/>+ <connect gate="G$1" pin="GPIO_36" pad="J2"/>+ <connect gate="G$1" pin="GPIO_38" pad="J1"/>+ <connect gate="G$1" pin="VIO1@2" pad="H11"/>+ <connect gate="G$1" pin="GPIO_6" pad="H10"/>+ <connect gate="G$1" pin="GPIO_7" pad="H9"/>+ <connect gate="G$1" pin="GPIO_24" pad="H8"/>+ <connect gate="G$1" pin="GPIO_20" pad="H7"/>+ <connect gate="G$1" pin="GPIO_26" pad="H6"/>+ <connect gate="G$1" pin="GPIO_29" pad="H5"/>+ <connect gate="G$1" pin="GPIO_31" pad="H4"/>+ <connect gate="G$1" pin="GPIO_40" pad="H3"/>+ <connect gate="G$1" pin="GPIO_39" pad="H2"/>+ <connect gate="G$1" pin="VDD@7" pad="H1"/>+ <connect gate="G$1" pin="VSS@13" pad="G11"/>+ <connect gate="G$1" pin="GPIO_3" pad="G10"/>+ <connect gate="G$1" pin="GPIO_4" pad="G9"/>+ <connect gate="G$1" pin="GPIO_15" pad="G8"/>+ <connect gate="G$1" pin="GPIO_21" pad="G7"/>+ <connect gate="G$1" pin="GPIO_22" pad="G6"/>+ <connect gate="G$1" pin="GPIO_25" pad="G5"/>+ <connect gate="G$1" pin="GPIO_30" pad="G4"/>+ <connect gate="G$1" pin="GPIO_43" pad="G3"/>+ <connect gate="G$1" pin="GPIO_42" pad="G2"/>+ <connect gate="G$1" pin="VSS@14" pad="G1"/>+ <connect gate="G$1" pin="VDD@8" pad="F11"/>+ <connect gate="G$1" pin="GPIO_0" pad="F10"/>+ <connect gate="G$1" pin="GPIO_1" pad="F9"/>+ <connect gate="G$1" pin="GPIO_5" pad="F8"/>+ <connect gate="G$1" pin="GPIO_2" pad="F7"/>+ </connects>+ <technologies><technology name=""/></technologies>+ </device>+ </devices>+</deviceset>+</devicesets>+</library>+</drawing>+</eagle>
cyusb3014-bzxi.stepadded+3134@@ -0,0 +1,3134 @@+ISO-10303-21;+HEADER;+/* BGA-121_9.0x9.0mm_Layout11x11_P0.8mm.step 3D STEP model for use in ECAD systems+ * Copyright (C) 2026, KiCAD+ *+ * This work is licensed under the+ * [Creative Commons CC-BY-SA 4.0 License](https://creativecommons.org/licenses/by-sa/4.0/legalcode),+ * with the following exception:+ *+ * To the extent that the creation of electronic designs that use 'Licensed Material' can be+ * considered to be 'Adapted Material', then the copyright holder waives article 3 of the license+ * with respect to these designs and any generated files which use data provided as part of the+ * 'Licensed Material'.+ *+ * You are free to use the library data in your own projects without the obligation to share your+ * project files under this or any other license agreement. However, if you wish to distribute+ * these libraries, or parts thereof (including in modified form) as a collection then the exception+ * above does not apply. Please refer to+ * https://gitlab.com/kicad/libraries/kicad-packages3D/-/blob/master/LICENSE.md for further clarification+ * of the exception.+ *+ * Disclaimer of Warranties and Limitation of Liability.+ * These libraries are provided in the hope that they will be useful, but are provided without warranty of any kind, express or implied.+ * USE 3D CAD DATA AT YOUR OWN RISK+ * DO NOT RELY UPON ANY INFORMATION FOUND HERE WITHOUT INDEPENDENT VERIFICATION.+ */++FILE_DESCRIPTION(+/* description */ ('model of BGA-121_9.0x9.0mm_Layout11x11_P0.8mm'),+/* implementation_level */ '2;1');++FILE_NAME(+/* name */ 'BGA-121_9.0x9.0mm_Layout11x11_P0.8mm.step',+/* time_stamp */ '1970-01-01T00:00:00',+/* author */ ('KiCAD','kicad'),+/* organization */ ('OCCT'),+/* preprocessor_version */ '',+/* originating_system */ 'KiCAD',+/* authorisation */ '');++FILE_SCHEMA(('AUTOMOTIVE_DESIGN { 1 0 10303 214 1 1 1 1 }'));+ENDSEC;++DATA;+#1=APPLICATION_PROTOCOL_DEFINITION('international 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package.jsonadded+871@@ -0,0 +1,871 @@+{+ "slug": "cyusb3014-bzxi",+ "version": "0.1.0",+ "type": "component",+ "description": "Cypress Semicon CYPRESS, BGA-121. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "cyusb3014-bzxi",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cyusb3014-bzxi.kicad_sym",+ "cyusb3014-bzxi.kicad_mod",+ "cyusb3014-bzxi.glb",+ "cyusb3014-bzxi.step",+ "cyusb3014-bzxi.lbr",+ "docs/hero.png",+ "docs/cyusb3014-bzxi-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cyusb3014-bzxi-hero.glb",+ "cyusb3014-bzxi-hero.overlay.json",+ "cyusb3014-bzxi-etched.glb"+ ],+ "component": {+ "mpn": "CYUSB3014-BZXI",+ "manufacturer": "Cypress Semicon",+ "package": "BGA-121",+ "pin_count": 121,+ "category": "Embedded Processors & Controllers",+ "subcategory": "CYPRESS",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/9bf8eaa3d2ea4b51ad0ef9dc0c29253c.pdf",+ "parts": {+ "symbol": "cyusb3014-bzxi.kicad_sym",+ "footprint": "cyusb3014-bzxi.kicad_mod",+ "model_3d": "cyusb3014-bzxi-hero.glb",+ "model_3d_plain": "cyusb3014-bzxi-etched.glb",+ "model_3d_step": "cyusb3014-bzxi-etched.step",+ "model_3d_step_plain": "cyusb3014-bzxi.step",+ "lbr": "cyusb3014-bzxi.lbr"+ },+ "distributor_links": {+ "lcsc": "C57294"+ },+ "distributor_check": {+ "checked_at": "2026-10-22T20:04:12Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "quota"+ },+ "mouser": {+ "pn": null,+ "status": "quota"+ }+ },+ "pins": [+ {+ "number": "A1",+ "name": "U3VSSQ",+ "type": "power_in",+ "description": "Ground return for the USB 3.0 transceiver supply domain (U3RXVDDQ/U3TXVDDQ), shown on the 121-ball BGA map."+ },+ {+ "number": "A2",+ "name": "U3RXVDDQ",+ "type": "power_in",+ "description": "USB 3.0 receive-side supply input; the datasheet requires a bypass capacitor on this pin."+ },+ {+ "number": "A3",+ "name": "SSRXM",+ "type": "input",+ "description": "USB 3.0 SuperSpeed receive differential input, negative (SSRX-)."+ },+ {+ "number": "A4",+ "name": "SSRXP",+ "type": "input",+ "description": "USB 3.0 SuperSpeed receive differential input, positive (SSRX+)."+ },+ {+ "number": "A5",+ "name": "SSTXP",+ "type": "output",+ "description": "USB 3.0 SuperSpeed transmit differential output, positive (SSTX+)."+ },+ {+ "number": "A6",+ "name": "SSTXM",+ "type": "output",+ "description": "USB 3.0 SuperSpeed transmit differential output, negative (SSTX-)."+ },+ {+ "number": "A7",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply for the crystal oscillator/PLL domain (XTALIN and XTALOUT are in the AVDD domain)."+ },+ {+ "number": "A8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "A9",+ "name": "DP",+ "type": "bidirectional",+ "description": "USB 2.0 D+ data line."+ },+ {+ "number": "A10",+ "name": "DM",+ "type": "bidirectional",+ "description": "USB 2.0 D- data line."+ },+ {+ "number": "A11",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect."+ },+ {+ "number": "B1",+ "name": "VIO4",+ "type": "power_in",+ "description": "I/O supply for the VIO4 domain (GPIO[53] to GPIO[57])."+ },+ {+ "number": "B2",+ "name": "FSLC[0]",+ "type": "input",+ "description": "Clock input frequency select bit 0 (FSLC[0]), CVDDQ domain."+ },+ {+ "number": "B3",+ "name": "R_USB3",+ "type": "passive",+ "description": "Precision resistor pin for USB 3.0: connect a 200 ohm ±1% resistor between this pin and GND."+ },+ {+ "number": "B4",+ "name": "FSLC[1]",+ "type": "input",+ "description": "Clock input frequency select bit 1 (FSLC[1]), CVDDQ domain."+ },+ {+ "number": "B5",+ "name": "U3TXVDDQ",+ "type": "power_in",+ "description": "USB 3.0 transmit-side supply input; the datasheet requires a bypass capacitor on this pin."+ },+ {+ "number": "B6",+ "name": "CVDDQ",+ "type": "power_in",+ "description": "Supply for the clock and reset input domain (FSLC[2:0], CLKIN)."+ },+ {+ "number": "B7",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "B8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "B9",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "B10",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "B11",+ "name": "TRST#",+ "type": "input",+ "description": "JTAG test reset, active low, with a fixed 50-kohm internal pull-up."+ },+ {+ "number": "C1",+ "name": "GPIO[54]",+ "type": "bidirectional",+ "description": "VIO4 GPIO; UART_CTS or SPI_SSN, I2S_CLK in the I2S+GPIO configuration, otherwise GPIO."+ },+ {+ "number": "C2",+ "name": "GPIO[55]",+ "type": "bidirectional",+ "description": "VIO4 GPIO; UART_TX or SPI_MISO, I2S_SD in the I2S+GPIO configuration, otherwise GPIO."+ },+ {+ "number": "C3",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "C4",+ "name": "GPIO[57]",+ "type": "bidirectional",+ "description": "VIO4 GPIO; I2S_MCLK in the UART+SPI+I2S and I2S+GPIO configurations, otherwise GPIO."+ },+ {+ "number": "C5",+ "name": "RESET#",+ "type": "input",+ "description": "Hard reset input, active low; its assertion wakes the device from low-power modes."+ },+ {+ "number": "C6",+ "name": "XTALIN",+ "type": "passive",+ "description": "Crystal input (AVDD domain); a 19.2-MHz crystal may be used, or a clock may be supplied on CLKIN instead."+ },+ {+ "number": "C7",+ "name": "XTALOUT",+ "type": "passive",+ "description": "Crystal output (AVDD domain)."+ },+ {+ "number": "C8",+ "name": "R_USB2",+ "type": "passive",+ "description": "Precision resistor pin for USB 2.0: connect a 6.04 kohm ±1% resistor between this pin and GND."+ },+ {+ "number": "C9",+ "name": "OTG_ID",+ "type": "input",+ "description": "USB OTG ID input; an impedance change on this pin is a wakeup source from suspend."+ },+ {+ "number": "C10",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test data output."+ },+ {+ "number": "C11",+ "name": "VIO5",+ "type": "power_in",+ "description": "I/O supply for the VIO5 domain (I2C_GPIO[58], I2C_GPIO[59], O[60])."+ },+ {+ "number": "D1",+ "name": "GPIO[50]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; I2S_CLK in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO."+ },+ {+ "number": "D2",+ "name": "GPIO[51]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; I2S_SD in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO."+ },+ {+ "number": "D3",+ "name": "GPIO[52]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; I2S_WS in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO."+ },+ {+ "number": "D4",+ "name": "GPIO[53]",+ "type": "bidirectional",+ "description": "VIO4 GPIO; UART_RTS or SPI_SCK depending on configuration, otherwise GPIO."+ },+ {+ "number": "D5",+ "name": "GPIO[56]",+ "type": "bidirectional",+ "description": "VIO4 GPIO; UART_RX or SPI_MOSI, I2S_WS in the I2S+GPIO configuration, otherwise GPIO."+ },+ {+ "number": "D6",+ "name": "CLKIN_32",+ "type": "input",+ "description": "32-kHz watchdog timer clock input."+ },+ {+ "number": "D7",+ "name": "CLKIN",+ "type": "input",+ "description": "External clock input (CVDDQ domain), alternative to the crystal; selectable 19.2, 26, 38.4 or 52 MHz."+ },+ {+ "number": "D8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "D9",+ "name": "I2C_GPIO[58]",+ "type": "bidirectional",+ "description": "I2C / GPIO pin in the VIO5 domain; I2C operation at 1.2 V to 3.3 V."+ },+ {+ "number": "D10",+ "name": "I2C_GPIO[59]",+ "type": "bidirectional",+ "description": "I2C / GPIO pin in the VIO5 domain; I2C operation at 1.2 V to 3.3 V."+ },+ {+ "number": "D11",+ "name": "O[60]",+ "type": "output",+ "description": "Output pin O[60] in the VIO5 domain."+ },+ {+ "number": "E1",+ "name": "GPIO[47]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; DQ[29] in the 32-bit data bus configuration, UART_CTS in the UART configurations, otherwise GPIO."+ },+ {+ "number": "E2",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "E3",+ "name": "VIO3",+ "type": "power_in",+ "description": "I/O supply for the VIO3 domain (GPIO[46] to GPIO[52])."+ },+ {+ "number": "E4",+ "name": "GPIO[49]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; DQ[31] in the 32-bit data bus configuration, UART_RX in the UART configurations, otherwise GPIO."+ },+ {+ "number": "E5",+ "name": "GPIO[48]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; DQ[30] in the 32-bit data bus configuration, UART_TX in the UART configurations, otherwise GPIO."+ },+ {+ "number": "E6",+ "name": "FSLC[2]",+ "type": "input",+ "description": "Clock input frequency select bit 2 (FSLC[2]), CVDDQ domain."+ },+ {+ "number": "E7",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input, with a fixed 50-kohm internal pull-up."+ },+ {+ "number": "E8",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select, with a fixed 50-kohm internal pull-up."+ },+ {+ "number": "E9",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "E10",+ "name": "VBATT",+ "type": "power_in",+ "description": "USB battery-power supply input (VBATT)."+ },+ {+ "number": "E11",+ "name": "VBUS",+ "type": "power_in",+ "description": "USB VBUS supply/detect input; VBUS detection is a wakeup source."+ },+ {+ "number": "F1",+ "name": "VIO2",+ "type": "power_in",+ "description": "I/O supply for the VIO2 domain (GPIO[33] to GPIO[45])."+ },+ {+ "number": "F2",+ "name": "GPIO[45]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; GPIO function in all interface configurations."+ },+ {+ "number": "F3",+ "name": "GPIO[44]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[27] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "F4",+ "name": "GPIO[41]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[24] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "F5",+ "name": "GPIO[46]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; DQ[28] in the 32-bit data bus configuration, UART_RTS in the UART configurations, otherwise GPIO."+ },+ {+ "number": "F6",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock, with a fixed 10-kohm internal pull-down."+ },+ {+ "number": "F7",+ "name": "GPIO[2]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[2] (Slave FIFO data)."+ },+ {+ "number": "F8",+ "name": "GPIO[5]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[5] (Slave FIFO data)."+ },+ {+ "number": "F9",+ "name": "GPIO[1]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[1] (Slave FIFO data)."+ },+ {+ "number": "F10",+ "name": "GPIO[0]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[0] (Slave FIFO data)."+ },+ {+ "number": "F11",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "G1",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "G2",+ "name": "GPIO[42]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[25] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "G3",+ "name": "GPIO[43]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[26] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "G4",+ "name": "GPIO[30]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; PMODE[0] mode-select input."+ },+ {+ "number": "G5",+ "name": "GPIO[25]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[8], GPIO in Slave FIFO mode."+ },+ {+ "number": "G6",+ "name": "GPIO[22]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[5], FLAGB in Slave FIFO mode."+ },+ {+ "number": "G7",+ "name": "GPIO[21]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[4], FLAGA in Slave FIFO mode."+ },+ {+ "number": "G8",+ "name": "GPIO[15]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[15] (Slave FIFO data)."+ },+ {+ "number": "G9",+ "name": "GPIO[4]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[4] (Slave FIFO data)."+ },+ {+ "number": "G10",+ "name": "GPIO[3]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[3] (Slave FIFO data)."+ },+ {+ "number": "G11",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "H1",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "H2",+ "name": "GPIO[39]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[22] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "H3",+ "name": "GPIO[40]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[23] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "H4",+ "name": "GPIO[31]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; PMODE[1] mode-select input."+ },+ {+ "number": "H5",+ "name": "GPIO[29]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[12], A0 in Slave FIFO mode."+ },+ {+ "number": "H6",+ "name": "GPIO[26]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[9], GPIO in Slave FIFO mode."+ },+ {+ "number": "H7",+ "name": "GPIO[20]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[3], SLRD# in Slave FIFO mode."+ },+ {+ "number": "H8",+ "name": "GPIO[24]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[7], PKTEND# in Slave FIFO mode."+ },+ {+ "number": "H9",+ "name": "GPIO[7]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[7] (Slave FIFO data)."+ },+ {+ "number": "H10",+ "name": "GPIO[6]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[6] (Slave FIFO data)."+ },+ {+ "number": "H11",+ "name": "VIO1",+ "type": "power_in",+ "description": "I/O supply for the VIO1 domain (GPIF II); the datasheet states it cannot be turned off if GPIF II is used."+ },+ {+ "number": "J1",+ "name": "GPIO[38]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[21] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "J2",+ "name": "GPIO[36]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[19] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "J3",+ "name": "GPIO[37]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[20] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "J4",+ "name": "GPIO[34]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[17] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "J5",+ "name": "GPIO[28]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[11], A1 in Slave FIFO mode."+ },+ {+ "number": "J6",+ "name": "GPIO[16]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; PCLK, CLK in Slave FIFO mode."+ },+ {+ "number": "J7",+ "name": "GPIO[19]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[2], SLOE# in Slave FIFO mode."+ },+ {+ "number": "J8",+ "name": "GPIO[14]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[14] (Slave FIFO data)."+ },+ {+ "number": "J9",+ "name": "GPIO[9]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[9] (Slave FIFO data)."+ },+ {+ "number": "J10",+ "name": "GPIO[8]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[8] (Slave FIFO data)."+ },+ {+ "number": "J11",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "K1",+ "name": "GPIO[35]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[18] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "K2",+ "name": "GPIO[33]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[16] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "K3",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "K4",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "K5",+ "name": "GPIO[27]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[10], GPIO in Slave FIFO mode."+ },+ {+ "number": "K6",+ "name": "GPIO[23]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[6], GPIO in Slave FIFO mode."+ },+ {+ "number": "K7",+ "name": "GPIO[18]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[1], SLWR# in Slave FIFO mode."+ },+ {+ "number": "K8",+ "name": "GPIO[17]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[0], SLCS# in Slave FIFO mode."+ },+ {+ "number": "K9",+ "name": "GPIO[13]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[13] (Slave FIFO data)."+ },+ {+ "number": "K10",+ "name": "GPIO[12]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[12] (Slave FIFO data)."+ },+ {+ "number": "K11",+ "name": "GPIO[10]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[10] (Slave FIFO data)."+ },+ {+ "number": "L1",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "L2",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "L3",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "L4",+ "name": "GPIO[32]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; PMODE[2] mode-select input."+ },+ {+ "number": "L5",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "L6",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "L7",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "L8",+ "name": "INT#",+ "type": "bidirectional",+ "description": "VIO1 pin INT#/CTL[15]; CTL[15] in Slave FIFO mode and not usable as a GPIO."+ },+ {+ "number": "L9",+ "name": "VIO1",+ "type": "power_in",+ "description": "I/O supply for the VIO1 domain (GPIF II); the datasheet states it cannot be turned off if GPIF II is used."+ },+ {+ "number": "L10",+ "name": "GPIO[11]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[11] (Slave FIFO data)."+ },+ {+ "number": "L11",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin List pages (Table 7 continuation, datasheet pages 17-18) were not supplied. Ball names for power; The package hint is 121-ball BGA and CYUSB3014-BZXI is the 121-ball BGA in Table 20 (–40 °C to +85 °; The XTALIN and XTALOUT pins are listed as I/O in Table 7 and were typed passive. The ball-count pull",+ "16/121 pins cited to the wrong page (name found elsewhere): ['A11:NC@p14', 'B1:VIO4@p14', 'B11:TRST#@p13', 'C10:TDO@p14']"+ ],+ "pages_sent": 15,+ "cost_usd": 0.3735,+ "at": "2026-10-22T20:03:25"+ },+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/9bf8eaa3d2ea4b51ad0ef9dc0c29253c.pdf",+ "pages": 52,+ "sha256": "87a3bd0918148fc2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 121,+ "described": 121,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cyusb3014-bzxi.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9.0,+ 9.0,+ 1.112+ ],+ "zmin_mm": -0.01,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "8da48d27804a2e36a4eccc28349fa8bbe4edb4cdcc7ec213934cac35ca478f69",+ "checked": "2026-10-22",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cyusb3014-bzxi-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9.0,+ 9.0,+ 1.112+ ],+ "zmin_mm": -0.01,+ "centre_offset_mm": 0.0,+ "footprint_binding": "identity",+ "sha256": "7c54e69a184cd84103ce664ce39efd3f996a4dc4c2b7046d4775b299492f9738",+ "checked": "2026-10-22",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ }+}
page.jsonadded+877@@ -0,0 +1,877 @@+{+ "slug": "cyusb3014-bzxi",+ "version": "0.1.0",+ "type": "component",+ "description": "Cypress Semicon CYPRESS, BGA-121. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "embedded processors & controllers",+ "cyusb3014-bzxi",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "cyusb3014-bzxi.kicad_sym",+ "cyusb3014-bzxi.kicad_mod",+ "cyusb3014-bzxi.glb",+ "cyusb3014-bzxi.step",+ "cyusb3014-bzxi.lbr",+ "docs/hero.png",+ "docs/cyusb3014-bzxi-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "cyusb3014-bzxi-hero.glb",+ "cyusb3014-bzxi-hero.overlay.json",+ "cyusb3014-bzxi-etched.glb"+ ],+ "component": {+ "mpn": "CYUSB3014-BZXI",+ "manufacturer": "Cypress Semicon",+ "package": "BGA-121",+ "pin_count": 121,+ "category": "Embedded Processors & Controllers",+ "subcategory": "CYPRESS",+ "datasheet": "https://datasheet.lcsc.com/datasheet/pdf/9bf8eaa3d2ea4b51ad0ef9dc0c29253c.pdf",+ "parts": {+ "symbol": "cyusb3014-bzxi.kicad_sym",+ "footprint": "cyusb3014-bzxi.kicad_mod",+ "model_3d": "cyusb3014-bzxi-hero.glb",+ "model_3d_plain": "cyusb3014-bzxi-etched.glb",+ "model_3d_step": "cyusb3014-bzxi-etched.step",+ "model_3d_step_plain": "cyusb3014-bzxi.step",+ "lbr": "cyusb3014-bzxi.lbr"+ },+ "distributor_links": {+ "lcsc": "C57294"+ },+ "distributor_check": {+ "checked_at": "2026-10-22T20:04:12Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "quota"+ },+ "mouser": {+ "pn": null,+ "status": "quota"+ }+ },+ "pins": [+ {+ "number": "A1",+ "name": "U3VSSQ",+ "type": "power_in",+ "description": "Ground return for the USB 3.0 transceiver supply domain (U3RXVDDQ/U3TXVDDQ), shown on the 121-ball BGA map."+ },+ {+ "number": "A2",+ "name": "U3RXVDDQ",+ "type": "power_in",+ "description": "USB 3.0 receive-side supply input; the datasheet requires a bypass capacitor on this pin."+ },+ {+ "number": "A3",+ "name": "SSRXM",+ "type": "input",+ "description": "USB 3.0 SuperSpeed receive differential input, negative (SSRX-)."+ },+ {+ "number": "A4",+ "name": "SSRXP",+ "type": "input",+ "description": "USB 3.0 SuperSpeed receive differential input, positive (SSRX+)."+ },+ {+ "number": "A5",+ "name": "SSTXP",+ "type": "output",+ "description": "USB 3.0 SuperSpeed transmit differential output, positive (SSTX+)."+ },+ {+ "number": "A6",+ "name": "SSTXM",+ "type": "output",+ "description": "USB 3.0 SuperSpeed transmit differential output, negative (SSTX-)."+ },+ {+ "number": "A7",+ "name": "AVDD",+ "type": "power_in",+ "description": "Analog supply for the crystal oscillator/PLL domain (XTALIN and XTALOUT are in the AVDD domain)."+ },+ {+ "number": "A8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "A9",+ "name": "DP",+ "type": "bidirectional",+ "description": "USB 2.0 D+ data line."+ },+ {+ "number": "A10",+ "name": "DM",+ "type": "bidirectional",+ "description": "USB 2.0 D- data line."+ },+ {+ "number": "A11",+ "name": "NC",+ "type": "unconnected",+ "description": "No connect."+ },+ {+ "number": "B1",+ "name": "VIO4",+ "type": "power_in",+ "description": "I/O supply for the VIO4 domain (GPIO[53] to GPIO[57])."+ },+ {+ "number": "B2",+ "name": "FSLC[0]",+ "type": "input",+ "description": "Clock input frequency select bit 0 (FSLC[0]), CVDDQ domain."+ },+ {+ "number": "B3",+ "name": "R_USB3",+ "type": "passive",+ "description": "Precision resistor pin for USB 3.0: connect a 200 ohm ±1% resistor between this pin and GND."+ },+ {+ "number": "B4",+ "name": "FSLC[1]",+ "type": "input",+ "description": "Clock input frequency select bit 1 (FSLC[1]), CVDDQ domain."+ },+ {+ "number": "B5",+ "name": "U3TXVDDQ",+ "type": "power_in",+ "description": "USB 3.0 transmit-side supply input; the datasheet requires a bypass capacitor on this pin."+ },+ {+ "number": "B6",+ "name": "CVDDQ",+ "type": "power_in",+ "description": "Supply for the clock and reset input domain (FSLC[2:0], CLKIN)."+ },+ {+ "number": "B7",+ "name": "AVSS",+ "type": "power_in",+ "description": "Analog ground."+ },+ {+ "number": "B8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "B9",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "B10",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "B11",+ "name": "TRST#",+ "type": "input",+ "description": "JTAG test reset, active low, with a fixed 50-kohm internal pull-up."+ },+ {+ "number": "C1",+ "name": "GPIO[54]",+ "type": "bidirectional",+ "description": "VIO4 GPIO; UART_CTS or SPI_SSN, I2S_CLK in the I2S+GPIO configuration, otherwise GPIO."+ },+ {+ "number": "C2",+ "name": "GPIO[55]",+ "type": "bidirectional",+ "description": "VIO4 GPIO; UART_TX or SPI_MISO, I2S_SD in the I2S+GPIO configuration, otherwise GPIO."+ },+ {+ "number": "C3",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "C4",+ "name": "GPIO[57]",+ "type": "bidirectional",+ "description": "VIO4 GPIO; I2S_MCLK in the UART+SPI+I2S and I2S+GPIO configurations, otherwise GPIO."+ },+ {+ "number": "C5",+ "name": "RESET#",+ "type": "input",+ "description": "Hard reset input, active low; its assertion wakes the device from low-power modes."+ },+ {+ "number": "C6",+ "name": "XTALIN",+ "type": "passive",+ "description": "Crystal input (AVDD domain); a 19.2-MHz crystal may be used, or a clock may be supplied on CLKIN instead."+ },+ {+ "number": "C7",+ "name": "XTALOUT",+ "type": "passive",+ "description": "Crystal output (AVDD domain)."+ },+ {+ "number": "C8",+ "name": "R_USB2",+ "type": "passive",+ "description": "Precision resistor pin for USB 2.0: connect a 6.04 kohm ±1% resistor between this pin and GND."+ },+ {+ "number": "C9",+ "name": "OTG_ID",+ "type": "input",+ "description": "USB OTG ID input; an impedance change on this pin is a wakeup source from suspend."+ },+ {+ "number": "C10",+ "name": "TDO",+ "type": "output",+ "description": "JTAG test data output."+ },+ {+ "number": "C11",+ "name": "VIO5",+ "type": "power_in",+ "description": "I/O supply for the VIO5 domain (I2C_GPIO[58], I2C_GPIO[59], O[60])."+ },+ {+ "number": "D1",+ "name": "GPIO[50]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; I2S_CLK in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO."+ },+ {+ "number": "D2",+ "name": "GPIO[51]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; I2S_SD in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO."+ },+ {+ "number": "D3",+ "name": "GPIO[52]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; I2S_WS in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO."+ },+ {+ "number": "D4",+ "name": "GPIO[53]",+ "type": "bidirectional",+ "description": "VIO4 GPIO; UART_RTS or SPI_SCK depending on configuration, otherwise GPIO."+ },+ {+ "number": "D5",+ "name": "GPIO[56]",+ "type": "bidirectional",+ "description": "VIO4 GPIO; UART_RX or SPI_MOSI, I2S_WS in the I2S+GPIO configuration, otherwise GPIO."+ },+ {+ "number": "D6",+ "name": "CLKIN_32",+ "type": "input",+ "description": "32-kHz watchdog timer clock input."+ },+ {+ "number": "D7",+ "name": "CLKIN",+ "type": "input",+ "description": "External clock input (CVDDQ domain), alternative to the crystal; selectable 19.2, 26, 38.4 or 52 MHz."+ },+ {+ "number": "D8",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "D9",+ "name": "I2C_GPIO[58]",+ "type": "bidirectional",+ "description": "I2C / GPIO pin in the VIO5 domain; I2C operation at 1.2 V to 3.3 V."+ },+ {+ "number": "D10",+ "name": "I2C_GPIO[59]",+ "type": "bidirectional",+ "description": "I2C / GPIO pin in the VIO5 domain; I2C operation at 1.2 V to 3.3 V."+ },+ {+ "number": "D11",+ "name": "O[60]",+ "type": "output",+ "description": "Output pin O[60] in the VIO5 domain."+ },+ {+ "number": "E1",+ "name": "GPIO[47]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; DQ[29] in the 32-bit data bus configuration, UART_CTS in the UART configurations, otherwise GPIO."+ },+ {+ "number": "E2",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "E3",+ "name": "VIO3",+ "type": "power_in",+ "description": "I/O supply for the VIO3 domain (GPIO[46] to GPIO[52])."+ },+ {+ "number": "E4",+ "name": "GPIO[49]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; DQ[31] in the 32-bit data bus configuration, UART_RX in the UART configurations, otherwise GPIO."+ },+ {+ "number": "E5",+ "name": "GPIO[48]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; DQ[30] in the 32-bit data bus configuration, UART_TX in the UART configurations, otherwise GPIO."+ },+ {+ "number": "E6",+ "name": "FSLC[2]",+ "type": "input",+ "description": "Clock input frequency select bit 2 (FSLC[2]), CVDDQ domain."+ },+ {+ "number": "E7",+ "name": "TDI",+ "type": "input",+ "description": "JTAG test data input, with a fixed 50-kohm internal pull-up."+ },+ {+ "number": "E8",+ "name": "TMS",+ "type": "input",+ "description": "JTAG test mode select, with a fixed 50-kohm internal pull-up."+ },+ {+ "number": "E9",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "E10",+ "name": "VBATT",+ "type": "power_in",+ "description": "USB battery-power supply input (VBATT)."+ },+ {+ "number": "E11",+ "name": "VBUS",+ "type": "power_in",+ "description": "USB VBUS supply/detect input; VBUS detection is a wakeup source."+ },+ {+ "number": "F1",+ "name": "VIO2",+ "type": "power_in",+ "description": "I/O supply for the VIO2 domain (GPIO[33] to GPIO[45])."+ },+ {+ "number": "F2",+ "name": "GPIO[45]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; GPIO function in all interface configurations."+ },+ {+ "number": "F3",+ "name": "GPIO[44]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[27] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "F4",+ "name": "GPIO[41]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[24] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "F5",+ "name": "GPIO[46]",+ "type": "bidirectional",+ "description": "VIO3 GPIO; DQ[28] in the 32-bit data bus configuration, UART_RTS in the UART configurations, otherwise GPIO."+ },+ {+ "number": "F6",+ "name": "TCK",+ "type": "input",+ "description": "JTAG test clock, with a fixed 10-kohm internal pull-down."+ },+ {+ "number": "F7",+ "name": "GPIO[2]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[2] (Slave FIFO data)."+ },+ {+ "number": "F8",+ "name": "GPIO[5]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[5] (Slave FIFO data)."+ },+ {+ "number": "F9",+ "name": "GPIO[1]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[1] (Slave FIFO data)."+ },+ {+ "number": "F10",+ "name": "GPIO[0]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[0] (Slave FIFO data)."+ },+ {+ "number": "F11",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "G1",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "G2",+ "name": "GPIO[42]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[25] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "G3",+ "name": "GPIO[43]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[26] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "G4",+ "name": "GPIO[30]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; PMODE[0] mode-select input."+ },+ {+ "number": "G5",+ "name": "GPIO[25]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[8], GPIO in Slave FIFO mode."+ },+ {+ "number": "G6",+ "name": "GPIO[22]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[5], FLAGB in Slave FIFO mode."+ },+ {+ "number": "G7",+ "name": "GPIO[21]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[4], FLAGA in Slave FIFO mode."+ },+ {+ "number": "G8",+ "name": "GPIO[15]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[15] (Slave FIFO data)."+ },+ {+ "number": "G9",+ "name": "GPIO[4]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[4] (Slave FIFO data)."+ },+ {+ "number": "G10",+ "name": "GPIO[3]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[3] (Slave FIFO data)."+ },+ {+ "number": "G11",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "H1",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "H2",+ "name": "GPIO[39]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[22] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "H3",+ "name": "GPIO[40]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[23] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "H4",+ "name": "GPIO[31]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; PMODE[1] mode-select input."+ },+ {+ "number": "H5",+ "name": "GPIO[29]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[12], A0 in Slave FIFO mode."+ },+ {+ "number": "H6",+ "name": "GPIO[26]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[9], GPIO in Slave FIFO mode."+ },+ {+ "number": "H7",+ "name": "GPIO[20]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[3], SLRD# in Slave FIFO mode."+ },+ {+ "number": "H8",+ "name": "GPIO[24]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[7], PKTEND# in Slave FIFO mode."+ },+ {+ "number": "H9",+ "name": "GPIO[7]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[7] (Slave FIFO data)."+ },+ {+ "number": "H10",+ "name": "GPIO[6]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[6] (Slave FIFO data)."+ },+ {+ "number": "H11",+ "name": "VIO1",+ "type": "power_in",+ "description": "I/O supply for the VIO1 domain (GPIF II); the datasheet states it cannot be turned off if GPIF II is used."+ },+ {+ "number": "J1",+ "name": "GPIO[38]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[21] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "J2",+ "name": "GPIO[36]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[19] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "J3",+ "name": "GPIO[37]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[20] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "J4",+ "name": "GPIO[34]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[17] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "J5",+ "name": "GPIO[28]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[11], A1 in Slave FIFO mode."+ },+ {+ "number": "J6",+ "name": "GPIO[16]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; PCLK, CLK in Slave FIFO mode."+ },+ {+ "number": "J7",+ "name": "GPIO[19]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[2], SLOE# in Slave FIFO mode."+ },+ {+ "number": "J8",+ "name": "GPIO[14]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[14] (Slave FIFO data)."+ },+ {+ "number": "J9",+ "name": "GPIO[9]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[9] (Slave FIFO data)."+ },+ {+ "number": "J10",+ "name": "GPIO[8]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[8] (Slave FIFO data)."+ },+ {+ "number": "J11",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "K1",+ "name": "GPIO[35]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[18] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "K2",+ "name": "GPIO[33]",+ "type": "bidirectional",+ "description": "VIO2 GPIO; DQ[16] in the 32-bit data bus configuration, otherwise GPIO."+ },+ {+ "number": "K3",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "K4",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "K5",+ "name": "GPIO[27]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[10], GPIO in Slave FIFO mode."+ },+ {+ "number": "K6",+ "name": "GPIO[23]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[6], GPIO in Slave FIFO mode."+ },+ {+ "number": "K7",+ "name": "GPIO[18]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[1], SLWR# in Slave FIFO mode."+ },+ {+ "number": "K8",+ "name": "GPIO[17]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; CTL[0], SLCS# in Slave FIFO mode."+ },+ {+ "number": "K9",+ "name": "GPIO[13]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[13] (Slave FIFO data)."+ },+ {+ "number": "K10",+ "name": "GPIO[12]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[12] (Slave FIFO data)."+ },+ {+ "number": "K11",+ "name": "GPIO[10]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[10] (Slave FIFO data)."+ },+ {+ "number": "L1",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "L2",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "L3",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "L4",+ "name": "GPIO[32]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; PMODE[2] mode-select input."+ },+ {+ "number": "L5",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "L6",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ },+ {+ "number": "L7",+ "name": "VDD",+ "type": "power_in",+ "description": "Core power supply (core operates at 1.2 V)."+ },+ {+ "number": "L8",+ "name": "INT#",+ "type": "bidirectional",+ "description": "VIO1 pin INT#/CTL[15]; CTL[15] in Slave FIFO mode and not usable as a GPIO."+ },+ {+ "number": "L9",+ "name": "VIO1",+ "type": "power_in",+ "description": "I/O supply for the VIO1 domain (GPIF II); the datasheet states it cannot be turned off if GPIF II is used."+ },+ {+ "number": "L10",+ "name": "GPIO[11]",+ "type": "bidirectional",+ "description": "VIO1 GPIF II pin; DQ[11] (Slave FIFO data)."+ },+ {+ "number": "L11",+ "name": "VSS",+ "type": "power_in",+ "description": "Ground."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-sonnet-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin List pages (Table 7 continuation, datasheet pages 17-18) were not supplied. Ball names for power; The package hint is 121-ball BGA and CYUSB3014-BZXI is the 121-ball BGA in Table 20 (–40 °C to +85 °; The XTALIN and XTALOUT pins are listed as I/O in Table 7 and were typed passive. The ball-count pull",+ "16/121 pins cited to the wrong page (name found elsewhere): ['A11:NC@p14', 'B1:VIO4@p14', 'B11:TRST#@p13', 'C10:TDO@p14']"+ ],+ "pages_sent": 15,+ "cost_usd": 0.3735,+ "at": "2026-10-22T20:03:25"+ },+ "datasheet": {+ "url": "https://datasheet.lcsc.com/datasheet/pdf/9bf8eaa3d2ea4b51ad0ef9dc0c29253c.pdf",+ "pages": 52,+ "sha256": "87a3bd0918148fc2",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 121,+ "described": 121,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "cyusb3014-bzxi.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.112+ ],+ "zmin_mm": -0.01,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "8da48d27804a2e36a4eccc28349fa8bbe4edb4cdcc7ec213934cac35ca478f69",+ "checked": "2026-10-22",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "cyusb3014-bzxi-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 9,+ 9,+ 1.112+ ],+ "zmin_mm": -0.01,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7c54e69a184cd84103ce664ce39efd3f996a4dc4c2b7046d4775b299492f9738",+ "checked": "2026-10-22",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}
viewers/footprint.htmladded+1@@ -0,0 +1 @@+<!doctype html><title>cyusb3014-bzxi</title>
viewers/symbol.htmladded+1@@ -0,0 +1 @@+<!doctype html><title>cyusb3014-bzxi</title>