component

CYUSB3014-BZXI

Public Made by Adom

by adom

Cypress Semicon CYPRESS, BGA-121. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscyusb3014-bzxifactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CYUSB3014-BZXI

Cypress Semicon · CYPRESS · BGA-121

CYUSB3014-BZXI from Cypress Semicon, in a BGA-121. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
A1 U3VSSQ power_in Ground return for the USB 3.0 transceiver supply domain (U3RXVDDQ/U3TXVDDQ), shown on the 121-ball BGA map.
A2 U3RXVDDQ power_in USB 3.0 receive-side supply input; the datasheet requires a bypass capacitor on this pin.
A3 SSRXM input USB 3.0 SuperSpeed receive differential input, negative (SSRX-).
A4 SSRXP input USB 3.0 SuperSpeed receive differential input, positive (SSRX+).
A5 SSTXP output USB 3.0 SuperSpeed transmit differential output, positive (SSTX+).
A6 SSTXM output USB 3.0 SuperSpeed transmit differential output, negative (SSTX-).
A7 AVDD power_in Analog supply for the crystal oscillator/PLL domain (XTALIN and XTALOUT are in the AVDD domain).
A8 VSS power_in Ground.
A9 DP bidirectional USB 2.0 D+ data line.
A10 DM bidirectional USB 2.0 D- data line.
A11 NC unconnected No connect.
B1 VIO4 power_in I/O supply for the VIO4 domain (GPIO[53] to GPIO[57]).
B2 FSLC[0] input Clock input frequency select bit 0 (FSLC[0]), CVDDQ domain.
B3 R_USB3 passive Precision resistor pin for USB 3.0: connect a 200 ohm ±1% resistor between this pin and GND.
B4 FSLC[1] input Clock input frequency select bit 1 (FSLC[1]), CVDDQ domain.
B5 U3TXVDDQ power_in USB 3.0 transmit-side supply input; the datasheet requires a bypass capacitor on this pin.
B6 CVDDQ power_in Supply for the clock and reset input domain (FSLC[2:0], CLKIN).
B7 AVSS power_in Analog ground.
B8 VSS power_in Ground.
B9 VSS power_in Ground.
B10 VDD power_in Core power supply (core operates at 1.2 V).
B11 TRST# input JTAG test reset, active low, with a fixed 50-kohm internal pull-up.
C1 GPIO[54] bidirectional VIO4 GPIO; UART_CTS or SPI_SSN, I2S_CLK in the I2S+GPIO configuration, otherwise GPIO.
C2 GPIO[55] bidirectional VIO4 GPIO; UART_TX or SPI_MISO, I2S_SD in the I2S+GPIO configuration, otherwise GPIO.
C3 VDD power_in Core power supply (core operates at 1.2 V).
C4 GPIO[57] bidirectional VIO4 GPIO; I2S_MCLK in the UART+SPI+I2S and I2S+GPIO configurations, otherwise GPIO.
C5 RESET# input Hard reset input, active low; its assertion wakes the device from low-power modes.
C6 XTALIN passive Crystal input (AVDD domain); a 19.2-MHz crystal may be used, or a clock may be supplied on CLKIN instead.
C7 XTALOUT passive Crystal output (AVDD domain).
C8 R_USB2 passive Precision resistor pin for USB 2.0: connect a 6.04 kohm ±1% resistor between this pin and GND.
C9 OTG_ID input USB OTG ID input; an impedance change on this pin is a wakeup source from suspend.
C10 TDO output JTAG test data output.
C11 VIO5 power_in I/O supply for the VIO5 domain (I2C_GPIO[58], I2C_GPIO[59], O[60]).
D1 GPIO[50] bidirectional VIO3 GPIO; I2S_CLK in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO.
D2 GPIO[51] bidirectional VIO3 GPIO; I2S_SD in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO.
D3 GPIO[52] bidirectional VIO3 GPIO; I2S_WS in the UART+SPI+I2S and 16-bit Data Bus + I2S configurations, otherwise GPIO.
D4 GPIO[53] bidirectional VIO4 GPIO; UART_RTS or SPI_SCK depending on configuration, otherwise GPIO.
D5 GPIO[56] bidirectional VIO4 GPIO; UART_RX or SPI_MOSI, I2S_WS in the I2S+GPIO configuration, otherwise GPIO.
D6 CLKIN_32 input 32-kHz watchdog timer clock input.
D7 CLKIN input External clock input (CVDDQ domain), alternative to the crystal; selectable 19.2, 26, 38.4 or 52 MHz.
D8 VSS power_in Ground.
D9 I2C_GPIO[58] bidirectional I2C / GPIO pin in the VIO5 domain; I2C operation at 1.2 V to 3.3 V.
D10 I2C_GPIO[59] bidirectional I2C / GPIO pin in the VIO5 domain; I2C operation at 1.2 V to 3.3 V.
D11 O[60] output Output pin O[60] in the VIO5 domain.
E1 GPIO[47] bidirectional VIO3 GPIO; DQ[29] in the 32-bit data bus configuration, UART_CTS in the UART configurations, otherwise GPIO.
E2 VSS power_in Ground.
E3 VIO3 power_in I/O supply for the VIO3 domain (GPIO[46] to GPIO[52]).
E4 GPIO[49] bidirectional VIO3 GPIO; DQ[31] in the 32-bit data bus configuration, UART_RX in the UART configurations, otherwise GPIO.
E5 GPIO[48] bidirectional VIO3 GPIO; DQ[30] in the 32-bit data bus configuration, UART_TX in the UART configurations, otherwise GPIO.
E6 FSLC[2] input Clock input frequency select bit 2 (FSLC[2]), CVDDQ domain.
E7 TDI input JTAG test data input, with a fixed 50-kohm internal pull-up.
E8 TMS input JTAG test mode select, with a fixed 50-kohm internal pull-up.
E9 VDD power_in Core power supply (core operates at 1.2 V).
E10 VBATT power_in USB battery-power supply input (VBATT).
E11 VBUS power_in USB VBUS supply/detect input; VBUS detection is a wakeup source.
F1 VIO2 power_in I/O supply for the VIO2 domain (GPIO[33] to GPIO[45]).
F2 GPIO[45] bidirectional VIO2 GPIO; GPIO function in all interface configurations.
F3 GPIO[44] bidirectional VIO2 GPIO; DQ[27] in the 32-bit data bus configuration, otherwise GPIO.
F4 GPIO[41] bidirectional VIO2 GPIO; DQ[24] in the 32-bit data bus configuration, otherwise GPIO.
F5 GPIO[46] bidirectional VIO3 GPIO; DQ[28] in the 32-bit data bus configuration, UART_RTS in the UART configurations, otherwise GPIO.
F6 TCK input JTAG test clock, with a fixed 10-kohm internal pull-down.
F7 GPIO[2] bidirectional VIO1 GPIF II pin; DQ[2] (Slave FIFO data).
F8 GPIO[5] bidirectional VIO1 GPIF II pin; DQ[5] (Slave FIFO data).
F9 GPIO[1] bidirectional VIO1 GPIF II pin; DQ[1] (Slave FIFO data).
F10 GPIO[0] bidirectional VIO1 GPIF II pin; DQ[0] (Slave FIFO data).
F11 VDD power_in Core power supply (core operates at 1.2 V).
G1 VSS power_in Ground.
G2 GPIO[42] bidirectional VIO2 GPIO; DQ[25] in the 32-bit data bus configuration, otherwise GPIO.
G3 GPIO[43] bidirectional VIO2 GPIO; DQ[26] in the 32-bit data bus configuration, otherwise GPIO.
G4 GPIO[30] bidirectional VIO1 GPIF II pin; PMODE[0] mode-select input.
G5 GPIO[25] bidirectional VIO1 GPIF II pin; CTL[8], GPIO in Slave FIFO mode.
G6 GPIO[22] bidirectional VIO1 GPIF II pin; CTL[5], FLAGB in Slave FIFO mode.
G7 GPIO[21] bidirectional VIO1 GPIF II pin; CTL[4], FLAGA in Slave FIFO mode.
G8 GPIO[15] bidirectional VIO1 GPIF II pin; DQ[15] (Slave FIFO data).
G9 GPIO[4] bidirectional VIO1 GPIF II pin; DQ[4] (Slave FIFO data).
G10 GPIO[3] bidirectional VIO1 GPIF II pin; DQ[3] (Slave FIFO data).
G11 VSS power_in Ground.
H1 VDD power_in Core power supply (core operates at 1.2 V).
H2 GPIO[39] bidirectional VIO2 GPIO; DQ[22] in the 32-bit data bus configuration, otherwise GPIO.
H3 GPIO[40] bidirectional VIO2 GPIO; DQ[23] in the 32-bit data bus configuration, otherwise GPIO.
H4 GPIO[31] bidirectional VIO1 GPIF II pin; PMODE[1] mode-select input.
H5 GPIO[29] bidirectional VIO1 GPIF II pin; CTL[12], A0 in Slave FIFO mode.
H6 GPIO[26] bidirectional VIO1 GPIF II pin; CTL[9], GPIO in Slave FIFO mode.
H7 GPIO[20] bidirectional VIO1 GPIF II pin; CTL[3], SLRD# in Slave FIFO mode.
H8 GPIO[24] bidirectional VIO1 GPIF II pin; CTL[7], PKTEND# in Slave FIFO mode.
H9 GPIO[7] bidirectional VIO1 GPIF II pin; DQ[7] (Slave FIFO data).
H10 GPIO[6] bidirectional VIO1 GPIF II pin; DQ[6] (Slave FIFO data).
H11 VIO1 power_in I/O supply for the VIO1 domain (GPIF II); the datasheet states it cannot be turned off if GPIF II is used.
J1 GPIO[38] bidirectional VIO2 GPIO; DQ[21] in the 32-bit data bus configuration, otherwise GPIO.
J2 GPIO[36] bidirectional VIO2 GPIO; DQ[19] in the 32-bit data bus configuration, otherwise GPIO.
J3 GPIO[37] bidirectional VIO2 GPIO; DQ[20] in the 32-bit data bus configuration, otherwise GPIO.
J4 GPIO[34] bidirectional VIO2 GPIO; DQ[17] in the 32-bit data bus configuration, otherwise GPIO.
J5 GPIO[28] bidirectional VIO1 GPIF II pin; CTL[11], A1 in Slave FIFO mode.
J6 GPIO[16] bidirectional VIO1 GPIF II pin; PCLK, CLK in Slave FIFO mode.
J7 GPIO[19] bidirectional VIO1 GPIF II pin; CTL[2], SLOE# in Slave FIFO mode.
J8 GPIO[14] bidirectional VIO1 GPIF II pin; DQ[14] (Slave FIFO data).
J9 GPIO[9] bidirectional VIO1 GPIF II pin; DQ[9] (Slave FIFO data).
J10 GPIO[8] bidirectional VIO1 GPIF II pin; DQ[8] (Slave FIFO data).
J11 VDD power_in Core power supply (core operates at 1.2 V).
K1 GPIO[35] bidirectional VIO2 GPIO; DQ[18] in the 32-bit data bus configuration, otherwise GPIO.
K2 GPIO[33] bidirectional VIO2 GPIO; DQ[16] in the 32-bit data bus configuration, otherwise GPIO.
K3 VSS power_in Ground.
K4 VSS power_in Ground.
K5 GPIO[27] bidirectional VIO1 GPIF II pin; CTL[10], GPIO in Slave FIFO mode.
K6 GPIO[23] bidirectional VIO1 GPIF II pin; CTL[6], GPIO in Slave FIFO mode.
K7 GPIO[18] bidirectional VIO1 GPIF II pin; CTL[1], SLWR# in Slave FIFO mode.
K8 GPIO[17] bidirectional VIO1 GPIF II pin; CTL[0], SLCS# in Slave FIFO mode.
K9 GPIO[13] bidirectional VIO1 GPIF II pin; DQ[13] (Slave FIFO data).
K10 GPIO[12] bidirectional VIO1 GPIF II pin; DQ[12] (Slave FIFO data).
K11 GPIO[10] bidirectional VIO1 GPIF II pin; DQ[10] (Slave FIFO data).
L1 VSS power_in Ground.
L2 VSS power_in Ground.
L3 VSS power_in Ground.
L4 GPIO[32] bidirectional VIO1 GPIF II pin; PMODE[2] mode-select input.
L5 VDD power_in Core power supply (core operates at 1.2 V).
L6 VSS power_in Ground.
L7 VDD power_in Core power supply (core operates at 1.2 V).
L8 INT# bidirectional VIO1 pin INT#/CTL[15]; CTL[15] in Slave FIFO mode and not usable as a GPIO.
L9 VIO1 power_in I/O supply for the VIO1 domain (GPIF II); the datasheet states it cannot be turned off if GPIF II is used.
L10 GPIO[11] bidirectional VIO1 GPIF II pin; DQ[11] (Slave FIFO data).
L11 VSS power_in Ground.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package BGA-121
Category Embedded Processors & Controllers
Pins 121

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature -65 150 °C 19
Ambient temperature with power supplied (Industrial) -40 85 °C Industrial 19
Supply voltage VDD, AVDDQ VDD, AVDDQ 1.25 V Supply voltage to ground potential 19
Supply voltage VIO1-VIO5 VIO1, VIO2, VIO3, VIO4, VIO5 3.6 V Supply voltage to ground potential 19
Supply voltage U3TXVDDQ, U3RXVDDQ U3TXVDDQ, U3RXVDDQ 1.25 V Supply voltage to ground potential 19
ESD protection HBM -2.2 2.2 kV HBM based on JESD22-A114 19
Latch-up current 200 mA > 200 mA 19
Maximum output short-circuit current -100 mA All I/O configurations, Vout = 0 V 19
Ambient temperature under bias (Industrial) TA -40 85 °C Industrial 19
Supply voltage VDD, AVDDQ, U3TXVDDQ, U3RXVDDQ VDD 1.15 1.25 V 19
VBATT supply voltage VBATT 3.2 6 V 19
VIO1-VIO4, CVDDQ supply voltage VIO1, VIO2, VIO3, VIO4, CVDDQ 1.7 3.6 V 19
VIO5 supply voltage VIO5 1.15 3.6 V 19
Core voltage supply VDD 1.15 1.25 V 1.2-V typical 19
Analog voltage supply AVDD 1.15 1.25 V 1.2-V typical 19
GPIF II I/O power supply domain VIO1 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical 19
IO2 power supply domain VIO2 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical 19
IO3 power supply domain VIO3 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical 19
UART/SPI/I2S power supply domain VIO4 1.7 3.6 V 1.8-, 2.5-, and 3.3-V typical 19
USB voltage supply VBATT 3.2 6 V 3.7-V typical 19
USB voltage supply VBUS 4 6 V 5-V typical 19
USB 3.0 1.2-V supply U3TXVDDQ 1.15 1.25 V 1.2-V typical. A 22-µF bypass capacitor is required 19
Clock voltage supply CVDDQ 1.7 3.6 V 1.8-, 3.3-V typical 19
I2C and JTAG voltage supply VIO5 1.15 3.6 V 1.2-, 1.8-, 2.5-, and 3.3-V typical 19
Input leakage current for all pins except SSTXP/SSXM/SSRXP/SSRXM IIX -1 1 µA All I/O signals held at VDDQ 20
Output High-Z leakage current for all pins except SSTXP/SSXM/SSRXP/SSRXM IOZ -1 1 µA All I/O signals held at VDDQ 20
Core and analog voltage operating current ICC Core 200 mA Total current through AVDD, VDD 20
USB voltage supply operating current ICC USB 60 mA 20
Voltage ramp rate on core and I/O supplies VRAMP 0.2 50 V/ms Voltage ramp must be monotonic 20
Noise level permitted on VDD and I/O supplies VN 100 mV Max p-p noise level permitted on all supplies except AVDD 20
Noise level permitted on AVDD supply VN_AVDD 20 mV Max p-p noise level permitted on AVDD 20
GPIO current source and sink ISS 20 mA Rating for quarter drive strength 20

CAD (KiCad official)

  • Symbol: CYUSB3014-BZXI
  • Footprint: Package_BGA:BGA-121_9.0x9.0mm_Layout11x11_P0.8mm_Ball0.4mm_Pad0.35mm_NSMD
  • 3D model: BGA-121 (KiCad packages3D, STEP)
  • 3D model files: cyusb3014-bzxi-etched.step / cyusb3014-bzxi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cyusb3014-bzxi.step / cyusb3014-bzxi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (52 pp, sha256 87a3bd0918148fc2, retrieved 2026-10-22, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF