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Infineon Technologies Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CYT2BL5CAAQ0AZEGS

Infineon Technologies · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

CYT2BL5CAAQ0AZEGS from Infineon Technologies, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VSSD	power_in	Main digital ground.
2	P0.0	bidirectional	GPIO_ENH port 0 bit 0; alternates include SCB0_RX(0)/SCB0_MISO(0), SCB7_SDA(2), LIN1_RX, TCPWM PWM0_18.
3	P0.1	bidirectional	GPIO_ENH port 0 bit 1; alternates include SCB0_TX(0)/SCB0_MOSI(0), SCB7_SCL(2), LIN1_TX, TCPWM PWM0_17.
4	P0.2	bidirectional	GPIO_ENH port 0 bit 2; alternates include SCB0_RTS(0)/SCB0_SCL(0)/SCB0_CLK(0), LIN1_EN, CAN0_1_TX.
5	P0.3	bidirectional	GPIO_ENH port 0 bit 3; alternates include SCB0_CTS(0)/SCB0_SDA(0)/SCB0_SEL0(0), CAN0_1_RX.
6	P2.0	bidirectional	GPIO_STD port 2 bit 0; alternates include SWJ_TRSTN, SCB7_RX(0)/SCB7_MISO(0), LIN0_RX, CAN0_0_TX, TRIG_IN[2].
7	P2.1	bidirectional	GPIO_STD port 2 bit 1; alternates include SCB7_TX(0)/SCB7_SDA(0)/SCB7_MOSI(0), LIN0_TX, CAN0_0_RX, TRIG_IN[3].
8	P2.2	bidirectional	GPIO_STD port 2 bit 2; alternates include SCB7_RTS(0)/SCB7_SCL(0)/SCB7_CLK(0), SCB0_SEL3(0), LIN0_EN, TRIG_IN[4].
9	P2.3	bidirectional	GPIO_STD port 2 bit 3; alternates include SCB7_CTS(0)/SCB7_SEL0(0), LIN5_RX, TRIG_IN[5].
10	P3.0	bidirectional	GPIO_STD port 3 bit 0; alternates include SCB6_RX(0)/SCB6_MISO(0), CAN0_3_TX, TRIG_DBG[0].
11	P3.1	bidirectional	GPIO_STD port 3 bit 1; alternates include SCB6_TX(0)/SCB6_SDA(0)/SCB6_MOSI(0), CAN0_3_RX, TRIG_DBG[1].
12	VDDD	power_in	Main digital supply.
13	VSSD	power_in	Main digital ground.
14	P5.0	bidirectional	GPIO_STD port 5 bit 0; alternates include SCB5_SEL2(0), LIN7_RX, PWM0_9.
15	P5.1	bidirectional	GPIO_STD port 5 bit 1; alternates include LIN7_TX, PWM0_10.
16	P5.2	bidirectional	GPIO_STD port 5 bit 2; alternates include LIN7_EN, PWM0_11.
17	P5.3	bidirectional	GPIO_STD port 5 bit 3; alternates include LIN2_RX, PWM0_12.
18	P6.0	bidirectional	GPIO_STD port 6 bit 0; ADC[0]_0 analog input, SCB4_RX(0)/SCB4_MISO(0), LIN3_RX.
19	P6.1	bidirectional	GPIO_STD port 6 bit 1; ADC[0]_1 analog input, SCB4_TX(0)/SCB4_SDA(0)/SCB4_MOSI(0), LIN3_TX.
20	P6.2	bidirectional	GPIO_STD port 6 bit 2; ADC[0]_2 analog input, SCB4_RTS(0)/SCB4_SCL(0)/SCB4_CLK(0), LIN3_EN, CAN0_2_TX.
21	P6.3	bidirectional	GPIO_STD port 6 bit 3; ADC[0]_3 analog input, SCB4_CTS(0)/SCB4_SEL0(0), LIN4_RX, CAN0_2_RX, CAL_SUP_NZ.
22	P6.4	bidirectional	GPIO_STD port 6 bit 4; ADC[0]_4 analog input, SCB4_SEL1(0), LIN4_TX.
23	P6.5	bidirectional	GPIO_STD port 6 bit 5; ADC[0]_5 analog input, SCB4_SEL2(0), LIN4_EN.
24	VDDD	power_in	Main digital supply.
25	VDDIO_1	power_in	I/O supply for group 1.
26	VSSD	power_in	Main digital ground.
27	VSSD	power_in	Main digital ground.
28	VCCD	power_out	Main regulated supply driven by the LDO regulator; VCCD pins must be connected together for low impedance.
29	P7.0	bidirectional	GPIO_STD port 7 bit 0; ADC[0]_8 analog input, SCB5_RX(1)/SCB5_MISO(1), LIN4_RX, CXPI0_RX.
30	P7.1	bidirectional	GPIO_STD port 7 bit 1; ADC[0]_9 analog input, SCB5_TX(1)/SCB5_SDA(1)/SCB5_MOSI(1), LIN4_TX, CXPI0_TX.
31	P7.2	bidirectional	GPIO_STD port 7 bit 2; ADC[0]_10 analog input, SCB5_RTS(1)/SCB5_SCL(1)/SCB5_CLK(1), LIN4_EN, CXPI0_EN.
32	P7.3	bidirectional	GPIO_STD port 7 bit 3; ADC[0]_11 analog input, SCB5_CTS(1)/SCB5_SEL0(1).
33	P7.4	bidirectional	GPIO_STD port 7 bit 4; ADC[0]_12 analog input, SCB5_SEL1(1).
34	P7.5	bidirectional	GPIO_STD port 7 bit 5; ADC[0]_13 analog input, SCB5_SEL2(1), LIN10_RX.
35	P8.0	bidirectional	GPIO_STD port 8 bit 0; alternates include LIN2_RX, CAN0_0_TX, PWM0_19.
36	P8.1	bidirectional	GPIO_STD port 8 bit 1; ADC[0]_16 analog input, LIN2_TX, CAN0_0_RX, TRIG_IN[14].
37	P8.2	bidirectional	GPIO_STD port 8 bit 2; ADC[0]_17 analog input, LIN2_EN, TRIG_IN[15].
38	P11.0	bidirectional	GPIO_STD port 11 bit 0; ADC[0]_M analog input with highest-priority simultaneous ADC capture.
39	P11.1	bidirectional	GPIO_STD port 11 bit 1; ADC[1]_M analog input with highest-priority simultaneous ADC capture.
40	P11.2	bidirectional	GPIO_STD port 11 bit 2; ADC[2]_M analog input with highest-priority simultaneous ADC capture.
41	VREFL	power_in	Low reference voltage for SAR ADC.
42	VSSA	power_in	Main analog ground.
43	VDDA	power_in	Main analog supply for the PASS SAR ADC.
44	VREFH	power_in	High reference voltage for SAR ADC.
45	P12.0	bidirectional	GPIO_STD port 12 bit 0; ADC[1]_4 analog input, CAN0_2_TX, TRIG_IN[20], SMARTIO12_0.
46	P12.1	bidirectional	GPIO_STD port 12 bit 1; ADC[1]_5 analog input, LIN6_EN, CAN0_2_RX, TRIG_IN[21], SMARTIO12_1.
47	P12.2	bidirectional	GPIO_STD port 12 bit 2; ADC[1]_6 analog input, EXT_MUX[1]_EN, LIN6_RX, SMARTIO12_2.
48	P12.3	bidirectional	GPIO_STD port 12 bit 3; ADC[1]_7 analog input, EXT_MUX[1]_0, LIN6_TX, SMARTIO12_3.
49	P12.4	bidirectional	GPIO_STD port 12 bit 4; ADC[1]_8 analog input, EXT_MUX[1]_1, SMARTIO12_4.
50	VDDIO_2	power_in	I/O supply for group 2.
51	VSSD	power_in	Main digital ground.
52	P13.0	bidirectional	GPIO_STD port 13 bit 0; ADC[1]_12 analog input, EXT_MUX[2]_0, SCB3_RX(0)/SCB3_MISO(0), LIN3_RX, CXPI1_RX.
53	P13.1	bidirectional	GPIO_STD port 13 bit 1; ADC[1]_13 analog input, EXT_MUX[2]_1, SCB3_TX(0)/SCB3_SDA(0)/SCB3_MOSI(0), LIN3_TX, CXPI1_TX.
54	P13.2	bidirectional	GPIO_STD port 13 bit 2; ADC[1]_14 analog input, EXT_MUX[2]_2, SCB3_RTS(0)/SCB3_SCL(0)/SCB3_CLK(0), LIN3_EN, CXPI1_EN.
55	P13.3	bidirectional	GPIO_STD port 13 bit 3; ADC[1]_15 analog input, EXT_MUX[2]_EN, SCB3_CTS(0)/SCB3_SEL0(0).
56	P13.4	bidirectional	GPIO_STD port 13 bit 4; ADC[1]_16 analog input, SCB3_SEL1(0), LIN8_RX, PWM0_H_4.
57	P13.5	bidirectional	GPIO_STD port 13 bit 5; ADC[1]_17 analog input, SCB3_SEL2(0), LIN8_TX, CXPI2_RX.
58	P13.6	bidirectional	GPIO_STD port 13 bit 6; ADC[1]_18 analog input, SCB3_SEL3(0), LIN8_EN, CXPI2_TX, TRIG_IN[22].
59	P13.7	bidirectional	GPIO_STD port 13 bit 7; ADC[1]_19 analog input, CXPI2_EN, TRIG_IN[23].
60	P14.0	bidirectional	GPIO_STD port 14 bit 0; ADC[1]_20 analog input, SCB2_RX(0)/SCB2_MISO(0), CAN1_0_TX.
61	P14.1	bidirectional	GPIO_STD port 14 bit 1; ADC[1]_21 analog input, SCB2_TX(0)/SCB2_SDA(0)/SCB2_MOSI(0), CAN1_0_RX.
62	P14.2	bidirectional	GPIO_STD port 14 bit 2; ADC[1]_22 analog input, SCB2_RTS(0)/SCB2_SCL(0)/SCB2_CLK(0), LIN6_RX.
63	P14.3	bidirectional	GPIO_STD port 14 bit 3; ADC[1]_23 analog input, SCB2_CTS(0)/SCB2_SEL0(0), LIN6_TX.
64	P17.0	bidirectional	GPIO_STD port 17 bit 0; CAN1_1_TX, PWM0_61, SMARTIO17_0.
65	P17.1	bidirectional	GPIO_STD port 17 bit 1; SCB3_RX(1)/SCB3_MISO(1), CAN1_1_RX, SMARTIO17_1.
66	P17.2	bidirectional	GPIO_STD port 17 bit 2; SCB3_TX(1)/SCB3_SDA(1)/SCB3_MOSI(1), SMARTIO17_2.
67	P18.0	bidirectional	GPIO_STD port 18 bit 0; ADC[2]_0 analog input, SCB1_RX(0)/SCB1_MISO(0), FAULT_OUT_0.
68	P18.1	bidirectional	GPIO_STD port 18 bit 1; ADC[2]_1 analog input, SCB1_TX(0)/SCB1_SDA(0)/SCB1_MOSI(0), FAULT_OUT_1.
69	P18.2	bidirectional	GPIO_STD port 18 bit 2; ADC[2]_2 analog input, SCB1_RTS(0)/SCB1_SCL(0)/SCB1_CLK(0).
70	P18.3	bidirectional	GPIO_STD port 18 bit 3; ADC[2]_3 analog input, SCB1_CTS(0)/SCB1_SEL0(0), TRACE_CLOCK(0).
71	P18.4	bidirectional	GPIO_STD port 18 bit 4; ADC[2]_4 analog input, SCB1_SEL1(0), TRACE_DATA_0(0).
72	P18.5	bidirectional	GPIO_STD port 18 bit 5; ADC[2]_5 analog input, SCB1_SEL2(0), TRACE_DATA_1(0).
73	P18.6	bidirectional	GPIO_STD port 18 bit 6; ADC[2]_6 analog input, SCB1_SEL3(0), CAN1_2_TX, TRACE_DATA_2(0).
74	P18.7	bidirectional	GPIO_STD port 18 bit 7; ADC[2]_7 analog input, CAN1_2_RX, TRACE_DATA_3(0).
75	VDDD	power_in	Main digital supply.
76	VSSD	power_in	Main digital ground.
77	P19.0	bidirectional	GPIO_STD port 19 bit 0; SCB2_RX(1)/SCB2_MISO(1), CAN1_3_TX, FAULT_OUT_2.
78	P19.1	bidirectional	GPIO_STD port 19 bit 1; SCB2_TX(1)/SCB2_SDA(1)/SCB2_MOSI(1), CAN1_3_RX, CXPI3_RX, FAULT_OUT_3.
79	P19.2	bidirectional	GPIO_STD port 19 bit 2; SCB2_RTS(1)/SCB2_SCL(1)/SCB2_CLK(1), CXPI3_TX, TRIG_IN[28].
80	P19.3	bidirectional	GPIO_STD port 19 bit 3; SCB2_CTS(1)/SCB2_SEL0(1), CXPI3_EN, TRIG_IN[29].
81	P21.0	bidirectional	GPIO_STD port 21 bit 0; WCO_IN watch crystal input (set high-impedance when oscillator enabled), SCB1_SEL2(1).
82	P21.1	bidirectional	GPIO_STD port 21 bit 1; WCO_OUT watch crystal output (set high-impedance when oscillator enabled).
83	P21.2	bidirectional	GPIO_STD port 21 bit 2; ECO_IN external crystal input (set high-impedance when oscillator enabled), EXT_CLK, TRIG_DBG[1].
84	P21.3	bidirectional	GPIO_STD port 21 bit 3; ECO_OUT external crystal output (set high-impedance when oscillator enabled).
85	XRES_L	input	Active LOW external reset input.
86	VDDD	power_in	Main digital supply.
87	VSSD	power_in	Main digital ground.
88	VSSD	power_in	Main digital ground.
89	VCCD	power_out	Main regulated supply driven by the LDO regulator; VCCD pins must be connected together for low impedance.
90	P21.5	bidirectional	GPIO_STD port 21 bit 5; LIN0_RX, PWM0_37.
91	P22.0	bidirectional	GPIO_STD port 22 bit 0; SCB6_RX(1)/SCB6_MISO(1), CAN1_1_TX, TRACE_DATA_0(1).
92	P22.1	bidirectional	GPIO_STD port 22 bit 1; SCB6_TX(1)/SCB6_SDA(1)/SCB6_MOSI(1), CAN1_1_RX, TRACE_DATA_1(1).
93	P22.2	bidirectional	GPIO_STD port 22 bit 2; SCB6_RTS(1)/SCB6_SCL(1)/SCB6_CLK(1), TRACE_DATA_2(1).
94	P22.3	bidirectional	GPIO_STD port 22 bit 3; SCB6_CTS(1)/SCB6_SEL0(1), TRACE_DATA_3(1).
95	P23.3	bidirectional	GPIO_STD port 23 bit 3; SCB7_CTS(1)/SCB7_SEL0(1), FAULT_OUT_3, TRIG_IN[30].
96	P23.4	bidirectional	GPIO_STD port 23 bit 4; SWJ_SWO_TDO debug output, SCB7_SEL1(1), TRIG_DBG[0], TRIG_IN[31].
97	P23.5	bidirectional	GPIO_STD port 23 bit 5; SWJ_SWCLK_TCLK debug clock, SCB7_SEL2(1), LIN9_RX.
98	P23.6	bidirectional	GPIO_STD port 23 bit 6; SWJ_SWDIO_TMS debug data, LIN9_TX.
99	P23.7	bidirectional	GPIO_STD port 23 bit 7; SWJ_SWDOE_TDI, HIBERNATE_WAKEUP[1], LIN9_EN, EXT_CLK, CAL_SUP_NZ.
100	VDDD	power_in	Main digital supply.

Key specifications

Parameter	Value
Manufacturer	Infineon Technologies
Package	LQFP-100(14x14)
Category	Single Chip Microcomputer/Microcontroller
Pins	100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power supply voltage	VDDD, VDDA, VDDIO_1, VDDIO_2	2.7		5.5	V	SID40	94
Power supply voltage for eFuse programming	VDDIO_1_EFP	3		5.5	V	SID40A	94
Smoothing capacitor	CS1	3.76		11	µF	SID41	94
VDDD power supply voltage (abs max)	VDDD_ABS	-0.3		6	V	Min VSSD, 0.3, Max VSSD + 6.0; ports 0-5, 16-23	92
VDDIO_1 power supply voltage (abs max)	VDDIO_1_ABS	-0.3		6	V	Min VSSD, 0.3, Max VSSD + 6.0; ports 6, 7, 8, 9	92
VDDIO_2 power supply voltage (abs max)	VDDIO_2_ABS	-0.3		6	V	Min VSSD, 0.3, Max VSSD + 6.0; ports 10-15	92
VDDA analog power supply voltage (abs max)	VDDA_ABS	-0.3		6	V	Min VSSA, 0.3, Max VSSA + 6.0; VDDIO_2 = VDDA	92
Analog reference voltage, HIGH	VREFH_ABS	-0.3		6	V	Min VSSA, 0.3, Max VSSA + 6.0; VREFH VDDA + 0.3 V	92
Analog reference voltage, LOW	VREFL_ABS	-0.3		0.3	V	Min VSSA, 0.3, Max VSSA + 0.3	92
Analog input voltage	VIA_ABS	-0.3		0.3	V	Min VSSA, 0.3, Max VDDA + 0.3 (offset +0.3 over VDDA)	92
Maximum clamp current	ICLAMP_ABS	-5		5	mA	SID18	92
Maximum positive clamp current per I/O supply pin	ICLAMP_SUPPLY_POS_ABS			10	mA	+B injected DC currents not allowed for Ports 11 and 21	93
Maximum negative clamp current per I/O ground pin	ICLAMP_SUPPLY_NEG_ABS			10	mA	+B injected DC currents not allowed for Ports 11 and 21	93
Maximum positive clamp current per I/O supply	ICLAMP_TOTAL_POS_ABS			50	mA	If not limited by the per supply pin (SID18A)	93
Maximum negative clamp current per I/O ground	ICLAMP_TOTAL_NEG_ABS			50	mA	If not limited by the per supply pin (SID18B)	93
LOW-level maximum output current GPIO_STD	IOL1A_ABS			6	mA	drive_sel<1:0>= 0b0X	93
HIGH-level maximum output current GPIO_STD	IOH1A_ABS			-5	mA	drive_sel<1:0>= 0b0X	93
LOW-level total output current	ΣIOL_ABS_GPIO			50	mA		93
HIGH-level total output current	ΣIOH_ABS_GPIO			-50	mA		93
Power dissipation	PD			1000	mW	TJ should not exceed 150 °C	93
Ambient temperature (E-grade)	TA	-40		125	°C	For E-grade devices	93
Storage temperature	TSTG	-55		150	°C		93
Operating junction temperature	TJ	-40		150	°C		93
ESD human body model	VESD_HBM	2000			V		93
ESD charged device model, corner pins	VESD_CDM1	750			V		93
ESD charged device model, all other pins	VESD_CDM2	500			V		93
Latch-up pin current	ILU	-100		100	mA		93
SAR ADC resolution	A_RES			12	bits		108
VREFH voltage range	A_VREFH	2.7			V	Max VDDA; ADC performance degrades when high reference is higher than supply	108
VDDA voltage range (ADC)	A_VDDA	2.7		5.5	V		108
Internal band gap reference voltage	Vband_gap	0.882	0.9	0.918	V		108
Clamp coupling ratio positive	CLAMP_COUPLING_RATIO_POS			0.25	%		108
Clamp coupling ratio negative	CLAMP_COUPLING_RATIO_NEG			1.2	%		108
Internal pin resistance to current collection point	RCLAMP_INTERNAL			50	Ω		108
Zero transition voltage	VZT	-20		20	mV	VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C before offset adjustment	110
Full-scale transition voltage	VFST	-20		20	mV	VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C before offset adjustment	110
ADC operating frequency	fADC_4P5	2		26.67	MHz	4.5 V ≤ VDDA ≤ 5.5 V	110
ADC operating frequency	fADC_2P7	2		13.34	MHz	2.7 V ≤ VDDA < 4.5 V	110
Analog input sample time, own SARMUX	tS_4P5	412			ns	4.5 V ≤ VDDA ≤ 5.5 V, Guaranteed by design	110
Analog input sample time, own SARMUX	tS_2P7	600			ns	2.7 V ≤ VDDA < 4.5 V, Guaranteed by design	110
ADC max throughput, own SARMUX	tST_4P5			1	Msps	4.5 V ≤ VDDA ≤ 5.5 V, 80 MHz / 3 = 26.67 MHz, 11 sampling cycles, 15 conversion cycles	111
ADC max throughput, own SARMUX	tST_2P7			0.5	Msps	2.7 V ≤ VDDA < 4.5 V 80 MHz / 6 = 13.3 MHz, 11 sampling cycles, 15 conversion cycles	111
ADC input sampling capacitance	CVIN			4.8	pF	Guaranteed by design	111
Input path ON resistance (4.5 V to 5.5 V)	RVIN1			9.4	kΩ	Guaranteed by design	111
Input path ON resistance (2.7 V to 4.5 V)	RVIN2			13.9	kΩ	Guaranteed by design	111
Diagnostic reference resistor ladder accuracy	ACC_RLAD	-4		4	%		111
Total error after offset and gain adjustment	A_TE	-5		5	LSb	VDDA = VREFH = 2.7 V to 5.5 V, VREFL = VSSA, -40 °C ≤ TA ≤ 125 °C, 12 bit resolution mode	111
Total error before offset and gain adjustment	A_TEB	-12		12	LSb	VDDA = VREFH = 2.7 V to 5.5 V, VREFL = VSSA, -40 °C ≤ TA ≤ 125 °C, 12 bit resolution mode	111
Integral nonlinearity	A_INL	-2.5		2.5	LSb	VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C	111
Differential nonlinearity	A_DNL	-0.99		1.9	LSb	VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C	111
Channel-to-channel variation	A_CE	-1		1	LSb	VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C	112
Analog input leakage current	IAIC	-350	70	350	nA	When input pad is selected for conversion	112
Analog power supply current while ADC is operating	IVDDA		360	550	µA	Per enabled ADC	112
Temperature sensor accuracy 2	TSENSACC2	-5		5	°C	-40 °C ≤ TJ ≤ 150 °C; 3.0 V ≤ VDDA ≤ 3.6 V or 4.5 V ≤ VDDA ≤ 5.5 V	112
Temperature sensor accuracy 3	TSENSACC3	-10		10	°C	-40 °C ≤ TJ ≤ 150 °C; 2.7 V ≤ VDDA = VREFH ≤ 5.5 V	112
Uncorrected monitor voltage divider accuracy	VMONDIV	-20	2	20	%	Any HV supply pad within 2.7 V - 5.5 V operating range	112
IMO operating frequency	fIMOTOLA	7.68	8	8.32	MHz		140
ILO operating frequency	fILOTRIM	31.1296	32.768	34.4064	kHz		140
ECO crystal frequency range	fECO	3.988		33.34	MHz		140
SWD clock input frequency	fSWDCLK			10	MHz	2.7 V ≤ VDDD ≤ 5.5 V	138
Package thermal resistance junction to ambient	RθJA			22.7	°C/Watt	100 LQFP; JESD51-7 (4 Layers); max value at TA = 125 °C	149
Package thermal resistance junction to board	RθJB			13.8	°C/Watt	100 LQFP	149
Package thermal resistance junction to case	RθJC			4.4	°C/Watt	100 LQFP	149

CAD (KiCad official)

Symbol: CYT2BL5CAAQ0AZEGS
Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
3D model files: cyt2bl5caaq0azegs-etched.step / cyt2bl5caaq0azegs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cyt2bl5caaq0azegs.step / cyt2bl5caaq0azegs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Infineon Technologies datasheet (175 pp, sha256 cbbfe9ff4ec421ea, retrieved 2026-11-13, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CYT2BL5CAAQ0AZEGS

Verified CYT2BL5CAAQ0AZEGS

Verification log 1 record

CYT2BL5CAAQ0AZEGS

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance