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Infineon Technologies Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CYT2B73CADQ0AZSGS

Infineon Technologies · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

CYT2B73CADQ0AZSGS from Infineon Technologies, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P0.0	bidirectional	GPIO_ENH pin supporting a 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages, also carrying SCB0_RX, SCB7_SDA (2), SCB0_MISO and LIN1_RX.
2	P0.1	bidirectional	GPIO_ENH pin supporting a 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages, also carrying SCB0_TX, SCB7_SCL (2), SCB0_MOSI and LIN1_TX.
3	P0.2	bidirectional	GPIO_ENH pin supporting a 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages, also carrying SCB0_RTS, SCB0_SCL, SCB0_CLK, LIN1_EN and CAN0_1_TX.
4	P0.3	bidirectional	GPIO_ENH pin supporting a 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages, also carrying SCB0_CTS, SCB0_SDA, SCB0_SEL0 and CAN0_1_RX.
5	P2.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB7_RX (0), LIN0_RX, CAN0_0_TX, SWJ_TRSTN and TRIG_IN[2].
6	P2.1	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB7_TX (0), LIN0_TX, CAN0_0_RX and TRIG_IN[3].
7	P5.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying LIN7_RX, SCB5_SEL2 (0) and PWM0_9.
8	P5.1	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying LIN7_TX and PWM0_10.
9	P6.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_RX (0), LIN3_RX and ADC[0]_0.
10	P6.1	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_TX (0), LIN3_TX and ADC[0]_1.
11	P6.2	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_RTS (0), SCB4_SCL (0), SCB4_CLK (0), LIN3_EN, CAN0_2_TX and ADC[0]_2.
12	P6.3	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_CTS (0), LIN4_RX, CAN0_2_RX, CAL_SUP_NZ and ADC[0]_3.
13	P6.4	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_SEL1 (0), LIN4_TX and ADC[0]_4.
14	P6.5	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_SEL2 (0), LIN4_EN and ADC[0]_5.
15	P6.6	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_SEL3 (0), TRIG_IN[8] and ADC[0]_6.
16	VDDD	power_in	Main digital supply.
17	VSSD	power_in	Main digital ground.
18	P7.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB5_RX (1), LIN4_RX and ADC[0]_8.
19	P7.1	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB5_TX (1), LIN4_TX and ADC[0]_9.
20	P7.2	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB5_RTS (1), SCB5_SCL (1), SCB5_CLK (1), LIN4_EN and ADC[0]_10.
21	P8.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying LIN2_RX and CAN0_0_TX.
22	P8.1	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying LIN2_TX, CAN0_0_RX, TRIG_IN[14] and ADC[0]_16.
23	P11.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range with analog capability, also serving as ADC[0]_M motor control input for simultaneous ADC capture.
24	P11.1	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range with analog capability, also serving as ADC[1]_M motor control input for simultaneous ADC capture.
25	P11.2	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range with analog capability, also serving as ADC[2]_M motor control input for simultaneous ADC capture.
26	VREFL	power_in	Low reference voltage for SAR ADCs.
27	VSSA	power_in	Main analog ground.
28	VDDA	power_in	Main analog supply for SAR ADCs.
29	VREFH	power_in	High reference voltage for SAR ADCs.
30	P12.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying CAN0_2_TX, TRIG_IN[20], ADC[1]_4 and SMARTIO12_0.
31	P12.1	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying LIN6_EN, CAN0_2_RX, TRIG_IN[21], ADC[1]_5 and SMARTIO12_1.
32	VDDIO_2	power_in	I/O supply for analog I/Os other than those on VDDA, including port P11.
33	VSSD	power_in	Main digital ground.
34	P13.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying EXT_MUX[2]_0, SCB3_RX (0), ADC[1]_12 and SMARTIO13_0.
35	P13.1	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying EXT_MUX[2]_1, SCB3_TX (0), ADC[1]_13 and SMARTIO13_1.
36	P13.2	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying EXT_MUX[2]_2, SCB3_RTS (0), SCB3_SCL (0), ADC[1]_14 and SMARTIO13_2.
37	P13.3	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying EXT_MUX[2]_EN, SCB3_CTS (0), ADC[1]_15 and SMARTIO13_3.
38	P14.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB2_RX (0), CAN1_0_TX, ADC[1]_20 and SMARTIO14_0.
39	P14.1	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB2_TX (0), CAN1_0_RX, ADC[1]_21 and SMARTIO14_1.
40	P14.2	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB2_RTS (0), SCB2_SCL (0), LIN6_RX, ADC[1]_22 and SMARTIO14_2.
41	P18.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_RX (0), FAULT_OUT_0, ADC[2]_0 and PWM0_H_0.
42	P18.1	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_TX (0), FAULT_OUT_1, ADC[2]_1 and PWM0_H_0_N.
43	P18.3	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_CTS (0), TRACE_CLOCK (0), ADC[2]_3 and PWM0_H_1_N.
44	P18.4	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_SEL1 (0), TRACE_DATA_0 (0), ADC[2]_4 and PWM0_H_2.
45	P18.5	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_SEL2 (0), TRACE_DATA_1 (0), ADC[2]_5 and PWM0_H_2_N.
46	P18.6	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_SEL3 (0), CAN1_2_TX, TRACE_DATA_2 (0), ADC[2]_6 and PWM0_H_3.
47	P18.7	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying CAN1_2_RX, TRACE_DATA_3 (0), ADC[2]_7 and PWM0_H_3_N.
48	VDDD	power_in	Main digital supply.
49	VSSD	power_in	Main digital ground.
50	P21.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also serving as WCO_IN for the watch-crystal oscillator input and SCB1_SEL2 (1).
51	P21.1	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also serving as WCO_OUT for the watch-crystal oscillator output.
52	P21.2	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also serving as ECO_IN and EXT_CLK, with TRIG_DBG[1].
53	P21.3	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also serving as ECO_OUT for the external crystal oscillator output.
54	XRES_L	input	Active LOW external reset input.
55	VDDD	power_in	Main digital supply.
56	VSSD	power_in	Main digital ground.
57	VSSD	power_in	Main digital ground.
58	VCCD	passive	Main regulated supply driven by an LDO regulator (internal or external); VCCD pins must be connected together for a low-impedance connection.
59	P22.0	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB6_RX (1), CAN1_1_TX and TRACE_DATA_0 (1).
60	P23.3	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB7_CTS (1), SCB7_SEL0 (1), FAULT_OUT_3 and TRIG_IN[30].
61	P23.4	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SWJ_SWO_TDO, SCB7_SEL1 (1), TRIG_IN[31] and TRIG_DBG[0].
62	P23.5	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SWJ_SWCLK_TCLK and SCB7_SEL2 (1).
63	P23.6	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SWJ_SWDIO_TMS.
64	P23.7	bidirectional	GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SWJ_SWDOE_TDI, EXT_CLK, CAL_SUP_NZ and HIBERNATE_WAKEUP[1].

Key specifications

Parameter	Value
Manufacturer	Infineon Technologies
Package	LQFP-64(10x10)
Category	Single Chip Microcomputer/Microcontroller
Pins	64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Power supply voltage	VDDD, VDDA, VDDIO_1, VDDIO_2	2.7		5.5	V		90
Power supply voltage for eFuse programming	VDDIO_1_EFP	3		5.5	V		90
Smoothing capacitor	CS1	3.76		11	µF		90
Maximum clamp current	ICLAMP_ABS	-5		5	mA		88
Maximum positive clamp current per I/O supply pin	ICLAMP_SUPPLY_POS_ABS			10	mA		88
Maximum negative clamp current per I/O ground pin	ICLAMP_SUPPLY_NEG_ABS			10	mA		88
Maximum positive clamp current per I/O supply	ICLAMP_TOTAL_POS_ABS			50	mA		88
Maximum negative clamp current per I/O ground	ICLAMP_TOTAL_NEG_ABS			50	mA		88
LOW-level maximum output current GPIO_STD	IOL1A_ABS			6	mA	drive_sel<1:0>= 0b0X	88
LOW-level maximum output current GPIO_STD	IOL1B_ABS			2	mA	drive_sel<1:0>= 0b10	88
LOW-level maximum output current GPIO_STD	IOL1C_ABS			1	mA	drive_sel<1:0>= 0b11	88
LOW-level maximum output current GPIO_ENH	IOL2A_ABS			6	mA	drive_sel<1:0>= 0b0X	88
LOW-level maximum output current GPIO_ENH	IOL2B_ABS			2	mA	drive_sel<1:0>= 0b10	88
LOW-level maximum output current GPIO_ENH	IOL2C_ABS			1	mA	drive_sel<1:0>= 0b11	88
LOW-level total output current	ΣIOL_ABS_GPIO			50	mA		88
HIGH-level maximum output current GPIO_STD	IOH1A_ABS			-5	mA	drive_sel<1:0>= 0b0X	88
HIGH-level maximum output current GPIO_STD	IOH1B_ABS			-2	mA	drive_sel<1:0>= 0b10	88
HIGH-level maximum output current GPIO_STD	IOH1C_ABS			-1	mA	drive_sel<1:0>= 0b11	88
HIGH-level maximum output current GPIO_ENH	IOH2A_ABS			-5	mA	drive_sel<1:0>= 0b0X	88
HIGH-level maximum output current GPIO_ENH	IOH2B_ABS			-2	mA	drive_sel<1:0>= 0b10	88
HIGH-level maximum output current GPIO_ENH	IOH2C_ABS			-1	mA	drive_sel<1:0>= 0b11	88
HIGH-level total output current	ΣIOH_ABS_GPIO			-50	mA		88
Power dissipation	PD			1000	mW	TJ should not exceed 150 °C	88
Ambient temperature	TA	-40		105	°C	For S-grade devices	88
Storage temperature	TSTG	-55		150	°C		88
Operating junction temperature	TJ	-40		150	°C		88
ESD human body model	VESD_HBM	2000			V		88
ESD charged device model corner pins	VESD_CDM1	750			V		88
ESD charged device model all other pins	VESD_CDM2	500			V		88
Latch-up pin current	ILU	-100		100	mA		88
Package thermal resistance junction to ambient	RθJA			37.6	°C/Watt	64 LQFP	139
Package thermal resistance junction to board	RθJB			32	°C/Watt	64 LQFP	139
Package thermal resistance junction to case	RθJC			7.8	°C/Watt	64 LQFP	139
Operating ambient temperature	TA	-40		105	°C	S-grade	139
Operating junction temperature	TJ			150	°C		139
Internal band gap reference voltage	Vband_gap	0.882	0.9	0.918	V		103
VREFH voltage range	A_VREFH	2.7			V	ADC performance degrades when high reference is higher than supply	103
ADC VDDA voltage range	A_VDDA	2.7		5.5	V		103
ADC resolution	A_RES			12	bits		103
Zero transition voltage	VZT	-20		20	mV	VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C before offset adjustment	105
Full-scale transition voltage	VFST	-20		20	mV	VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C before offset adjustment	105
ADC operating frequency	fADC_4P5	2		26.67	MHz	4.5 V ≤ VDDA ≤ 5.5 V	105
ADC operating frequency	fADC_2P7	2		13.34	MHz	2.7 V ≤ VDDA < 4.5 V	105
Total error after offset and gain adjustment	A_TE	-5		5	LSb	VDDA = VREFH = 2.7 V to 5.5 V, VREFL = VSSA, -40 °C ≤ TA ≤ 125 °C	106
Total error before offset and gain adjustment	A_TEB	-12		12	LSb	VDDA = VREFH = 2.7 V to 5.5 V, VREFL = VSSA, -40 °C ≤ TA ≤ 125 °C	106
Integral nonlinearity	A_INL	-2.5		2.5	LSb	VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C	106
Differential nonlinearity	A_DNL	-0.99		1.9	LSb	VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C	106
Channel-to-channel variation	A_CE	-1		1	LSb	VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C	106
Analog input leakage current	IAIC	-350	70	350	nA	When input pad is selected for conversion	106
Analog power supply current while ADC is operating	IVDDA		360	550	µA	Per enabled ADC	106
Temperature sensor accuracy 1	TSENSACC1	-2		2	°C	TJ = 150 °C	107
Temperature sensor accuracy 2	TSENSACC2	-5		5	°C	-40 °C ≤ TJ < 150 °C	107
Temperature sensor accuracy 3	TSENSACC3	-10		10	°C	-40 °C ≤ TJ ≤ 150 °C	107
Uncorrected monitor voltage divider accuracy	VMONDIV	-20	2	20	%	Any HV supply pad within 2.7-V-5.5-V operating range	107
LP Active mode current (CM4 and CM0+ at 8 MHz, peripherals disabled)	IDD1_CM04_8_1A		4	9	mA	CM0+ and CM4 clocked at 8 MHz with IMO. All peripherals are disabled. No IO toggling.	91
Active mode current (CM4 at 160 MHz, CM0+ at 80 MHz)	IDD1_F160_1M		39	102	mA	PLL enabled at 160 MHz with ECO reference. All peripherals are enabled. No I/O toggling.	91
Sleep mode current	IDD2_8_1		3	46	mA	PLL disabled, CM4 and CM0+ sleeping at 8 MHz with IMO	91
Output frequency	fOUT_GPIO_ENH3H			15	MHz	6-pF load, drive_sel<1:0>= 0b11, 4.5 V ≤ VDDD ≤ 5.5 V	102
Minimum pulse width for GPIO interrupt	tINT	160			ns		102
Minimum MCWDT timeout	tMCWDT1	58.12			µs	When using the ILO (32.768 kHz + 5%) and 16-bit MCWDT counter	136

CAD (KiCad official)

Symbol: CYT2B73CADQ0AZSGS
Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
3D model files: cyt2b73cadq0azsgs-etched.step / cyt2b73cadq0azsgs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cyt2b73cadq0azsgs.step / cyt2b73cadq0azsgs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Infineon Technologies datasheet (164 pp, sha256 03e98bd0604b3676, retrieved 2026-11-13, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# CYT2B73CADQ0AZSGS

**Infineon Technologies** · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

CYT2B73CADQ0AZSGS from Infineon Technologies, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.0 | bidirectional | GPIO_ENH pin supporting a 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages, also carrying SCB0_RX, SCB7_SDA (2), SCB0_MISO and LIN1_RX. |
| 2 | P0.1 | bidirectional | GPIO_ENH pin supporting a 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages, also carrying SCB0_TX, SCB7_SCL (2), SCB0_MOSI and LIN1_TX. |
| 3 | P0.2 | bidirectional | GPIO_ENH pin supporting a 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages, also carrying SCB0_RTS, SCB0_SCL, SCB0_CLK, LIN1_EN and CAN0_1_TX. |
| 4 | P0.3 | bidirectional | GPIO_ENH pin supporting a 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages, also carrying SCB0_CTS, SCB0_SDA, SCB0_SEL0 and CAN0_1_RX. |
| 5 | P2.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB7_RX (0), LIN0_RX, CAN0_0_TX, SWJ_TRSTN and TRIG_IN[2]. |
| 6 | P2.1 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB7_TX (0), LIN0_TX, CAN0_0_RX and TRIG_IN[3]. |
| 7 | P5.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying LIN7_RX, SCB5_SEL2 (0) and PWM0_9. |
| 8 | P5.1 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying LIN7_TX and PWM0_10. |
| 9 | P6.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_RX (0), LIN3_RX and ADC[0]_0. |
| 10 | P6.1 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_TX (0), LIN3_TX and ADC[0]_1. |
| 11 | P6.2 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_RTS (0), SCB4_SCL (0), SCB4_CLK (0), LIN3_EN, CAN0_2_TX and ADC[0]_2. |
| 12 | P6.3 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_CTS (0), LIN4_RX, CAN0_2_RX, CAL_SUP_NZ and ADC[0]_3. |
| 13 | P6.4 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_SEL1 (0), LIN4_TX and ADC[0]_4. |
| 14 | P6.5 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_SEL2 (0), LIN4_EN and ADC[0]_5. |
| 15 | P6.6 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB4_SEL3 (0), TRIG_IN[8] and ADC[0]_6. |
| 16 | VDDD | power_in | Main digital supply. |
| 17 | VSSD | power_in | Main digital ground. |
| 18 | P7.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB5_RX (1), LIN4_RX and ADC[0]_8. |
| 19 | P7.1 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB5_TX (1), LIN4_TX and ADC[0]_9. |
| 20 | P7.2 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB5_RTS (1), SCB5_SCL (1), SCB5_CLK (1), LIN4_EN and ADC[0]_10. |
| 21 | P8.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying LIN2_RX and CAN0_0_TX. |
| 22 | P8.1 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying LIN2_TX, CAN0_0_RX, TRIG_IN[14] and ADC[0]_16. |
| 23 | P11.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range with analog capability, also serving as ADC[0]_M motor control input for simultaneous ADC capture. |
| 24 | P11.1 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range with analog capability, also serving as ADC[1]_M motor control input for simultaneous ADC capture. |
| 25 | P11.2 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range with analog capability, also serving as ADC[2]_M motor control input for simultaneous ADC capture. |
| 26 | VREFL | power_in | Low reference voltage for SAR ADCs. |
| 27 | VSSA | power_in | Main analog ground. |
| 28 | VDDA | power_in | Main analog supply for SAR ADCs. |
| 29 | VREFH | power_in | High reference voltage for SAR ADCs. |
| 30 | P12.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying CAN0_2_TX, TRIG_IN[20], ADC[1]_4 and SMARTIO12_0. |
| 31 | P12.1 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying LIN6_EN, CAN0_2_RX, TRIG_IN[21], ADC[1]_5 and SMARTIO12_1. |
| 32 | VDDIO_2 | power_in | I/O supply for analog I/Os other than those on VDDA, including port P11. |
| 33 | VSSD | power_in | Main digital ground. |
| 34 | P13.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying EXT_MUX[2]_0, SCB3_RX (0), ADC[1]_12 and SMARTIO13_0. |
| 35 | P13.1 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying EXT_MUX[2]_1, SCB3_TX (0), ADC[1]_13 and SMARTIO13_1. |
| 36 | P13.2 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying EXT_MUX[2]_2, SCB3_RTS (0), SCB3_SCL (0), ADC[1]_14 and SMARTIO13_2. |
| 37 | P13.3 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying EXT_MUX[2]_EN, SCB3_CTS (0), ADC[1]_15 and SMARTIO13_3. |
| 38 | P14.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB2_RX (0), CAN1_0_TX, ADC[1]_20 and SMARTIO14_0. |
| 39 | P14.1 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB2_TX (0), CAN1_0_RX, ADC[1]_21 and SMARTIO14_1. |
| 40 | P14.2 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB2_RTS (0), SCB2_SCL (0), LIN6_RX, ADC[1]_22 and SMARTIO14_2. |
| 41 | P18.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_RX (0), FAULT_OUT_0, ADC[2]_0 and PWM0_H_0. |
| 42 | P18.1 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_TX (0), FAULT_OUT_1, ADC[2]_1 and PWM0_H_0_N. |
| 43 | P18.3 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_CTS (0), TRACE_CLOCK (0), ADC[2]_3 and PWM0_H_1_N. |
| 44 | P18.4 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_SEL1 (0), TRACE_DATA_0 (0), ADC[2]_4 and PWM0_H_2. |
| 45 | P18.5 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_SEL2 (0), TRACE_DATA_1 (0), ADC[2]_5 and PWM0_H_2_N. |
| 46 | P18.6 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB1_SEL3 (0), CAN1_2_TX, TRACE_DATA_2 (0), ADC[2]_6 and PWM0_H_3. |
| 47 | P18.7 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying CAN1_2_RX, TRACE_DATA_3 (0), ADC[2]_7 and PWM0_H_3_N. |
| 48 | VDDD | power_in | Main digital supply. |
| 49 | VSSD | power_in | Main digital ground. |
| 50 | P21.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also serving as WCO_IN for the watch-crystal oscillator input and SCB1_SEL2 (1). |
| 51 | P21.1 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also serving as WCO_OUT for the watch-crystal oscillator output. |
| 52 | P21.2 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also serving as ECO_IN and EXT_CLK, with TRIG_DBG[1]. |
| 53 | P21.3 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also serving as ECO_OUT for the external crystal oscillator output. |
| 54 | XRES_L | input | Active LOW external reset input. |
| 55 | VDDD | power_in | Main digital supply. |
| 56 | VSSD | power_in | Main digital ground. |
| 57 | VSSD | power_in | Main digital ground. |
| 58 | VCCD | passive | Main regulated supply driven by an LDO regulator (internal or external); VCCD pins must be connected together for a low-impedance connection. |
| 59 | P22.0 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB6_RX (1), CAN1_1_TX and TRACE_DATA_0 (1). |
| 60 | P23.3 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SCB7_CTS (1), SCB7_SEL0 (1), FAULT_OUT_3 and TRIG_IN[30]. |
| 61 | P23.4 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SWJ_SWO_TDO, SCB7_SEL1 (1), TRIG_IN[31] and TRIG_DBG[0]. |
| 62 | P23.5 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SWJ_SWCLK_TCLK and SCB7_SEL2 (1). |
| 63 | P23.6 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SWJ_SWDIO_TMS. |
| 64 | P23.7 | bidirectional | GPIO_STD pin supporting a 2.7 V to 5.5 V VDDIO range, also carrying SWJ_SWDOE_TDI, EXT_CLK, CAL_SUP_NZ and HIBERNATE_WAKEUP[1]. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon Technologies |
| Package | LQFP-64(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage | VDDD, VDDA, VDDIO_1, VDDIO_2 | 2.7 |  | 5.5 | V |  | 90 |
| Power supply voltage for eFuse programming | VDDIO_1_EFP | 3 |  | 5.5 | V |  | 90 |
| Smoothing capacitor | CS1 | 3.76 |  | 11 | µF |  | 90 |
| Maximum clamp current | ICLAMP_ABS | -5 |  | 5 | mA |  | 88 |
| Maximum positive clamp current per I/O supply pin | ICLAMP_SUPPLY_POS_ABS |  |  | 10 | mA |  | 88 |
| Maximum negative clamp current per I/O ground pin | ICLAMP_SUPPLY_NEG_ABS |  |  | 10 | mA |  | 88 |
| Maximum positive clamp current per I/O supply | ICLAMP_TOTAL_POS_ABS |  |  | 50 | mA |  | 88 |
| Maximum negative clamp current per I/O ground | ICLAMP_TOTAL_NEG_ABS |  |  | 50 | mA |  | 88 |
| LOW-level maximum output current GPIO_STD | IOL1A_ABS |  |  | 6 | mA | drive_sel<1:0>= 0b0X | 88 |
| LOW-level maximum output current GPIO_STD | IOL1B_ABS |  |  | 2 | mA | drive_sel<1:0>= 0b10 | 88 |
| LOW-level maximum output current GPIO_STD | IOL1C_ABS |  |  | 1 | mA | drive_sel<1:0>= 0b11 | 88 |
| LOW-level maximum output current GPIO_ENH | IOL2A_ABS |  |  | 6 | mA | drive_sel<1:0>= 0b0X | 88 |
| LOW-level maximum output current GPIO_ENH | IOL2B_ABS |  |  | 2 | mA | drive_sel<1:0>= 0b10 | 88 |
| LOW-level maximum output current GPIO_ENH | IOL2C_ABS |  |  | 1 | mA | drive_sel<1:0>= 0b11 | 88 |
| LOW-level total output current | ΣIOL_ABS_GPIO |  |  | 50 | mA |  | 88 |
| HIGH-level maximum output current GPIO_STD | IOH1A_ABS |  |  | -5 | mA | drive_sel<1:0>= 0b0X | 88 |
| HIGH-level maximum output current GPIO_STD | IOH1B_ABS |  |  | -2 | mA | drive_sel<1:0>= 0b10 | 88 |
| HIGH-level maximum output current GPIO_STD | IOH1C_ABS |  |  | -1 | mA | drive_sel<1:0>= 0b11 | 88 |
| HIGH-level maximum output current GPIO_ENH | IOH2A_ABS |  |  | -5 | mA | drive_sel<1:0>= 0b0X | 88 |
| HIGH-level maximum output current GPIO_ENH | IOH2B_ABS |  |  | -2 | mA | drive_sel<1:0>= 0b10 | 88 |
| HIGH-level maximum output current GPIO_ENH | IOH2C_ABS |  |  | -1 | mA | drive_sel<1:0>= 0b11 | 88 |
| HIGH-level total output current | ΣIOH_ABS_GPIO |  |  | -50 | mA |  | 88 |
| Power dissipation | PD |  |  | 1000 | mW | TJ should not exceed 150 °C | 88 |
| Ambient temperature | TA | -40 |  | 105 | °C | For S-grade devices | 88 |
| Storage temperature | TSTG | -55 |  | 150 | °C |  | 88 |
| Operating junction temperature | TJ | -40 |  | 150 | °C |  | 88 |
| ESD human body model | VESD_HBM | 2000 |  |  | V |  | 88 |
| ESD charged device model corner pins | VESD_CDM1 | 750 |  |  | V |  | 88 |
| ESD charged device model all other pins | VESD_CDM2 | 500 |  |  | V |  | 88 |
| Latch-up pin current | ILU | -100 |  | 100 | mA |  | 88 |
| Package thermal resistance junction to ambient | RθJA |  |  | 37.6 | °C/Watt | 64 LQFP | 139 |
| Package thermal resistance junction to board | RθJB |  |  | 32 | °C/Watt | 64 LQFP | 139 |
| Package thermal resistance junction to case | RθJC |  |  | 7.8 | °C/Watt | 64 LQFP | 139 |
| Operating ambient temperature | TA | -40 |  | 105 | °C | S-grade | 139 |
| Operating junction temperature | TJ |  |  | 150 | °C |  | 139 |
| Internal band gap reference voltage | Vband_gap | 0.882 | 0.9 | 0.918 | V |  | 103 |
| VREFH voltage range | A_VREFH | 2.7 |  |  | V | ADC performance degrades when high reference is higher than supply | 103 |
| ADC VDDA voltage range | A_VDDA | 2.7 |  | 5.5 | V |  | 103 |
| ADC resolution | A_RES |  |  | 12 | bits |  | 103 |
| Zero transition voltage | VZT | -20 |  | 20 | mV | VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C before offset adjustment | 105 |
| Full-scale transition voltage | VFST | -20 |  | 20 | mV | VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C before offset adjustment | 105 |
| ADC operating frequency | fADC_4P5 | 2 |  | 26.67 | MHz | 4.5 V ≤ VDDA ≤ 5.5 V | 105 |
| ADC operating frequency | fADC_2P7 | 2 |  | 13.34 | MHz | 2.7 V ≤ VDDA < 4.5 V | 105 |
| Total error after offset and gain adjustment | A_TE | -5 |  | 5 | LSb | VDDA = VREFH = 2.7 V to 5.5 V, VREFL = VSSA, -40 °C ≤ TA ≤ 125 °C | 106 |
| Total error before offset and gain adjustment | A_TEB | -12 |  | 12 | LSb | VDDA = VREFH = 2.7 V to 5.5 V, VREFL = VSSA, -40 °C ≤ TA ≤ 125 °C | 106 |
| Integral nonlinearity | A_INL | -2.5 |  | 2.5 | LSb | VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C | 106 |
| Differential nonlinearity | A_DNL | -0.99 |  | 1.9 | LSb | VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C | 106 |
| Channel-to-channel variation | A_CE | -1 |  | 1 | LSb | VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C | 106 |
| Analog input leakage current | IAIC | -350 | 70 | 350 | nA | When input pad is selected for conversion | 106 |
| Analog power supply current while ADC is operating | IVDDA |  | 360 | 550 | µA | Per enabled ADC | 106 |
| Temperature sensor accuracy 1 | TSENSACC1 | -2 |  | 2 | °C | TJ = 150 °C | 107 |
| Temperature sensor accuracy 2 | TSENSACC2 | -5 |  | 5 | °C | -40 °C ≤ TJ < 150 °C | 107 |
| Temperature sensor accuracy 3 | TSENSACC3 | -10 |  | 10 | °C | -40 °C ≤ TJ ≤ 150 °C | 107 |
| Uncorrected monitor voltage divider accuracy | VMONDIV | -20 | 2 | 20 | % | Any HV supply pad within 2.7-V-5.5-V operating range | 107 |
| LP Active mode current (CM4 and CM0+ at 8 MHz, peripherals disabled) | IDD1_CM04_8_1A |  | 4 | 9 | mA | CM0+ and CM4 clocked at 8 MHz with IMO. All peripherals are disabled. No IO toggling. | 91 |
| Active mode current (CM4 at 160 MHz, CM0+ at 80 MHz) | IDD1_F160_1M |  | 39 | 102 | mA | PLL enabled at 160 MHz with ECO reference. All peripherals are enabled. No I/O toggling. | 91 |
| Sleep mode current | IDD2_8_1 |  | 3 | 46 | mA | PLL disabled, CM4 and CM0+ sleeping at 8 MHz with IMO | 91 |
| Output frequency | fOUT_GPIO_ENH3H |  |  | 15 | MHz | 6-pF load, drive_sel<1:0>= 0b11, 4.5 V ≤ VDDD ≤ 5.5 V | 102 |
| Minimum pulse width for GPIO interrupt | tINT | 160 |  |  | ns |  | 102 |
| Minimum MCWDT timeout | tMCWDT1 | 58.12 |  |  | µs | When using the ILO (32.768 kHz + 5%) and 16-bit MCWDT counter | 136 |

## CAD (KiCad official)

- Symbol: `CYT2B73CADQ0AZSGS`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `cyt2b73cadq0azsgs-etched.step` / `cyt2b73cadq0azsgs-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cyt2b73cadq0azsgs.step` / `cyt2b73cadq0azsgs.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon Technologies datasheet](docs/cyt2b73cadq0azsgs-datasheet.pdf) (164 pp, sha256 `03e98bd0604b3676`, retrieved 2026-11-13, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cyt2b73cadq0azsgs-datasheet.pdf)

CYT2B73CADQ0AZSGS

Verified CYT2B73CADQ0AZSGS

Verification log 1 record

CYT2B73CADQ0AZSGS

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance