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CYT2B65BADQ0AZSGS

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Infineon Technologies Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercyt2b65badq0azsgsfactory-2.0.0extractor-text

Verified CYT2B65BADQ0AZSGS

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier mfr, 100 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CYT2B65BADQ0AZSGS · LQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 166-page datasheet
  • ✓distributor: lcsc C6520240, digikey 448-CYT2B65BADQ0AZSGS-ND, mouser 727-YT2B65BADQ0AZSGS
  • ✓family: LQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ng1qml3u/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.143)
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 108 kB, viewers/symbol.html 61 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cyt2b65badq0azsgs.kicad_sym✓ cyt2b65badq0azsgs.kicad_mod✓ cyt2b65badq0azsgs.step
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cyt2b65badq0azsgs-etched.step cyt2b65badq0azsgs: factory component page (tier=mfr) · Ray
cyt2b65badq0azsgs-hero.glb cyt2b65badq0azsgs: hero GLB from the etched model (keeps the MPN mark) · Ray
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verification.json Verified: Published by the parts factory: tier mfr, 100 pins · Ray

CYT2B65BADQ0AZSGS

Infineon Technologies · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

CYT2B65BADQ0AZSGS from Infineon Technologies, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSSD power_in Main digital ground.
2 P0.0 bidirectional GPIO_ENH port pin (2.7 V to 5.5 V VDDIO, higher current at lower VDDIO); alternates include SCB0_RX/SCB0_MISO, SCB7_SDA, LIN1_RX and PWM_18.
3 P0.1 bidirectional GPIO_ENH port pin (2.7 V to 5.5 V VDDIO, higher current at lower VDDIO); alternates include SCB0_TX/SCB0_MOSI, SCB7_SCL, LIN1_TX and PWM_17.
4 P0.2 bidirectional GPIO_ENH port pin (2.7 V to 5.5 V VDDIO, higher current at lower VDDIO); alternates include SCB0_RTS/SCB0_SCL/SCB0_CLK, LIN1_EN and CAN0_1_TX.
5 P0.3 bidirectional GPIO_ENH port pin (2.7 V to 5.5 V VDDIO, higher current at lower VDDIO); alternates include SCB0_CTS/SCB0_SDA/SCB0_SEL0, CAN0_1_RX and PWM_13.
6 P2.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include SWJ_TRSTN, SCB7_RX/SCB7_MISO, SCB0_SEL1, LIN0_RX, CAN0_0_TX and TRIG_IN[2].
7 P2.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include SCB7_TX/SCB7_MOSI, SCB7_SDA (0), SCB0_SEL2, LIN0_TX, CAN0_0_RX and TRIG_IN[3].
8 P2.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include SCB7_RTS/SCB7_CLK, SCB7_SCL (0), SCB0_SEL3, LIN0_EN and TRIG_IN[4].
9 P2.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include SCB7_CTS/SCB7_SEL0, PWM_4 and TRIG_IN[5].
10 P3.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_1, TC_1_TR0 and TRIG_DBG[0].
11 P3.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_0, PWM_1_N, TC_0_TR0, TC_1_TR1 and TRIG_DBG[1].
12 VDDD power_in Main digital supply.
13 VSSD power_in Main digital ground.
14 P5.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_9 and TC_9_TR0.
15 P5.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_10, PWM_9_N, TC_10_TR0 and TC_9_TR1.
16 P5.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_11, PWM_10_N, TC_11_TR0 and TC_10_TR1.
17 P5.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_12, PWM_11_N, TC_12_TR0 and TC_11_TR1.
18 P6.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_M_0, SCB4_RX/SCB4_MISO, LIN3_RX and ADC[0]_0.
19 P6.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_0, SCB4_TX/SCB4_SDA/SCB4_MOSI, LIN3_TX and ADC[0]_1.
20 P6.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_M_1, SCB4_RTS/SCB4_SCL/SCB4_CLK, LIN3_EN and ADC[0]_2.
21 P6.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_1, SCB4_CTS/SCB4_SEL0, LIN4_RX, CAL_SUP_NZ and ADC[0]_3.
22 P6.4 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_M_2, SCB4_SEL1, LIN4_TX and ADC[0]_4.
23 P6.5 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_2, SCB4_SEL2, LIN4_EN and ADC[0]_5.
24 VDDD power_in Main digital supply.
25 VDDIO_1 power_in I/O supply for analog I/Os (except analog I/Os on VDDA).
26 VSSD power_in Main digital ground.
27 VSSD power_in Main digital ground.
28 VCCD power_out Main regulated supply driven by the LDO regulator; VCCD pins must be connected together for a low-impedance connection.
29 P7.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_M_4, SCB5_RX/SCB5_MISO, LIN4_RX and ADC[0]_8.
30 P7.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_15, SCB5_TX/SCB5_SDA/SCB5_MOSI, LIN4_TX and ADC[0]_9.
31 P7.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_15_N, SCB5_RTS/SCB5_SCL/SCB5_CLK and LIN4_EN.
32 P7.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_16, SCB5_CTS/SCB5_SEL0 and ADC[0]_11.
33 P7.4 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_16_N, SCB5_SEL1 and ADC[0]_12.
34 P7.5 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_17 and SCB5_SEL2.
35 P8.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_19, LIN2_RX and CAN0_0_TX.
36 P8.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_20, PWM_19_N, LIN2_TX, CAN0_0_RX and TRIG_IN[14].
37 P8.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_21, PWM_20_N, LIN2_EN, TRIG_IN[15] and ADC[0]_17.
38 P11.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO) on Port 11, which can pass full-level analog signals to the SAR without clipping to VDDD; ADC[0]_M is the highest-priority capture input.
39 P11.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO) on Port 11, which can pass full-level analog signals to the SAR without clipping to VDDD; ADC[1]_M is the highest-priority capture input.
40 P11.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO) on Port 11, which can pass full-level analog signals to the SAR without clipping to VDDD; ADC[2]_M is the highest-priority capture input.
41 VREFL power_in Low reference voltage for the SAR ADCs.
42 VSSA power_in Main analog ground.
43 VDDA power_in Main analog supply for the SAR ADCs.
44 VREFH power_in High reference voltage for the SAR ADCs.
45 P12.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_36, TC_36_TR0, TRIG_IN[20], ADC[1]_4 and SMARTIO12_0.
46 P12.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_37, TRIG_IN[21], ADC[1]_5 and SMARTIO12_1.
47 P12.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_38, EXT_MUX[1]_EN, ADC[1]_6 and SMARTIO12_2.
48 P12.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_39, EXT_MUX[1]_0, ADC[1]_7 and SMARTIO12_3.
49 P12.4 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_40, EXT_MUX[1]_1, ADC[1]_8 and SMARTIO12_4.
50 VDDIO_2 power_in I/O supply for analog I/Os (except analog I/Os on VDDA), including Port 11.
51 VSSD power_in Main digital ground.
52 P13.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include EXT_MUX[2]_0, SCB3_RX/SCB3_MISO, ADC[1]_12 and SMARTIO13_0.
53 P13.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_44, EXT_MUX[2]_1, SCB3_TX/SCB3_SDA/SCB3_MOSI, ADC[1]_13 and SMARTIO13_1.
54 P13.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_44_N, EXT_MUX[2]_2, SCB3_RTS/SCB3_SCL/SCB3_CLK, ADC[1]_14 and SMARTIO13_2.
55 P13.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_45, EXT_MUX[2]_EN, SCB3_CTS/SCB3_SEL0, ADC[1]_15 and SMARTIO13_3.
56 P13.4 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_45_N, SCB3_SEL1, ADC[1]_16 and SMARTIO13_4.
57 P13.5 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_46, SCB3_SEL2, ADC[1]_17 and SMARTIO13_5.
58 P13.6 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_46_N, SCB3_SEL3, TRIG_IN[22] and SMARTIO13_6.
59 P13.7 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_47, TRIG_IN[23] and SMARTIO13_7.
60 P14.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_48, PWM_47_N, CAN1_0_TX and SMARTIO14_0.
61 P14.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_49, PWM_48_N, CAN1_0_RX and SMARTIO14_1.
62 P14.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_50, PWM_49_N, ADC[1]_22 and SMARTIO14_2.
63 P14.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_51, PWM_50_N and ADC[1]_23.
64 P17.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternate CAN1_1_TX.
65 P17.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_H_2 and CAN1_1_RX.
66 P17.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternate PWM_H_2_N.
67 P18.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_H_0, SCB1_RX/SCB1_MISO, FAULT_OUT_0 and ADC[2]_0.
68 P18.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_H_0_N, SCB1_TX/SCB1_SDA/SCB1_MOSI, FAULT_OUT_1 and ADC[2]_1.
69 P18.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_55, SCB1_RTS/SCB1_SCL/SCB1_CLK and ADC[2]_2.
70 P18.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_54, PWM_55_N, SCB1_CTS/SCB1_SEL0, TRACE_CLOCK and ADC[2]_3.
71 P18.4 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_53, PWM_H_2, SCB1_SEL1, TRACE_DATA_0 and ADC[2]_4.
72 P18.5 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_52, PWM_H_2_N, SCB1_SEL2, TRACE_DATA_1 and ADC[2]_5.
73 P18.6 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_51, SCB1_SEL3, TRACE_DATA_2 and ADC[2]_6.
74 P18.7 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_50, TRACE_DATA_3 and ADC[2]_7.
75 VDDD power_in Main digital supply.
76 VSSD power_in Main digital ground.
77 P19.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_50_N, TC_50_TR1, TC_H_0_TR0 and FAULT_OUT_2.
78 P19.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_26, TC_26_TR0, TC_H_0_TR1 and FAULT_OUT_3.
79 P19.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_26_N, TC_26_TR1 and TRIG_IN[28].
80 P19.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternate TRIG_IN[29].
81 P21.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO) used as WCO_IN; must be configured high-impedance when the watch crystal oscillator is enabled.
82 P21.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO) used as WCO_OUT; must be configured high-impedance when the watch crystal oscillator is enabled.
83 P21.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO) used as ECO_IN; must be configured high-impedance when the external crystal oscillator is enabled.
84 P21.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO) used as ECO_OUT; must be configured high-impedance when the external crystal oscillator is enabled.
85 XRES_L input Active-low external reset input.
86 VDDD power_in Main digital supply.
87 VSSD power_in Main digital ground.
88 VSSD power_in Main digital ground.
89 VCCD power_out Main regulated supply driven by the LDO regulator; VCCD pins must be connected together for a low-impedance connection.
90 P21.5 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_37 and TC_37_TR0.
91 P22.0 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_34, TC_34_TR0 and CAN1_1_TX.
92 P22.1 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_33, PWM_34_N, TC_33_TR0, TC_34_TR1 and CAN1_1_RX.
93 P22.2 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_33_N and TC_33_TR1.
94 P22.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO) with no alternate function listed in the pin table.
95 P23.3 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include FAULT_OUT_3 and TRIG_IN[30].
96 P23.4 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_25, TC_25_TR0, TRIG_DBG[0], SWJ_SWO_TDO and TRIG_IN[31].
97 P23.5 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_24, PWM_25_N, TC_24_TR0, TC_25_TR1 and SWJ_SWCLK_TCLK.
98 P23.6 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_23, PWM_24_N, TC_23_TR0, TC_24_TR1 and SWJ_SWDIO_TMS.
99 P23.7 bidirectional GPIO_STD port pin (2.7 V to 5.5 V VDDIO); alternates include PWM_22, PWM_23_N, TC_22_TR0, TC_23_TR1, CAL_SUP_NZ, SWJ_SWDOE_TDI, EXT_CLK and HIBERNATE_WAKEUP[1].
100 VDDD power_in Main digital supply.

Key specifications

Parameter Value
Manufacturer Infineon Technologies
Package LQFP-100(14x14)
Category Single Chip Microcomputer/Microcontroller
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage (VDDD, VDDA, VDDIO_1, VDDIO_2) VDDD, VDDA, VDDIO_1, VDDIO_2 2.7 5.5 V 87
Power supply voltage for eFuse programming VDDIO_1_EFP 3 5.5 V 87
Smoothing capacitor CS1 3.76 11 µF Required per chip, not per VCCD pin 87
VDDD power supply voltage VDDD_ABS_5 -0.3 6 V Ports 0,2,3,5,17,18,19,21,22,23; min VSSD, 0.3 V, max VSSD + 6.0 V 84
VDDA analog power supply voltage VDDA_ABS -0.3 6 V VDDIO_2 = VDDA; min VSSA, 0.3 V, max VSSA + 6.0 V 84
Analog reference voltage, HIGH VREFH_ABS -0.3 6 V VREFH ≤ VDDA + 0.3 V; min VSSA, 0.3 V, max VSSA + 6.0 V 84
Analog reference voltage, LOW VREFL_ABS -0.3 0.3 V Limits printed as VSSA ± 0.3 V 84
Input voltage (ports 0,2,3,5,17,18,19,21,22,23) VI0_ABS0_5 -0.5 0.5 V Limits printed as VSSD, 0.5 V / VDDD + 0.5 V 84
Analog input voltage VIA_ABS -0.3 0.3 V Limits printed as VSSA, 0.3 V / VDDA + 0.3 V 84
Output voltage (ports 0,2,3,5,17,18,19,21,22,23) VO0_ABS0_5 -0.3 0.3 V Limits printed as VSSD, 0.3 V / VDDD + 0.3 V 84
Maximum clamp current ICLAMP_ABS -5 5 mA 84
Maximum positive clamp current per I/O supply, if not limited by per-pin limit ICLAMP_TOTAL_POS_ABS 50 mA Per I/O supply, if not limited by the per supply pin limit (SID18A) 84
Maximum negative clamp current per I/O ground, if not limited by per-pin limit ICLAMP_TOTAL_NEG_ABS 50 mA Per I/O ground, if not limited by the per ground pin limit (SID18B) 84
LOW-level maximum output current (GPIO_STD) IOL1A_ABS 6 mA GPIO_STD, drive_sel<1:0> = 0b0X 84
LOW-level maximum output current (GPIO_STD) IOL1B_ABS 2 mA GPIO_STD, drive_sel<1:0> = 0b10 84
LOW-level maximum output current (GPIO_STD) IOL1C_ABS 1 mA GPIO_STD, drive_sel<1:0> = 0b11 84
LOW-level maximum output current (GPIO_ENH) IOL2A_ABS 6 mA GPIO_ENH, drive_sel<1:0> = 0b0X 84
LOW-level total output current ∑IOL_ABS_GPIO 50 mA Total through all GPIO_STD and GPIO_ENH I/Os 85
HIGH-level maximum output current (GPIO_STD) IOH1A_ABS -5 mA GPIO_STD, drive_sel<1:0> = 0b0X 85
HIGH-level maximum output current (GPIO_STD) IOH1B_ABS -2 mA GPIO_STD, drive_sel<1:0> = 0b10 85
HIGH-level maximum output current (GPIO_STD) IOH1C_ABS -1 mA GPIO_STD, drive_sel<1:0> = 0b11 85
HIGH-level maximum output current (GPIO_ENH) IOH2A_ABS -5 mA GPIO_ENH, drive_sel<1:0> = 0b0X 85
HIGH-level total output current ∑IOH_ABS_GPIO -50 mA Total through all GPIO_STD and GPIO_ENH I/Os 85
Power dissipation PD 1000 mW TJ should not exceed 150 °C 85
Ambient temperature (S-grade) TA -40 105 °C For S-grade devices 85
Storage temperature TSTG -55 150 °C 85
Operating junction temperature TJ -40 150 °C 85
Electrostatic discharge human body model VESD_HBM 2000 V Human body model 85
Electrostatic discharge charged device model, corner pins VESD_CDM1 750 V Corner pins 85
Electrostatic discharge charged device model, all other pins VESD_CDM2 500 V All other pins 85
Maximum pin current before latch-up ILU -100 100 mA 85
LP Active mode current (CM4 and CM0+ at 8 MHz, peripherals disabled) IDD1_CM04_8_1A 4 9 mA CM0+ and CM4 at 8 MHz IMO, all peripherals disabled, no IO toggling; MAX at TA 25 °C, VDDD 5.5 V, FF 88
LP Active mode current (CM4 and CM0+ at 8 MHz, peripherals enabled) IDD1_CM04_8B 5 49 mA All peripherals enabled, no IO toggling, M-DMA and P-DMA active; MAX at TA 125 °C, VDDD 5.5 V, FF 88
Active mode current (CM4 and CM0+ at 80 MHz, all peripherals enabled) IDD1_F80_512 29 85 mA PLL at 80 MHz with ECO reference, all peripherals enabled, no IO toggling; MAX at TA 125 °C, VDDD 5.5 V, FF 88
All CPUs in Sleep mode current IDD2_8_1 3 46 mA PLL disabled, CM4 and CM0+ sleeping at 8 MHz IMO, peripherals/DMA/CSV/FLL/ECO disabled; MAX at TA 125 °C, VDDD 5.5 V, FF 88
Thermal resistance, junction to ambient (100-LQFP) RθJA 29.8 °C/Watt 100 LQFP; JESD51-7 4-layer board; max value for TA = 125 °C 142
Thermal resistance, junction to board (100-LQFP) RθJB 21.3 °C/Watt 100 LQFP 142
Thermal resistance, junction to case (100-LQFP) RθJC 5.6 °C/Watt 100 LQFP 142
SAR ADC resolution A_RES 12 bits 100
VREFH voltage range (max printed as VDDA) A_VREFH 2.7 V Max printed as VDDA; ADC performance degrades when high reference is higher than supply 100
VDDA voltage range for ADC A_VDDA 2.7 5.5 V 100
Internal band gap reference voltage Vband_gap 0.882 0.9 0.918 V 100
Internal pin resistance to current collection point RCLAMP_INTERNAL 50 Ω 100
Zero transition voltage VZT -20 20 mV VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C, before offset adjustment 102
Full-scale transition voltage VFST -20 20 mV VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C, before offset adjustment 102
ADC operating frequency fADC_4P5 2 26.67 MHz 4.5 V ≤ VDDA ≤ 5.5 V 102
ADC operating frequency fADC_2P7 2 13.34 MHz 2.7 V ≤ VDDA < 4.5 V 102
Analog input sample time for channels of own SARMUX tS_4P5 412 ns 4.5 V ≤ VDDA ≤ 5.5 V; guaranteed by design 102
Analog input sample time for channels of own SARMUX tS_2P7 600 ns 2.7 V ≤ VDDA < 4.5 V; guaranteed by design 102
Total error A_TEB -12 12 LSb VDDA = VREFH = 2.7 V to 5.5 V, VREFL = VSSA, -40 °C ≤ TA ≤ 125 °C; before offset and gain adjustment, 12-bit 104
Integral nonlinearity A_INL -2.5 2.5 LSb VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C 104
Differential nonlinearity A_DNL -0.99 1.9 LSb VDDA = 2.7 V to 5.5 V, -40 °C ≤ TA ≤ 125 °C 104
Analog power supply current while ADC is operating IVDDA 360 550 µA Per enabled ADC 104
Maximum operating frequency of GPIO_ENH output (3L drive) fOUT_GPIO_ENH3L 10 MHz 6-pF load, drive_sel<1:0> = 0b11, 2.7 V ≤ VDDD < 4.5 V 99
Analog glitch filter pulse suppression width tFT 50 ns One filter per port group 99
Minimum pulse width for GPIO interrupt tINT 160 ns 99
Temperature sensor accuracy 2 TSENSACC2 -5 5 °C -40 °C ≤ TJ ≤ 150 °C; valid with ADC[0], ADC[1] or ADC[2] under printed supply/reference conditions 105
Temperature sensor accuracy 3 TSENSACC3 -10 10 °C -40 °C ≤ TJ ≤ 150 °C; valid with ADC[0] or ADC[2] under printed supply conditions 105
Uncorrected monitor voltage divider accuracy VMONDIV -20 2 20 % Any HV supply pad within 2.7 V-5.5 V operating range; compared to ideal supply/2 105
Minimum WDT timeout tWDT1 58.12 µs ILO at 32.768 kHz + 5%, 32-bit WDT counter; guaranteed by design 139
Maximum WDT timeout tWDT2 38.33 h ILO at 32.768 kHz, 5%, 32-bit WDT counter; guaranteed by design 139

CAD (KiCad official)

  • Symbol: CYT2B65BADQ0AZSGS
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: cyt2b65badq0azsgs-etched.step / cyt2b65badq0azsgs-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cyt2b65badq0azsgs.step / cyt2b65badq0azsgs.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Technologies datasheet (166 pp, sha256 86323d02acede4a1, retrieved 2026-11-13, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF