component

CYPD6127-48LQXIT

Public Made by Adom

by adom

Infineon/Cypress Semicon Telecom Interface ICs, QFN-48(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterfacecypd6127-48lqxitfactory-2.0.0extractor-text

Changed since verified CYPD6127-48LQXIT

by Ray · last 31 Oct 2026 · 1 record · files changed since
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 49 pinschanged since
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CYPD6127-48LQXIT · QFN-48(6x6) · 49 pins
  • ✓copper: 49 copper pads, none touching another net
  • ✓datasheet: all 49 pin names found in the 59-page datasheet
  • ✓distributor: lcsc C5439678, digikey 448-CYPD6127-48LQXITTR-ND, mouser 727-CYPD6127-48LQXIT
  • ✓family: QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-ertr5bi8/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 49 pins = 49 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 49 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files! cypd6127-48lqxit.kicad_sym✓ cypd6127-48lqxit.kicad_mod✓ cypd6127-48lqxit.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cypd6127-48lqxit: symbol repaired (body fitted to the names) · Ray
cypd6127-48lqxit-etched.glb Publish 0.1.0 · Ray
cypd6127-48lqxit-etched.step cypd6127-48lqxit: factory component page (tier=mfr) · Ray
cypd6127-48lqxit-hero.glb cypd6127-48lqxit: hero GLB from the etched model (keeps the MPN mark) · Ray
cypd6127-48lqxit-hero.overlay.json Publish 0.1.0 · Ray
cypd6127-48lqxit.glb Publish 0.1.0 · Ray
cypd6127-48lqxit.kicad_mod Publish 0.1.0 · Ray
cypd6127-48lqxit.kicad_sym cypd6127-48lqxit: symbol repaired (body fitted to the names) · Ray
cypd6127-48lqxit.lbr cypd6127-48lqxit: symbol repaired (body fitted to the names) · Ray
cypd6127-48lqxit.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 49 pins · Ray

CYPD6127-48LQXIT

Infineon/Cypress Semicon · Telecom Interface ICs · QFN-48(6x6)

CYPD6127-48LQXIT from Infineon/Cypress Semicon, in a QFN-48(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBUS_C power_in Type-C VBUS connector input, 4-V to 21.5-V.
2 VBUS_C power_in Type-C VBUS connector input, 4-V to 21.5-V.
3 VBUS_C power_in Type-C VBUS connector input, 4-V to 21.5-V.
4 VBUS_P power_in VBUS provider input, 4-V to 5.5-V.
5 VBUS_P power_in VBUS provider input, 4-V to 5.5-V.
6 VBUS_P power_in VBUS provider input, 4-V to 5.5-V.
7 VBUS_P power_in VBUS provider input, 4-V to 5.5-V.
8 VSYS power_in 2.75-V to 5.5-V supply for the system.
9 VCCD power_out 1.8-V regulator output for filter capacitor; this pin cannot drive an external load.
10 VDDIO power_in I/O supply; at system level short VDDD to VDDIO.
11 VDDD power_out VDDD supply output; VSYS powered (min VSYS-50 mV) 2.7 to 5.5 V, VBUS powered 3.0 V to 3.6 V.
12 P3.3 bidirectional General-purpose I/O (P3.3).
13 I2C_SCL_SCB1/P0.3 bidirectional SCB1 clock or GPIO.
14 SWD_IO/P1.1 bidirectional Serial wire debug I/O or GPIO.
15 SWD_CLK/P1.0 bidirectional Serial wire debug clock or GPIO.
16 I2C_SDA_SCB1/P0.2 bidirectional SCB1 data or GPIO.
17 I2C_INT_TBT/P0.4 bidirectional Thunderbolt interrupt or GPIO.
18 DP_TOP bidirectional USB 2.0 DP from top of Type-C connector.
19 DM_TOP bidirectional USB 2.0 DM from top of Type-C connector.
20 DP_BOT bidirectional USB 2.0 DP from bottom of Type-C connector.
21 DM_BOT bidirectional USB 2.0 DM from bottom of Type-C connector.
22 DM_SYS bidirectional USB 2.0 DM from the host system.
23 DP_SYS bidirectional USB 2.0 DP from the host system.
24 UART_TX/P1.4 bidirectional UART Tx from host system or GPIO.
25 UART_RX/P1.3 bidirectional UART Rx from host system or GPIO.
26 I2C_INT_EC/P1.2 bidirectional Embedded controller interrupt or GPIO.
27 HPD/P2.0 bidirectional Hot plug detect I/O or GPIO.
28 I2C_SDA_SCB2/P2.1 bidirectional SCB2 data or GPIO.
29 I2C_SCL_SCB2/P2.2 bidirectional SCB2 clock or GPIO.
30 P2.3 bidirectional General-purpose I/O (P2.3).
31 P2.4 bidirectional General-purpose I/O (P2.4).
32 I2C_SCL_SCB0/P4.0 bidirectional SCB0 clock or GPIO.
33 I2C_SDA_SCB0/P4.1 bidirectional SCB0 data or GPIO.
34 XRES input Reset input.
35 P3.0 bidirectional General-purpose I/O (P3.0).
36 I2C_SDA_SCB3/P3.1 bidirectional SCB3 data or GPIO.
37 I2C_SCL_SCB3/P3.2 bidirectional SCB3 clock or GPIO.
38 CSN input Current sense negative input for the other side of the external Rsense.
39 CSP input Current sense positive input for the VBUS side of the external Rsense.
40 SBU2_SYS bidirectional Type-C sideband use signal, system side.
41 SBU1_SYS bidirectional Type-C sideband use signal, system side.
42 SBU1 bidirectional Type-C sideband use signal, connector side.
43 SBU2 bidirectional Type-C sideband use signal, connector side.
44 CC2 bidirectional USB PD connector detect/configuration channel 2.
45 V5V power_in 4.85-V to 5.5-V supply for the VCONN FET of Type-C.
46 CC1 bidirectional USB PD connector detect/configuration channel 1.
47 VBUS_C_CTRL output Full rail control I/O for enabling/disabling the consumer load NFET of USB Type-C.
48 VBUS_C power_in Type-C VBUS connector input, 4-V to 21.5-V.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Infineon/Cypress Semicon
Package QFN-48(6x6)
Category Interface
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VSYS maximum VSYS_MAX 6 V Supply relative to VSS 34
Max supply voltage V5V V5V_MAX 6 V Relative to VSS 34
VBUS voltage VBUS_C -0.3 24 V VBUS voltage relative to Vss 34
GPIO input voltage VGPIO_ABS -0.5 V Inputs to GPIO, DP/DM mux, SBU mux; max is VDDIO + 0.5 34
Maximum current per GPIO IGPIO_ABS -25 25 mA 34
GPIO injection current IGPIO_INJECTION -0.5 0.5 mA Absolute max, current injected per pin 34
Pin current for latch-up LU -100 100 mA 34
Max voltage on CC1 and CC2 pins VCC_PIN_ABS 24 V 34
Max voltage on SBU1 and SBU2 pins VSBU_PIN_ABS 24 V 34
OVT pins (16, 17) voltage VGPIO_OVT_ABS -0.5 6 V 34
Internal system ambient temperature TA -40 55 °C Ambient temp inside system enclosure 34
Junction temperature TJ -40 125 °C 34
ESD human body model ESD_HBM 2200 V All pins except SBU1_P0/1, SBU2_P0/1, CC1_0/1, CC2_0/1, VBUS_P_P0/1 & VBUS_C_P0/1 34
ESD HBM for SBU pins ESD_HBM_SBU 1100 V Only applicable to SBU1_P0/1, SBU2_P0/1 pins 34
ESD HBM for CC pins ESD_HBM_CC 1100 V Only applicable to CC1_P0/1, CC2_P0/1 pins 34
ESD charged device model ESD_CDM 500 V Charged device model ESD 34
ESD HBM for VBUS pins ESD_HBM_VBUS 500 V Only applicable to VBUS_P_P0/1 and VBUS_C_P0/1 pins 34
VSYS valid range UFP VSYS_UFP 2.75 5.5 V UFP applications 35
VSYS valid range DFP/DRP VSYS_UFP_DRP 3 5.5 V DFP/DRP applications 35
VBUS_C port 0/1 valid range VBUS_C 4 21.5 V 35
Max VBUS_C_P0/1 voltage relative to VSS VBUS_MAX 24 V -40°C to +55°C TA, absolute maximum 35
VBUS_P port 0/1 valid range VBUS_P 4.9 5.5 V This is not a power pin. 35
VDDD regulated output when VBUS powered VDDD 3 3.65 V -40°C ≤ TA ≤ +55°C 35
V5V supply V5V 4.85 5.5 V 35
CPU input frequency FCPU 48 MHz -40°C ≤TA ≤ +55°C, all VDDD 36
Power-up to Ready to accept I2C/CC command T_PWR_RDY 5 25 ms 36
VIH LVTTL input, VDDIO ≥ 2.7 V VIH_VDDIO2.7+ 2 V LVTTL input, VDDIO ≥ 2.7 V 36
VIL LVTTL input, VDDIO ≥ 2.7 V VIL_VDDIO2.7+ 0.8 V LVTTL input, VDDIO ≥ 2.7 V 36
Output low voltage VOL1_20mA 0.4 V IOL = 20 mA, VDDIO > 3.0 V, applicable for overvoltage-tolerant pins only 36
Output voltage LOW level VOL_3V 0.6 V IOL = 10 mA at 3-V VDDIO 36
Pull-up resistor when enabled Rpu 3.5 5.6 8.5 kΩ +25 °C TA, All VDDIO 36
Pull-down resistor when enabled Rpd 3.5 5.6 8.5 kΩ +25 °C TA, All VDDIO 36
Input leakage current (absolute value) IIL 2 nA +25 °C TA, 3-V VDDIO 36
Max pin capacitance CPIN 3 7 pF -40°C ≤ TA ≤ +55°C, ALL VDDD, ALL I/Os 36
Input hysteresis, LVTTL, VDDIO > 2.7 V VHYSTTL 15 40 mV VDDIO > 2.7 V. Guaranteed by characterization. 36
Input hysteresis CMOS VHYSCMOS55 200 mV VDDIO > 4.5 V 36
VIH, 1.8 V input mode VIH_VCCHIB 1.26 V 36
VIL, 1.8 V input mode VIL_VCCHIB 0.54 V 36
Input hysteresis, 1.8 V input mode VHYS_VCCHIB 90 mV 36
Rise time in Fast Strong mode TRISEF 2 12 ns 3.3-V VDDIO, Cload = 25 pF 37
Fall time in Fast Strong mode TFALLF 2 12 ns 3.3-V VDDIO, Cload = 25 pF 37
Rise time in Slow Strong mode TRISES 10 60 ns 3.3-V VDDIO, Cload = 25 pF 37
Fall time in Slow Strong mode TFALLS 10 60 ns 3.3-V VDDIO, Cload = 25 pF 37
GPIO FOUT Fast Strong, 3.3 V ≤ VDDIO ≤ 5.5 V FGPIO_OUT1 16 MHz 90/10%, 25-pF load 37
GPIO FOUT Fast Strong, 1.7 V ≤ VDDIO ≤ 3.3 V FGPIO_OUT2 16 MHz 90/10%, 25-pF load 37
GPIO FOUT Slow Strong, 3.3 V ≤ VDDIO ≤ 5.5 V FGPIO_OUT3 7 MHz 90/10%, 25-pF load 37
GPIO FOUT Slow Strong, 1.7 V ≤ VDDIO ≤ 3.3 V FGPIO_OUT4 3.5 MHz 90/10%, 25-pF load 37
GPIO input operating frequency FGPIO_IN 16 MHz 90/10% VIO 37
Input capacitance on XRES pin CIN_XRES 7 pF 37
VCONN switch ON resistance Ron 0.7 1.3 Ω V5V = 5 V with 215-mA load current 47
VCONN overcurrent detection range IOCP 550 mA 47
CC1/CC2 overvoltage protection threshold OVP_threshold 200 1200 mV Above VDDD or V5V, whichever is higher 47
VCONN switch turn-on time TON 200 µs 47
VBUS discharge NMOS Ron5 Ron5 300 600 Ω dischg_ds<4:0> = 1 47
Package thermal resistance JA (48-pin QFN) TJA 40.2 °C/W 49
Package thermal resistance JC (48-pin QFN) TJC 40.1 °C/W 49
Regulator bypass capacitor for VCCD CEFC 100 nF X5R ceramic 35
Power supply decoupling capacitor for VDDD CEXC 1 µF 35
VCCD regulated output VCCD 1.8 V 35
Active mode supply current IDD12 10 mA TA = 25°C, CC I/O IN transmit or receive, no I/O sourcing current, CPU at 24 MHz, PD port active 35
Deep Sleep supply current IDD29 150 µA VSYS = 3.3 V, TA = 25°C 35
Deep Sleep current, CC wakeup on IDD_DS1 200 µA Power source = VSYS, Type-C not attached, CC enabled for wakeup 35
Supply current while XRES asserted IDD_XR 130 µA Power source = VSYS = 3.3 V, Type-C not attached, TA = 25°C 35

CAD (KiCad official)

  • Symbol: CYPD6127-48LQXIT
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: QFN-48(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: cypd6127-48lqxit-etched.step / cypd6127-48lqxit-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cypd6127-48lqxit.step / cypd6127-48lqxit.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon/Cypress Semicon datasheet (59 pp, sha256 be31cde7b9b5053d, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF