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CYPD4226-40LQXI

Public Made by Adom

by adom

SPANSION Microcontroller Units (MCUs/MPUs/SOCs), QFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CYPD4226-40LQXI

SPANSION · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-40-EP(6x6)

CYPD4226-40LQXI from SPANSION, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SWD_IO/AR_RST#/P1.1 bidirectional Serial wire debug I/O, also usable as SCB0 signal or Alpine Ridge reset and GPIO P1.1.
2 SWD_CLK/I2C_CFG_EC/P1.2 input Serial wire debug clock, also usable as I2C_CFG_EC and GPIO P1.2.
3 I2C_SDA_SCB1_AR/VSEL_1_P0/P1.3 bidirectional I2C data line of SCB0 or SCB1, or voltage selection control for VBUS on port 0, also usable as GPIO P1.3.
4 I2C_SCL_SCB1_AR/VSEL_1_P1/P1.0 bidirectional I2C clock line of SCB1, or voltage selection control for VBUS on port 1, also usable as GPIO P1.0.
5 I2C_INT_AR_P0/OCP_DET_P0/P1.4 input I2C interrupt line or VBUS overcurrent protection input for port 0 (active LOW), also usable as GPIO P1.4.
6 I2C_INT_AR_P1/P1.5 bidirectional I2C interrupt line, also usable as SCB0/SCB1 function or GPIO P1.5.
7 CC2_P0 bidirectional USB PD connector detect and Configuration Channel 2 for Type-C port 0, with HBM and IEC ESD protection.
8 V5V_P0 power_in 2.7-V to 5.5-V supply for the VCONN FET of Type-C port 0.
9 CC1_P0 bidirectional USB PD connector detect and Configuration Channel 1 for Type-C port 0, with HBM and IEC ESD protection.
10 XRES input Reset input, active LOW.
11 VBUS_P_CTRL_P0/P1.6 bidirectional Full-rail control I/O for enabling or disabling the provider load FET of USB Type-C port 0, also usable as GPIO P1.6.
12 VBUS_C_CTRL_P0/P1.7 bidirectional Full-rail control I/O for enabling or disabling the consumer load FET of USB Type-C port 0, also usable as SCB0 function or GPIO P1.7.
13 VBUS_MON_P0/P2.0 bidirectional VBUS overvoltage protection monitoring signal for port 0, also usable as GPIO P2.0.
14 OVP_TRIP_P0/P2.1 output VBUS overvoltage output indicator for port 0, active LOW, also usable as GPIO P2.1.
15 I2C_INT_EC/P2.2 bidirectional I2C interrupt line, also usable as GPIO P2.2.
16 I2C_SDA_SCB0_EC/P0.0 bidirectional I2C data line of SCB0 or SCB2, also usable as GPIO P0.0.
17 I2C_SCL_SCB0_EC/P0.1 bidirectional I2C clock line of SCB0 or SCB3, also usable as GPIO P0.1.
18 HPD_P0/P2.3 bidirectional Hot Plug Detect I/O for port 0, also usable as GPIO P2.3.
19 VCONN_MON_P0/P2.4 bidirectional Monitors VCONN for an undervoltage protection condition on port 0, also usable as GPIO P2.4.
20 VBUS_DISCHARGE_P0/P2.5 bidirectional I/O used for discharging the VBUS line during voltage change on port 0, also usable as GPIO P2.5.
21 OVP_TRIP_P1/P3.0 output VBUS overvoltage output indicator for port 1 (active LOW), also usable as GPIO P3.0.
22 CC1_P1 bidirectional USB PD connector detect and Configuration Channel 1 for Type-C port 1, with HBM and IEC ESD protection.
23 V5V_P1 power_in 2.7-V to 5.5-V supply for the VCONN FET of Type-C port 1.
24 CC2_P1 bidirectional USB PD connector detect and Configuration Channel 2 for Type-C port 1, with HBM and IEC ESD protection.
25 SCL_2/VCONN_MON_P1/P2.7 bidirectional SCB2 I2C clock, or VCONN monitor for undervoltage protection on port 1, also usable as GPIO P2.7.
26 SDA_2/MUX_CTRL_3_P0/VSEL_2_P0/P2.6 bidirectional SCB2 data, or mux control 3 for port 0, or voltage selection control for VBUS on port 0, also usable as GPIO P2.6.
27 VSEL_2_P1/P3.1 bidirectional Voltage selection control for VBUS on port 1, also usable as GPIO P3.1.
28 SDA_3/MUX_CTRL_2_P0/P3.2 bidirectional SCB3 data, or mux control 2 for port 0, also usable as GPIO P3.2.
29 SCL_3/MUX_CTRL_1_P0/P3.3 bidirectional SCB3 clock, or mux control 1 for port 0, also usable as GPIO P3.3.
30 HPD_P1/P3.4 bidirectional Hot Plug Detect I/O for port 1, also usable as GPIO P3.4.
31 VDDD power_in VDDD supply input/output, 2.7 V to 5.5 V; the internal operating supply is derived from this pin.
32 VDDIO power_in Supply for I/Os, 1.71 V to 5.5 V, which should be less than or equal to VDDD.
33 VCCD power_out 1.8-V regulator output for the filter capacitor, which cannot drive an external load.
34 MUX_CTRL_3_P1/OCP_DET_P1/P3.5 bidirectional Mux control for port 1 or VBUS overcurrent protection input for port 1 (active LOW), also usable as GPIO P3.5.
35 MUX_CTRL_2_P1/P3.6 bidirectional Mux control for port 1, also usable as SCB3 function or GPIO P3.6.
36 MUX_CTRL_1_P1/P3.7 bidirectional Mux control for port 1, also usable as SCB3 function or GPIO P3.7.
37 VBUS_MON_P1/P4.0 bidirectional VBUS overvoltage protection monitoring signal for port 1, also usable as GPIO P4.0.
38 VBUS_C_CTRL_P1/P4.1 bidirectional Full-rail control I/O for enabling or disabling the consumer load FET of USB Type-C port 1, also usable as GPIO P4.1.
39 VBUS_P_CTRL_P1/P4.2 bidirectional Full-rail control I/O for enabling or disabling the provider load FET of USB Type-C port 1, also usable as GPIO P4.2.
40 VBUS_DISCHARGE_P1/P4.3 bidirectional I/O used for discharging the VBUS line during voltage change on port 1, also usable as GPIO P4.3.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer SPANSION
Package QFN-40-EP(6x6)
Category Embedded Processors & Controllers
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_MAX -0.5 6 V Absolute max 22
Max supply voltage relative to VSS V5V_P0 6 V Absolute max 22
GPIO voltage VGPIO_ABS -0.5 V Absolute max; printed max is VDDIO + 0.5 22
Maximum current per GPIO IGPIO_ABS -25 25 mA Absolute max 22
GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS IGPIO_injection -0.5 0.5 mA Absolute max, current injected per pin 22
Electrostatic discharge human body model ESD_HBM 2200 V 22
Electrostatic discharge charged device model ESD_CDM 500 V 22
Pin current for latch-up LU -200 200 mA 22
Electrostatic discharge IEC61000-4-2 ESD_IEC_CON 8000 V Contact discharge on CC1 and CC2 pins 22
Electrostatic discharge IEC61000-4-2 ESD_IEC_AIR 15000 V Air discharge for pins CC1 and CC2 22
Power supply input voltage SID.PWR#1 2.7 5.5 V UFP applications 23
Power supply input voltage SID.PWR#1_A 3.15 5.5 V DFP/DRP applications 23
Power supply input voltage SID.PWR#26 V5V_P0, V5V_P1 4.85 5.5 V 23
GPIO power supply PWR#13 VDDIO 1.71 5.5 V 23
Output voltage (for core logic) SID.PWR#24 VCCD 1.8 V 23
External regulator voltage bypass on VCCD SID.PWR#15 CEFC 80 100 120 nF X5R ceramic or better 23
Power supply decoupling capacitor on VDDD SID.PWR#16 CEXC 0.8 1 µF X5R ceramic or better 23
Power supply decoupling capacitor on V5V_P0 and V5V_P1 SID.PWR#27 CEXV 0.1 µF X5R ceramic or better 23
Supply current SID.PWR#4 IDD12 10 mA V5V_P0 and V5V_P1 = 5 V, TA = 25 °C, CC I/O IN Transmit or Receive, no I/O sourcing current, CPU at 24 MHz, two PD ports active 23
Sleep mode supply current, I2C wakeup, WDT ON, IMO at 48 MHz SID25A IDD20A 2.5 4 mA VDDD = 3.3 V, TA = 25 °C, all blocks except CPU are ON, CC I/O ON, no I/O sourcing current 23
Deep Sleep supply current SID34 IDD29 80 µA I2C wakeup and WDT ON; VDDD = 3.3 V, TA = 25 °C 23
Deep Sleep supply current, CC wakeup ON SID_DS IDD_DS 2.5 µA Power source = VDDD, Type-C not attached, CC enabled for wakeup, RP disabled 23
Deep Sleep supply current, CC wakeup ON, RP and RD connected at 70 ms intervals SID_DS1 IDD_DS1 100 µA Power source = VDDD, Type-C not attached, CC enabled for wakeup, RP and RD connected at 70 ms intervals by CPU. RP, RD connection should be enabled for both PD ports. 23
Supply current while XRES asserted SID307 IDD_XR 1 10 µA 23
DFP CC termination for default USB Power SID.PD.1 Rp_std 64 80 96 µA 29
DFP CC termination for 1.5A power SID.PD.2 Rp_1.5A 166 180 194 µA 29
DFP CC termination for 3.0A power SID.PD.3 Rp_3.0A 304 330 356 µA 29
UFP CC termination SID.PD.4 Rd 4.59 5.1 5.61 kΩ 29
UFP Dead Battery CC termination on CC1 and CC2 SID.PD.5 Rd_DB 4.08 5.1 6.12 kΩ All supplies forced to 0 V and 1.0 V applied at CC1 or CC2. Applicable for DRP applications only. 29
Voltage drop from V5V_P0 and V5V_P1 pins to CC1 pin SID.PD.15 Vdrop_V5V_CC1 100 mV while sourcing 215 mA 29
Voltage drop from V5V_P0 and V5V_P1 pins to CC2 pin SID.PD.16 Vdrop_V5V_CC2 100 mV while sourcing 215 mA 29
ADC resolution SID.ADC.1 Resolution 8 bits 29
Integral nonlinearity SID.ADC.2 INL -1.5 1.5 LSB 29
Differential nonlinearity SID.ADC.3 DNL -2.5 2.5 LSB 29
Gain error SID.ADC.4 Gain Error -1 1 LSB 29
Rate of change of sampled voltage signal SID.ADC.5 SLEW_Max 3 V/ms 29
Operating ambient temperature TA -40 25 85 °C 31
Operating junction temperature TJ -40 100 °C 31
Package JA (40-pin QFN) TJA 31 °C/W 31
Package JC (40-pin QFN) TJC 29 °C/W 31

CAD (KiCad official)

  • Symbol: CYPD4226-40LQXI
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: cypd4226-40lqxi-etched.step / cypd4226-40lqxi-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cypd4226-40lqxi.step / cypd4226-40lqxi.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SPANSION datasheet (39 pp, sha256 e3db4d24156343a8, retrieved 2026-10-28, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF