# CYPD3175-24LQXQT

**Infineon** · USB Converters · QFN-24-EP(4x4)

CYPD3175-24LQXQT from Infineon, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.0 | bidirectional | Port 1 pin 0. Multi-function GPIO: UART_1_CTS / I2C_SDA_1 / TCPWM_line_0 / programmable SCP/OCP/OVP/UVP fault indication. |
| 2 | P1.1 | bidirectional | Port 1 pin 1. Multi-function GPIO: UART_1_RTS / I2C_SCL_1 / TCPWM_line_1 / programmable SCP/OCP/OVP/UVP fault indication. |
| 3 | VBUS_P_CTRL | output | Provider-side PMOS FET gate control, 30 V tolerant. Drive low to turn path ON, high to turn path OFF. |
| 4 | VBUS_C_CTRL | output | Consumer-side PMOS FET gate control, 30 V tolerant. Drive low to turn path ON, high-Z to turn path OFF. |
| 5 | DP1/P1.2 | bidirectional | USB D+ (secondary) / Port 1 pin 2 GPIO. Also usable as UART_1_TX1 or as legacy charging detection (AFC/QC/BC 1.2/Apple). |
| 6 | DM1/P1.3 | bidirectional | USB D- (secondary) / Port 1 pin 3 GPIO. Also usable as UART_1_RX1 or legacy charging detection (AFC/QC/BC 1.2/Apple). |
| 7 | SWD_DAT_0/P0.0 | bidirectional | SWD data / Port 0 pin 0 GPIO with over-voltage tolerance. Also I2C_SDA_0 / TCPWM_line_0 / UART_0_CTS. |
| 8 | SWD_CLK_0/P0.1 | bidirectional | SWD clock / Port 0 pin 1 GPIO with over-voltage tolerance. Also I2C_SCL_0 / TCPWM_line_1 / UART_0_RTS. |
| 9 | AXRES/P2.0 | bidirectional | Alternate external reset (active low) / Port 2 pin 0 GPIO. Also TCPWM_line_0 or UART_0_TX0. Internally pulled up during POR I/O init. |
| 10 | P2.1 | bidirectional | Port 2 pin 1 GPIO. Also TCPWM_line_1 or UART_0_RX0. |
| 11 | VBUS_C_MON_DISCHARGE | passive | Type-C VBUS monitor input with internal discharge FET. Connect to the consumer-side VBUS rail through the recommended divider network. |
| 12 | P2.2 | bidirectional | Port 2 pin 2 GPIO with open drain and pull-up assist. Configurable as GPIO_20VT / I2C_SDA_1 / IEC. Tolerant to temporary short to VBUS. |
| 13 | P2.3 | bidirectional | Port 2 pin 3 GPIO with open drain and pull-up assist. Configurable as GPIO_20VT / I2C_SCL_1 / IEC. Tolerant to temporary short to VBUS. |
| 14 | CC2 | bidirectional | USB Type-C Configuration Channel 2 with dead-battery Rd bonding option and IEC ESD protection. Tolerant to temporary short to VBUS. |
| 15 | CC1 | bidirectional | USB Type-C Configuration Channel 1 with dead-battery Rd bonding option and IEC ESD protection. Tolerant to temporary short to VBUS. |
| 16 | DM0/P3.1 | bidirectional | USB D- (primary) / Port 3 pin 1 GPIO. Also UART_1_RX0 or legacy charging detection (AFC/QC/BC 1.2/Apple). IEC ESD protected. |
| 17 | DP0/P3.0 | bidirectional | USB D+ (primary) / Port 3 pin 0 GPIO. Also UART_1_TX0 or legacy charging detection (AFC/QC/BC 1.2/Apple). IEC ESD protected. |
| 18 | VBUS_IN_DISCHARGE | power_in | VBUS power input, 3.0 V to 24.5 V, with internal discharge FET. Primary supply source when powered from Type-C VBUS. |
| 19 | CSP | input | Current-sense positive input for VBUS current monitoring via external shunt. |
| 20 | FB | input | Voltage regulation feedback pin used for direct-feedback DFP adapter voltage control. |
| 21 | CATH/COMP | bidirectional | Cathode of internal voltage-regulation shunt / loop compensation node for external analog applications. |
| 22 | GND | power_in | Device ground reference. Tie to system ground plane along with the exposed thermal pad. |
| 23 | VDDD | power_in | Digital supply input, 2.7 V to 5.5 V. When VBUS_IN_DISCHARGE is the primary supply, VDDD is regulated internally to 3.3 V and requires only a 1 µF decoupling capacitor. |
| 24 | VCCD | power_out | 1.8 V regulated core-logic supply output. Requires a 1 µF decoupling capacitor. Not intended to power external circuitry. |
| 25 | EPAD | power_in | Exposed thermal pad on package underside. Connect to ground plane for thermal and electrical grounding. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Infineon |
| Package | QFN-24-EP(4x4) |
| Category | Interface |
| Pins | 25 |

## Ordering variants

Same part, different packaging or reel option.

- `CYPD3175-24LQXQT`
- `CYPD3174-16SXQ`

## CAD (KiCad official)

- Symbol: `CYPD3175-24LQXQT`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm`
- 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `cypd3175-24lqxqt-etched.step` / `cypd3175-24lqxqt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cypd3175-24lqxqt.step` / `cypd3175-24lqxqt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Infineon datasheet](docs/cypd3175-24lqxqt-datasheet.pdf) (37 pp, sha256 `0be360796cb78e34`, retrieved 2026-08-17, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cypd3175-24lqxqt-datasheet.pdf)