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CYHCPL3120S
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OCIC Optocouplers - Logic Output, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CYHCPL3120S
OCIC · Optocouplers - Logic Output · SOP-8
CYHCPL3120S from OCIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal connection. |
| 2 | ANODE | input | LED anode input; recommended LED on-current is 7 to 16 mA, absolute maximum forward current is 25 mA. |
| 3 | CATHODE | input | LED cathode input; the LED is off for an input voltage of 0 to 0.8 V, and the maximum reverse input voltage is 5 V. |
| 4 | NC | unconnected | No internal connection. |
| 5 | VSS | power_in | Output-side negative supply/ground; a 0.1 uF bypass capacitor must be connected between pins 5 and 8. |
| 6 | VO1 | output | Gate-drive output (push-pull stage), peak output current 2.5 A typical; must be used connected in parallel with pin 7. |
| 7 | VO2 | output | Gate-drive output connected to the P-channel MOSFET stage; its external circuit must be used in parallel with pin 6. |
| 8 | VDD | power_in | Positive output supply, VDD-VSS 0 to 30 V; a 0.1 uF bypass capacitor must be connected between pins 5 and 8. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | OCIC |
| Package | SOP-8 |
| Category | Optocoupler/LED/Digital Tube/Photoelectric Device |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Forward input current, max (IFM) | IFM | 25 | mA | 2 | |||
| Input reverse voltage | VR | 5 | V | 2 | |||
| Peak output current | IO(PEAK) | 3 | A | 2 | |||
| Supply voltage (VDD-VSS) | VDD-VSS | 0 | 30 | V | 2 | ||
| Peak output voltage | VO(PECK) | 0 | V | printed as 0 to VDD; upper limit is VDD, not a number | 2 | ||
| Input signal rise/fall time | tR(IN), tF(IN) | 500 | ns | 2 | |||
| Storage temperature | TSTG | -55 | 125 | ℃ | 2 | ||
| Operating temperature (absolute maximum table) | TA | -40 | 100 | ℃ | 2 | ||
| Operating ambient temperature (recommended) | TA | -40 | 100 | ℃ | 2 | ||
| Supply voltage (recommended) | VDD-VSS | 0 | 30 | V | 2 | ||
| Peak output voltage (recommended) | VO(PECK) | 15 | V | printed as 15 to VDD; upper limit is VDD, not a number | 2 | ||
| Input current (ON) | IFON) | 7 | 16 | mA | 2 | ||
| Input voltage (OFF) | VF(OFF) | 0 | 0.8 | V | 2 | ||
| Input forward voltage | VF | 1.2 | 1.5 | 1.8 | V | IF=10mA | 3 |
| High-level output current (Vo=VDD-3V) | IOH | -1 | -2 | -2.5 | A | Vo=VDD-3V | 3 |
| Low-level output current (Vo=VSS+3V) | IOL | 1 | 2 | 2.5 | A | Vo=VSS+3V | 3 |
| Low-to-high UVLO threshold voltage | VUVLO+ | 11.5 | 12.7 | 13.5 | V | IF=10mA, VO>5V | 3 |
| High-to-low UVLO threshold voltage | VUVLO- | 10 | 11.2 | 12 | V | IF=10mA, VO<5V | 3 |
| Logic low propagation delay | tPHL | 150 | 275 | 400 | ns | IF=7mA to 16mA, Rg=10Ω, Cg=10nF, f=10kHz, 占空比=50% | 3 |
| Logic high propagation delay | tPLH | 150 | 255 | 400 | ns | IF=7mA to 16mA, Rg=10Ω, Cg=10nF, f=10kHz, 占空比=50% | 3 |
| Propagation delay difference (tPHL-tPLH) | PDD (Skew) | -250 | 250 | ns | Note: difference between any two CYHCPL3120 devices under same test conditions | 3 |
CAD (KiCad official)
- Symbol:
CYHCPL3120S - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
cyhcpl3120s-etched.step/cyhcpl3120s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cyhcpl3120s.step/cyhcpl3120s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: OCIC datasheet (14 pp, sha256
da8b5edc98e6b34e, retrieved 2026-11-04, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CYHCPL3120S
**OCIC** · Optocouplers - Logic Output · SOP-8
CYHCPL3120S from OCIC, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal connection. |
| 2 | ANODE | input | LED anode input; recommended LED on-current is 7 to 16 mA, absolute maximum forward current is 25 mA. |
| 3 | CATHODE | input | LED cathode input; the LED is off for an input voltage of 0 to 0.8 V, and the maximum reverse input voltage is 5 V. |
| 4 | NC | unconnected | No internal connection. |
| 5 | VSS | power_in | Output-side negative supply/ground; a 0.1 uF bypass capacitor must be connected between pins 5 and 8. |
| 6 | VO1 | output | Gate-drive output (push-pull stage), peak output current 2.5 A typical; must be used connected in parallel with pin 7. |
| 7 | VO2 | output | Gate-drive output connected to the P-channel MOSFET stage; its external circuit must be used in parallel with pin 6. |
| 8 | VDD | power_in | Positive output supply, VDD-VSS 0 to 30 V; a 0.1 uF bypass capacitor must be connected between pins 5 and 8. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | OCIC |
| Package | SOP-8 |
| Category | Optocoupler/LED/Digital Tube/Photoelectric Device |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Forward input current, max (IFM) | IFM | | | 25 | mA | | 2 |
| Input reverse voltage | VR | | | 5 | V | | 2 |
| Peak output current | IO(PEAK) | | | 3 | A | | 2 |
| Supply voltage (VDD-VSS) | VDD-VSS | 0 | | 30 | V | | 2 |
| Peak output voltage | VO(PECK) | 0 | | | V | printed as 0 to VDD; upper limit is VDD, not a number | 2 |
| Input signal rise/fall time | tR(IN), tF(IN) | | | 500 | ns | | 2 |
| Storage temperature | TSTG | -55 | | 125 | ℃ | | 2 |
| Operating temperature (absolute maximum table) | TA | -40 | | 100 | ℃ | | 2 |
| Operating ambient temperature (recommended) | TA | -40 | | 100 | ℃ | | 2 |
| Supply voltage (recommended) | VDD-VSS | 0 | | 30 | V | | 2 |
| Peak output voltage (recommended) | VO(PECK) | 15 | | | V | printed as 15 to VDD; upper limit is VDD, not a number | 2 |
| Input current (ON) | IFON) | 7 | | 16 | mA | | 2 |
| Input voltage (OFF) | VF(OFF) | 0 | | 0.8 | V | | 2 |
| Input forward voltage | VF | 1.2 | 1.5 | 1.8 | V | IF=10mA | 3 |
| High-level output current (Vo=VDD-3V) | IOH | -1 | -2 | -2.5 | A | Vo=VDD-3V | 3 |
| Low-level output current (Vo=VSS+3V) | IOL | 1 | 2 | 2.5 | A | Vo=VSS+3V | 3 |
| Low-to-high UVLO threshold voltage | VUVLO+ | 11.5 | 12.7 | 13.5 | V | IF=10mA, VO>5V | 3 |
| High-to-low UVLO threshold voltage | VUVLO- | 10 | 11.2 | 12 | V | IF=10mA, VO<5V | 3 |
| Logic low propagation delay | tPHL | 150 | 275 | 400 | ns | IF=7mA to 16mA, Rg=10Ω, Cg=10nF, f=10kHz, 占空比=50% | 3 |
| Logic high propagation delay | tPLH | 150 | 255 | 400 | ns | IF=7mA to 16mA, Rg=10Ω, Cg=10nF, f=10kHz, 占空比=50% | 3 |
| Propagation delay difference (tPHL-tPLH) | PDD (Skew) | -250 | | 250 | ns | Note: difference between any two CYHCPL3120 devices under same test conditions | 3 |
## CAD (KiCad official)
- Symbol: `CYHCPL3120S`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `cyhcpl3120s-etched.step` / `cyhcpl3120s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cyhcpl3120s.step` / `cyhcpl3120s.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [OCIC datasheet](docs/cyhcpl3120s-datasheet.pdf) (14 pp, sha256 `da8b5edc98e6b34e`, retrieved 2026-11-04, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cyhcpl3120s-datasheet.pdf)