component

CY9BF516NPMC-G-JNE2

Public Made by Adom

by adom

Cypress Semicon Pre-ordered Products, LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentelectronic tools-instruments-consumablescy9bf516npmc-g-jne2factory-2.0.0extractor-text

Verified CY9BF516NPMC-G-JNE2

by Ray · last 13 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

13 Nov 2026RayPublished by the parts factory: tier lcsc, 100 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • •array (skip): not an array of element pairs
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY9BF516NPMC-G-JNE2 · LQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 118-page datasheet
  • ✓distributor: lcsc C2947753, digikey 448-CY9BF516NPMC-G-JNE2-ND, mouser 727-9BF516NPMCGJN
  • ✓family: LQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-6kw0ya8f/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.111)
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 108 kB, viewers/symbol.html 68 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy9bf516npmc-g-jne2.kicad_sym✓ cy9bf516npmc-g-jne2.kicad_mod✓ cy9bf516npmc-g-jne2.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cy9bf516npmc-g-jne2: viewers rendered from the public page · Ray
cy9bf516npmc-g-jne2-etched.glb cy9bf516npmc-g-jne2: factory component page (tier=lcsc) · Ray
cy9bf516npmc-g-jne2-etched.step cy9bf516npmc-g-jne2: factory component page (tier=lcsc) · Ray
cy9bf516npmc-g-jne2-hero.glb cy9bf516npmc-g-jne2: hero GLB from the etched model (keeps the MPN mark) · Ray
cy9bf516npmc-g-jne2-hero.overlay.json cy9bf516npmc-g-jne2: hero GLB from the etched model (keeps the MPN mark) · Ray
cy9bf516npmc-g-jne2.glb Publish 0.1.0 · Ray
cy9bf516npmc-g-jne2.kicad_mod Publish 0.1.0 · Ray
cy9bf516npmc-g-jne2.kicad_sym Publish 0.1.0 · Ray
cy9bf516npmc-g-jne2.lbr Publish 0.1.0 · Ray
cy9bf516npmc-g-jne2.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 100 pins · Ray

CY9BF516NPMC-G-JNE2

Cypress Semicon · Pre-ordered Products · LQFP-100(14x14)

CY9BF516NPMC-G-JNE2 from Cypress Semicon, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Digital power supply, 2.7 V to 5.5 V.
2 P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_0 bidirectional GPIO P50 with external interrupt 00, QPRC0 AIN, MFS3 SIN, MFT1 RTO10 and external bus data 0.
3 P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_0 bidirectional GPIO P51 with external interrupt 01, QPRC0 BIN, MFS3 SOT/SDA, MFT1 RTO11 and external bus data 1.
4 P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_0 bidirectional GPIO P52 with external interrupt 02, QPRC0 ZIN, MFS3 SCK/SCL, MFT1 RTO12 and external bus data 2.
5 P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_0 bidirectional GPIO P53 with MFS6 SIN, base timer 1 TIOA, external interrupt 07, MFT1 RTO13 and external bus data 3.
6 P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_0 bidirectional GPIO P54 with MFS6 SOT/SDA, base timer 1 TIOB, MFT1 RTO14 and external bus data 4.
7 P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_0 bidirectional GPIO P55 with MFS6 SCK/SCL, ADC trigger 1, MFT1 RTO15 and external bus data 5.
8 P56/INT08_2/DTTI1X_0/MADATA06_0 bidirectional GPIO P56 with external interrupt 08, MFT1 DTTI1X input and external bus data 6.
9 P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_0 bidirectional GPIO P30 with QPRC0 AIN, base timer 0 TIOB, external interrupt 03 and external bus data 7.
10 P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_0 bidirectional GPIO P31 with QPRC0 BIN, base timer 1 TIOB, MFS6 SCK/SCL, external interrupt 04 and external bus data 8.
11 P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_0 bidirectional GPIO P32 with QPRC0 ZIN, base timer 2 TIOB, MFS6 SOT/SDA, external interrupt 05 and external bus data 9.
12 P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_0 bidirectional GPIO P33 with external interrupt 04, base timer 3 TIOB, MFS6 SIN, ADC trigger 6 and external bus data 10.
13 P34/FRCK0_0/TIOB4_1/TX0_1/MADATA11_0 bidirectional GPIO P34 with MFT0 free-run clock, base timer 4 TIOB, CAN0 TX and external bus data 11.
14 P35/IC03_0/TIOB5_1/RX0_1/INT08_1/MADATA12_0 bidirectional GPIO P35 with MFT0 input capture 3, base timer 5 TIOB, CAN0 RX, external interrupt 08 and external bus data 12.
15 P36/IC02_0/SIN5_2/INT09_1/MADATA13_0 bidirectional GPIO P36 with MFT0 input capture 2, MFS5 SIN, external interrupt 09 and external bus data 13.
16 P37/IC01_0/SOT5_2/INT10_1/MADATA14_0 bidirectional GPIO P37 with MFT0 input capture 1, MFS5 SOT/SDA, external interrupt 10 and external bus data 14.
17 P38/IC00_0/SCK5_2/INT11_1/MADATA15_0 bidirectional GPIO P38 with MFT0 input capture 0, MFS5 SCK/SCL, external interrupt 11 and external bus data 15.
18 P39/DTTI0X_0/ADTG_2 bidirectional GPIO P39 with MFT0 DTTI0X input and ADC trigger 2.
19 P3A/RTO00_0/TIOA0_1/RTCCO_2/SUBOUT_2 bidirectional GPIO P3A with MFT0 RTO00, base timer 0 TIOA, RTC 0.5 s pulse output and sub clock output.
20 P3B/RTO01_0/TIOA1_1 bidirectional GPIO P3B with MFT0 RTO01 and base timer 1 TIOA.
21 P3C/RTO02_0/TIOA2_1 bidirectional GPIO P3C with MFT0 RTO02 and base timer 2 TIOA.
22 P3D/RTO03_0/TIOA3_1 bidirectional GPIO P3D with MFT0 RTO03 and base timer 3 TIOA.
23 P3E/RTO04_0/TIOA4_1 bidirectional GPIO P3E with MFT0 RTO04 and base timer 4 TIOA.
24 P3F/RTO05_0/TIOA5_1 bidirectional GPIO P3F with MFT0 RTO05 and base timer 5 TIOA.
25 VSS power_in Ground pin.
26 VCC power_in Digital power supply, 2.7 V to 5.5 V.
27 P40/TIOA0_0/RTO10_1/INT12_1 bidirectional GPIO P40 with base timer 0 TIOA, MFT1 RTO10 and external interrupt 12.
28 P41/TIOA1_0/RTO11_1/INT13_1 bidirectional GPIO P41 with base timer 1 TIOA, MFT1 RTO11 and external interrupt 13.
29 P42/TIOA2_0/RTO12_1 bidirectional GPIO P42 with base timer 2 TIOA and MFT1 RTO12.
30 P43/TIOA3_0/RTO13_1/ADTG_7 bidirectional GPIO P43 with base timer 3 TIOA, MFT1 RTO13 and ADC trigger 7.
31 P44/TIOA4_0/RTO14_1/MAD00_0 bidirectional GPIO P44 with base timer 4 TIOA, MFT1 RTO14 and external bus address 0.
32 P45 bidirectional GPIO P45 with base timer 5 TIOA, MFT1 RTO15 and external bus address 1.
33 C passive Power stabilization capacitor pin for the built-in 1.2 V regulator; smoothing capacitor 1 to 10 uF.
34 VSS power_in Ground pin.
35 VCC power_in Digital power supply, 2.7 V to 5.5 V.
36 P46/X0A bidirectional GPIO P46 or sub clock (32.768 kHz) oscillation input X0A.
37 P47/X1A bidirectional GPIO P47 or sub clock oscillation I/O X1A.
38 INITX input External reset input; reset is valid when INITX is low.
39 P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_0 bidirectional GPIO P48 with MFT1 DTTI1X, external interrupt 14, MFS3 SIN and external bus address 2.
40 P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_0 bidirectional GPIO P49 with base timer 0 TIOB, MFT1 input capture 0, QPRC0 AIN, MFS3 SOT/SDA and external bus address 3.
41 P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_0 bidirectional GPIO P4A with base timer 1 TIOB, MFT1 input capture 1, QPRC0 BIN, MFS3 SCK/SCL and external bus address 4.
42 P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_0 bidirectional GPIO P4B with base timer 2 TIOB, MFT1 input capture 2, QPRC0 ZIN and external bus address 5.
43 P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_0 bidirectional 5 V tolerant GPIO P4C with base timer 3 TIOB, MFT1 input capture 3, MFS7 SCK/SCL, QPRC1 AIN and external bus address 6.
44 P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_0 bidirectional 5 V tolerant GPIO P4D with base timer 4 TIOB, MFT1 free-run clock, MFS7 SOT/SDA, QPRC1 BIN and external bus address 7.
45 P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_0 bidirectional 5 V tolerant GPIO P4E with base timer 5 TIOB, external interrupt 06, MFS7 SIN, QPRC1 ZIN and external bus address 8.
46 PE0/MD1 input GPIO PE0 / mode pin 1; MD1 must be low during serial programming to Flash memory.
47 MD0 input Mode pin 0; must be low in normal operation and high during serial Flash programming.
48 PE2/X0 bidirectional GPIO PE2 or main clock (4 MHz to 48 MHz) oscillation input X0.
49 PE3/X1 bidirectional GPIO PE3 or main clock oscillation I/O X1.
50 VSS power_in Ground pin.
51 VCC power_in Digital power supply, 2.7 V to 5.5 V.
52 P10/AN00 bidirectional GPIO P10 with A/D converter analog input 0.
53 P11/AN01/SIN1_1/INT02_1/RX1_2/FRCK0_2/MAD09_0 bidirectional GPIO P11 with ADC input 1, MFS1 SIN, external interrupt 02, CAN1 RX, MFT0 free-run clock and external bus address 9.
54 P12/AN02/SOT1_1/TX1_2/IC00_2/MAD10_0 bidirectional GPIO P12 with ADC input 2, MFS1 SOT/SDA, CAN1 TX, MFT0 input capture 0 and external bus address 10.
55 P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/IC01_2/MAD11_0 bidirectional GPIO P13 with ADC input 3, MFS1 SCK/SCL, RTC output, sub clock output, MFT0 input capture 1 and external bus address 11.
56 P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_0 bidirectional GPIO P14 with ADC input 4, MFS0 SIN, external interrupt 03, MFT0 input capture 2 and external bus address 12.
57 P15/AN05/SOT0_1/IC03_2/MAD13_0 bidirectional GPIO P15 with ADC input 5, MFS0 SOT/SDA, MFT0 input capture 3 and external bus address 13.
58 P16/AN06/SCK0_1/MAD14_0 bidirectional GPIO P16 with ADC input 6, MFS0 SCK/SCL and external bus address 14.
59 P17/AN07/SIN2_2/INT04_1/MAD15_0 bidirectional GPIO P17 with ADC input 7, MFS2 SIN, external interrupt 04 and external bus address 15.
60 AVCC power_in A/D converter analog power supply, 2.7 V to 5.5 V (AVCC = VCC).
61 AVRH power_in A/D converter analog reference voltage input, 2.7 V to AVCC.
62 AVSS power_in A/D converter ground pin.
63 P18/AN08/SOT2_2/MAD16_0 bidirectional GPIO P18 with ADC input 8, MFS2 SOT/SDA and external bus address 16.
64 P19/AN09/SCK2_2/MAD17_0 bidirectional GPIO P19 with ADC input 9, MFS2 SCK/SCL and external bus address 17.
65 P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_0 bidirectional GPIO P1A with ADC input 10, MFS4 SIN, external interrupt 05, MFT0 input capture 0 and external bus address 18.
66 P1B/AN11/SOT4_1/IC01_1/MAD19_0 bidirectional GPIO P1B with ADC input 11, MFS4 SOT/SDA, MFT0 input capture 1 and external bus address 19.
67 P1C/AN12/SCK4_1/IC02_1/MAD20_0 bidirectional GPIO P1C with ADC input 12, MFS4 SCK/SCL, MFT0 input capture 2 and external bus address 20.
68 P1D/AN13/CTS4_1/IC03_1/MAD21_0 bidirectional GPIO P1D with ADC input 13, MFS4 CTS, MFT0 input capture 3 and external bus address 21.
69 P1E/AN14/RTS4_1/DTTI0X_1/MAD22_0 bidirectional GPIO P1E with ADC input 14, MFS4 RTS, MFT0 DTTI0X and external bus address 22.
70 P1F/AN15/ADTG_5/FRCK0_1/MAD23_0 bidirectional GPIO P1F with ADC input 15, ADC trigger 5, MFT0 free-run clock and external bus address 23.
71 P23/SCK0_0/TIOA7_1 bidirectional GPIO P23 with MFS0 SCK/SCL and base timer 7 TIOA.
72 P22/SOT0_0/TIOB7_1/ZIN1_1 bidirectional GPIO P22 with MFS0 SOT/SDA, base timer 7 TIOB and QPRC1 ZIN.
73 P21/SIN0_0/INT06_1/BIN1_1 bidirectional GPIO P21 with MFS0 SIN, external interrupt 06 and QPRC1 BIN.
74 P20/INT05_0/CROUT_0/AIN1_1/MAD24_0 bidirectional GPIO P20 with external interrupt 05, high-speed CR clock output, QPRC1 AIN and external bus address 24.
75 VSS power_in Ground pin.
76 VCC power_in Digital power supply, 2.7 V to 5.5 V.
77 P00/TRSTX/MCSX7_0 bidirectional GPIO P00 with JTAG test reset input and external bus chip select 7.
78 P01/TCK/SWCLK bidirectional GPIO P01 with JTAG test clock input and serial wire debug clock.
79 P02/TDI/MCSX6_0 bidirectional GPIO P02 with JTAG test data input and external bus chip select 6.
80 P03/TMS/SWDIO bidirectional GPIO P03 with JTAG test mode select and serial wire debug data I/O.
81 P04/TDO/SWO bidirectional GPIO P04 with JTAG test data output and serial wire viewer output.
82 P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_0 bidirectional GPIO P05 with ETM trace data 0, base timer 5 TIOA, MFS4 SIN, external interrupt 00 and chip select 5.
83 P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/AIN2_1/MCSX4_0 bidirectional GPIO P06 with ETM trace data 1, base timer 5 TIOB, MFS4 SOT/SDA, external interrupt 01, QPRC2 AIN and chip select 4.
84 P07/TRACED2/ADTG_0/SCK4_2/BIN2_1/MCLKOUT_0 bidirectional GPIO P07 with ETM trace data 2, ADC trigger 0, MFS4 SCK/SCL, QPRC2 BIN and external bus clock output.
85 P08/TRACED3/TIOA0_2/CTS4_2/ZIN2_1/MCSX3_0 bidirectional GPIO P08 with ETM trace data 3, base timer 0 TIOA, MFS4 CTS, QPRC2 ZIN and chip select 3.
86 P09/TRACECLK/TIOB0_2/RTS4_2/RTO20_1/MCSX2_0 bidirectional GPIO P09 with ETM trace clock, base timer 0 TIOB, MFS4 RTS, MFT2 RTO20 and chip select 2.
87 P0A/SIN4_0/INT00_2/FRCK1_0/FRCK2_0/RTO21_1/MCSX1_0 bidirectional 5 V tolerant GPIO P0A with MFS4 SIN, external interrupt 00, MFT1/MFT2 free-run clocks, MFT2 RTO21 and chip select 1.
88 P0B/SOT4_0/TIOB6_1/IC10_0/IC20_0/RTO22_1/MCSX0_0 bidirectional 5 V tolerant GPIO P0B with MFS4 SOT/SDA, base timer 6 TIOB, input captures IC10/IC20, MFT2 RTO22 and chip select 0.
89 P0C/SCK4_0/TIOA6_1/IC11_0/IC21_0/RTO23_1/MALE_0 bidirectional 5 V tolerant GPIO P0C with MFS4 SCK/SCL, base timer 6 TIOA, input captures IC11/IC21, MFT2 RTO23 and external bus address latch enable.
90 P0D/RTS4_0/TIOA3_2/IC12_0/IC22_0/RTO24_1/MDQM0_0 bidirectional GPIO P0D with MFS4 RTS, base timer 3 TIOA, input captures IC12/IC22, MFT2 RTO24 and byte mask 0.
91 P0E/CTS4_0/TIOB3_2/IC13_0/IC23_0/RTO25_1/MDQM1_0 bidirectional GPIO P0E with MFS4 CTS, base timer 3 TIOB, input captures IC13/IC23, MFT2 RTO25 and byte mask 1.
92 P0F bidirectional GPIO P0F with non-maskable interrupt input, CR clock output, RTC output, sub clock output and MFT2 DTTI2X.
93 P63/INT03_0/SIN5_1/RX0_2/MWEX_0 bidirectional GPIO P63 with external interrupt 03, MFS5 SIN, CAN0 RX and external bus write enable for SRAM.
94 P62/SCK5_0/ADTG_3/TX0_2/MOEX_0 bidirectional GPIO P62 with MFS5 SCK/SCL, ADC trigger 3, CAN0 TX and external bus read enable for SRAM.
95 P61/SOT5_0/TIOB2_2/UHCONX bidirectional GPIO P61 with MFS5 SOT/SDA, base timer 2 TIOB and USB external pull-up control.
96 P60/SIN5_0/TIOA2_2/INT15_1/MRDY_0 bidirectional 5 V tolerant GPIO P60 with MFS5 SIN, base timer 2 TIOA, external interrupt 15 and external bus RDY input.
97 USBVCC power_in USB I/O power supply, 3.0 V to 3.6 V for USB use, 2.7 V to 5.5 V when P80/P81 are GPIO.
98 P80/UDM0 bidirectional GPIO P80 or USB device/host D- pin.
99 P81/UDP0 bidirectional GPIO P81 or USB device/host D+ pin.
100 VSS power_in Ground pin.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package LQFP-100(14x14)
Category Electronic Tools/Instruments/Consumables
Pins 100

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption 49
contacts tin Lead-Free Packaging CAUTION: When ball grid array (FBGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction 48

CAD (KiCad official)

  • Symbol: CY9BF516NPMC-G-JNE2
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: cy9bf516npmc-g-jne2-etched.step / cy9bf516npmc-g-jne2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy9bf516npmc-g-jne2.step / cy9bf516npmc-g-jne2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (118 pp, sha256 09ff325b377163c4, retrieved 2026-11-13, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF