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CY9BF121JPMC-G-JNE2

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Infineon Cypress Semicon Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY9BF121JPMC-G-JNE2

Infineon Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)

CY9BF121JPMC-G-JNE2 from Infineon Cypress Semicon, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P3A bidirectional General-purpose I/O port 3A, multiplexed with multi-function timer 0 RTO00/PPG00 output, multi-function serial 2 SCK2 (I2C SCL2), free-run timer, external interrupt INT07_0 and sub-clock/RTC outputs; the relocated function is selected via EPFR.
2 P3B bidirectional General-purpose I/O port 3B, multiplexed with multi-function timer 0 RTO01/PPG00 output, input capture IC00_0, base timer TIOA1_1 and multi-function serial 2 SOT2 (I2C SDA2).
3 P3C bidirectional General-purpose I/O port 3C, multiplexed with multi-function timer 0 RTO02/PPG02 output, input capture IC01_0, external interrupt INT18_2, base timer TIOA2_1 and multi-function serial 2 SIN2.
4 P3D bidirectional General-purpose I/O port 3D, multiplexed with multi-function timer 0 RTO03/PPG02 output, input capture IC02_0, base timer TIOA3_1, multi-function serial 5 SCK5 (I2C SCL5) and QPRC AIN1_0.
5 P3E bidirectional General-purpose I/O port 3E, multiplexed with multi-function timer 0 RTO04/PPG04 output, external interrupt INT19_2, base timer TIOA4_1, multi-function serial 5 SOT5 (I2C SDA5) and QPRC BIN1_0.
6 P3F bidirectional General-purpose I/O port 3F, multiplexed with multi-function timer 0 RTO05/PPG04 output, base timer TIOA5_1, multi-function serial 5 SIN5 and QPRC ZIN1_0.
7 VCC power_in Analog/digital power supply pin; the recommended supply range is 2.7 V to 5.5 V.
8 C passive Power supply stabilization capacitor pin; a smoothing capacitor CS of 1 to 10 μF is connected for the internal regulator.
9 VSS power_in Analog/digital ground pin, 0 V reference for the device.
10 PE2/X0 input Main clock (oscillation) input pin X0, also usable as general-purpose I/O port E2; main crystal of 4 MHz to 48 MHz is supported.
11 PE3/X1 bidirectional Main clock (oscillation) I/O pin X1, also usable as general-purpose I/O port E3; it is the return side of the main oscillator.
12 INITX input External reset input pin; a reset is applied when INITX is low ("L"), with a minimum reset input time of 500 ns.
13 P46/X0A bidirectional Sub clock (oscillation) input pin X0A, also usable as general-purpose I/O port 46 and multiplexed with DTTI0X_0 and external interrupt INT07_1; sub clock is 32.768 kHz when using a crystal.
14 P47/X1A bidirectional Sub clock (oscillation) I/O pin X1A, also usable as general-purpose I/O port 47 and multiplexed with external interrupt INT14_2.
15 MD0 input Mode 0 pin; during normal operation MD0 must be held low ("L"), and during serial programming to Flash memory MD0 must be held high ("H").
16 PE0/MD1 input Mode 1 pin; during serial programming to Flash memory MD1 must be held low ("L"); the pin is also usable as general-purpose I/O port E0.
17 P11 bidirectional General-purpose I/O port 1 (5 V tolerant), multiplexed with A/D analog input AN01, multi-function serial 1 SIN1, external interrupt INT02_1, free-run timer FRCK0_2 and QPRC AIN1_2.
18 P12 bidirectional General-purpose I/O port 1 (5 V tolerant), multiplexed with A/D analog input AN02, multi-function serial 1 SOT1 (I2C SDA1), base timer TIOA6_2, input capture IC00_2 and QPRC BIN1_2.
19 P13 bidirectional General-purpose I/O port 1 (5 V tolerant), multiplexed with A/D analog input AN03, multi-function serial 1 SCK1 (I2C SCL1), sub clock output SUBOUT_1, base timer TIOB6_2, input capture IC01_2, RTC output RTCCO_1 and QPRC ZIN1_2.
20 P14 bidirectional General-purpose I/O port 1 (5 V tolerant), multiplexed with A/D analog input AN04, multi-function serial 0 SIN0_1, external interrupt INT03_1, multi-function serial 0 SCK0 (I2C SCL0) and input capture IC02_2.
21 P15 bidirectional General-purpose I/O port 1 (5 V tolerant), multiplexed with A/D analog input AN05, multi-function serial 0 SOT0 (I2C SDA0), external interrupt INT14_0 and input capture IC03_2.
22 P23 bidirectional General-purpose I/O port 2 (5 V tolerant), multiplexed with A/D analog input AN12, multi-function serial 0 SCK0_0 (I2C SCL0), base timer TIOA7_1, DTTI0X_1 and QPRC AIN1_1.
23 P22 bidirectional General-purpose I/O port 2 (5 V tolerant), multiplexed with A/D analog input AN13, multi-function serial 0 SOT0_0 (I2C SDA0), base timer TIOB7_1 and QPRC ZIN1_1.
24 P21 bidirectional General-purpose I/O port 2 (5 V tolerant), multiplexed with A/D analog input AN14, multi-function serial 0 SIN0_0, external interrupt INT06_1 and QPRC BIN1_1.
25 VCC power_in Analog/digital power supply pin; the recommended supply range is 2.7 V to 5.5 V.
26 VSS power_in Analog/digital ground pin, 0 V reference for the device.
27 AVRL power_in A/D converter analog reference voltage low input; it must be at VSS (0 V).
28 AVRH power_in A/D converter analog reference voltage high input; the recommended range is 2.7 V to VCC.
29 P01/SWCLK bidirectional General-purpose I/O port 0, used as the serial wire debug interface clock input SWCLK.
30 P03/SWDIO bidirectional General-purpose I/O port 0, used as the serial wire debug interface data input/output SWDIO.
31 P04/SWO bidirectional General-purpose I/O port 0, used as the serial wire viewer output SWO.
32 P0F/NMIX bidirectional General-purpose I/O port 0, multiplexed with the non-maskable interrupt input NMIX, sub clock output SUBOUT_0, built-in high-speed CR clock output CROUT_1 and RTC output RTCCO_0.

Key specifications

Parameter Value
Manufacturer Infineon Cypress Semicon
Package LQFP-32(7x7)
Category Embedded Processors & Controllers
Pins 32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage (absolute maximum) VCC 6.5 V 38
Analog reference voltage (absolute maximum) AVRH 6.5 V 38
Clamp maximum current ICLAMP -2 2 mA Note *7 38
Clamp total maximum current Σ[ICLAMP] 20 mA Note *7 38
L level maximum output current IOL 10 mA 4 mA type 38
L level maximum output current IOL 20 mA 12 mA type 38
L level average output current IOLAV 4 mA 4 mA type 38
L level average output current IOLAV 12 mA 12 mA type 38
L level total maximum output current ΣIOL 100 mA 38
L level total average output current ΣIOLAV 50 mA 38
H level maximum output current IOH -10 mA 4 mA type 38
H level maximum output current IOH -20 mA 12 mA type 38
H level average output current IOHAV -4 mA 4 mA type 38
H level average output current IOHAV -12 mA 12 mA type 38
H level total maximum output current ΣIOH -100 mA 38
H level total average output current ΣIOHAV -50 mA 38
Power consumption PD 350 mW 38
Storage temperature TSTG -55 150 °C 38
Power supply voltage (recommended) VCC 2.7 5.5 V 40
Analog reference voltage (recommended) AVRH 2.7 V 40
Smoothing capacitor for regulator CS 1 10 μF For regulator (note *1) 40
Operating temperature TA -40 105 °C When mounted on four-layer PCB 40
Operating temperature TA -40 85 °C When mounted on double-sided single-layer PCB 40
Input leak current IIL -5 5 μA 43
Pull-up resistance value RPU 33 50 90 kΩ Pull-up pin, VCC ≥ 4.5 V 43
Pull-up resistance value RPU 180 kΩ VCC < 4.5 V 43
Input capacitance CIN 5 15 pF Other than VCC, VSS, AVRH, AVRL 43
Run mode current, PLL ICC 27 35 mA CPU 72 MHz, peripheral 36 MHz, instruction on Flash; *1, *5 41
Run mode current, High-speed CR ICC 2.2 3.1 mA CPU/peripheral 4 MHz, instruction on Flash; *1, *2 41
Run mode current, Low-speed CR ICC 105 930 μA CPU/peripheral 100 kHz, instruction on Flash; *1 41
Sleep mode current, PLL ICCS 17 20 mA Peripheral 36 MHz; *1, *5 41
Sleep mode current, High-speed CR ICCS 1.3 2.2 mA Peripheral 4 MHz; *1, *2 41
Timer mode current, Main ICCT 3.5 4.1 mA TA = +25°C, LVD off; *1 42
Timer mode current, Sub ICCT 15 45 μA TA = +25°C, LVD off; *1 42
RTC mode current ICCR 13 39 μA TA = +25°C, LVD off; *1 42
Stop mode current ICCH 12 33 μA TA = +25°C, LVD off; *1 42
Flash memory write/erase current ICCFLASH 9.5 11.2 mA At write/erase 42
A/D converter power supply current ICCAD 0.7 0.9 mA At operation 42
Reference power supply current ICCAVRH 1.1 1.97 mA At operation, AVRH = 5.5 V 42
LVD power supply current ICCLVD 0.13 0.3 μA VCC = 5.5 V, at operation for reset, at not detect 42
Input frequency, crystal fCH 4 48 MHz Crystal oscillator connected, VCC ≥ 4.5 V 44
Input frequency, crystal fCH 4 20 MHz Crystal oscillator connected, VCC < 4.5 V 44
Input frequency, external clock fCH 4 48 MHz When using external clock 44
Input clock cycle tCYLH 20.83 250 ns When using external clock 44
Internal master clock frequency fCM 72 MHz 44
Sub clock input clock cycle tCYLL 10 31.25 μs When using external clock 45
Built-in High-speed CR clock frequency fCRH 3.88 4 4.12 MHz TA = -40°C to +105°C, 3.6 V < VCC ≤ 5.5 V, when trimming 46
Built-in High-speed CR clock frequency fCRH 2.8 4 5.2 MHz TA = -40°C to +105°C, when not trimming 46
Frequency stabilization time tCRWT 30 μs Time from trim value setting to stable High-speed CR frequency; *2 46
Built-in Low-speed CR clock frequency fCRL 50 100 150 kHz 46
PLL input clock frequency (main clock input) fPLLI 4 16 MHz Main clock used as Main PLL input 47
PLL oscillation stabilization wait time (lock-up time) tLOCK 100 μs Main clock used as Main PLL input 47
Reset input time tINITX 500 ns 48
Power supply shut down time tOFF 1 ms VCC held below 0.2 V 48
Power ramp rate dV/dt 1.2 1000 mV/μs VCC 0.2 V to 2.70 V 48
Time until releasing power-on reset tPRT 0.34 3.15 ms 48
Integral nonlinearity -4.5 3 4.5 LSB AVRH = 2.7 V to 5.5 V 63
Differential nonlinearity -3.5 2.5 3.5 LSB AVRH = 2.7 V to 5.5 V 63
Sampling time tS 0.3 10 μs Depends on external impedance 63

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing abs Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of 25
contacts tin Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength 25

CAD (KiCad official)

  • Symbol: CY9BF121JPMC-G-JNE2
  • Footprint: Package_QFP:LQFP-32_7x7mm_P0.8mm
  • 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
  • 3D model files: cy9bf121jpmc-g-jne2-etched.step / cy9bf121jpmc-g-jne2-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy9bf121jpmc-g-jne2.step / cy9bf121jpmc-g-jne2.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Cypress Semicon datasheet (79 pp, sha256 bbf814d761ffaaf9, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF