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CY9AF314NAPMC-GNE2
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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownCY9AF314NAPMC-GNE2
Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)
CY9AF314NAPMC-GNE2 from Cypress Semicon, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VCC | power_in | Power supply pin; Vcc is 2.7 V to 5.5 V under the recommended operating conditions. |
| 2 | P50/INT00_0/AIN0_2/SIN3_1/RTO10_0/MADATA00_1 | bidirectional | General-purpose I/O port 5 with per-pin pull-up control; alternate functions INT00_0, AIN0_2, SIN3_1, RTO10_0 and MADATA00_1 (relocated functions selected via EPFR). |
| 3 | P51/INT01_0/BIN0_2/SOT3_1/RTO11_0/MADATA01_1 | bidirectional | General-purpose I/O port 5 with per-pin pull-up control; alternate functions INT01_0, BIN0_2, SOT3_1, RTO11_0 and MADATA01_1 (relocated functions selected via EPFR). |
| 4 | P52/INT02_0/ZIN0_2/SCK3_1/RTO12_0/MADATA02_1 | bidirectional | General-purpose I/O port 5 with per-pin pull-up control; alternate functions INT02_0, ZIN0_2, SCK3_1, RTO12_0 and MADATA02_1 (relocated functions selected via EPFR). |
| 5 | P53/SIN6_0/TIOA1_2/INT07_2/RTO13_0/MADATA03_1 | bidirectional | General-purpose I/O port 5 with per-pin pull-up control; alternate functions SIN6_0, TIOA1_2, INT07_2, RTO13_0 and MADATA03_1 (relocated functions selected via EPFR). |
| 6 | P54/SOT6_0/TIOB1_2/RTO14_0/MADATA04_1 | bidirectional | General-purpose I/O port 5 with per-pin pull-up control; alternate functions SOT6_0, TIOB1_2, RTO14_0 and MADATA04_1 (relocated functions selected via EPFR). |
| 7 | P55/SCK6_0/ADTG_1/RTO15_0/MADATA05_1 | bidirectional | General-purpose I/O port 5 with per-pin pull-up control; alternate functions SCK6_0, ADTG_1, RTO15_0 and MADATA05_1 (relocated functions selected via EPFR). |
| 8 | P56/INT08_2/DTTI1X_0/MADATA06_1 | bidirectional | General-purpose I/O port 5 with per-pin pull-up control; alternate functions INT08_2, DTTI1X_0 and MADATA06_1 (relocated functions selected via EPFR). |
| 9 | P30/AIN0_0/TIOB0_1/INT03_2/MADATA07_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions AIN0_0, TIOB0_1, INT03_2 and MADATA07_1 (relocated functions selected via EPFR). |
| 10 | P31/BIN0_0/TIOB1_1/SCK6_1/INT04_2/MADATA08_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions BIN0_0, TIOB1_1, SCK6_1, INT04_2 and MADATA08_1 (relocated functions selected via EPFR). |
| 11 | P32/ZIN0_0/TIOB2_1/SOT6_1/INT05_2/MADATA09_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions ZIN0_0, TIOB2_1, SOT6_1, INT05_2 and MADATA09_1 (relocated functions selected via EPFR). |
| 12 | P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/MADATA10_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions INT04_0, TIOB3_1, SIN6_1, ADTG_6 and MADATA10_1 (relocated functions selected via EPFR). |
| 13 | P34/FRCK0_0/TIOB4_1/MADATA11_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions FRCK0_0, TIOB4_1 and MADATA11_1 (relocated functions selected via EPFR). |
| 14 | P35/IC03_0/TIOB5_1/INT08_1/MADATA12_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions IC03_0, TIOB5_1, INT08_1 and MADATA12_1 (relocated functions selected via EPFR). |
| 15 | P36/IC02_0/SIN5_2/INT09_1/MADATA13_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions IC02_0, SIN5_2, INT09_1 and MADATA13_1 (relocated functions selected via EPFR). |
| 16 | P37/IC01_0/SOT5_2/INT10_1/MADATA14_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions IC01_0, SOT5_2, INT10_1 and MADATA14_1 (relocated functions selected via EPFR). |
| 17 | P38/IC00_0/SCK5_2/INT11_1/MADATA15_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions IC00_0, SCK5_2, INT11_1 and MADATA15_1 (relocated functions selected via EPFR). |
| 18 | P39/DTTI0X_0/ADTG_2 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions DTTI0X_0 and ADTG_2 (relocated functions selected via EPFR). |
| 19 | P3A/RTO00_0/TIOA0_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions RTO00_0 (PPG00_0 in PPG output modes) and TIOA0_1 (relocated functions selected via EPFR). |
| 20 | P3B/RTO01_0/TIOA1_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions RTO01_0 (PPG00_0 in PPG output modes) and TIOA1_1 (relocated functions selected via EPFR). |
| 21 | P3C/RTO02_0/TIOA2_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions RTO02_0 (PPG02_0 in PPG output modes) and TIOA2_1 (relocated functions selected via EPFR). |
| 22 | P3D/RTO03_0/TIOA3_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions RTO03_0 (PPG02_0 in PPG output modes) and TIOA3_1 (relocated functions selected via EPFR). |
| 23 | P3E/RTO04_0/TIOA4_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions RTO04_0 (PPG04_0 in PPG output modes) and TIOA4_1 (relocated functions selected via EPFR). |
| 24 | P3F/RTO05_0/TIOA5_1 | bidirectional | General-purpose I/O port 3 with per-pin pull-up control; alternate functions RTO05_0 (PPG04_0 in PPG output modes) and TIOA5_1 (relocated functions selected via EPFR). |
| 25 | VSS | power_in | Ground (0 V) reference pin. |
| 26 | VCC | power_in | Power supply pin; Vcc is 2.7 V to 5.5 V under the recommended operating conditions. |
| 27 | P40/TIOA0_0/RTO10_1/INT12_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control; alternate functions TIOA0_0, RTO10_1 (PPG10_1 in PPG output modes) and INT12_1 (relocated functions selected via EPFR). |
| 28 | P41/TIOA1_0/RTO11_1/INT13_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control; alternate functions TIOA1_0, RTO11_1 (PPG10_1 in PPG output modes) and INT13_1 (relocated functions selected via EPFR). |
| 29 | P42/TIOA2_0/RTO12_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control; alternate functions TIOA2_0 and RTO12_1 (PPG12_1 in PPG output modes) (relocated functions selected via EPFR). |
| 30 | P43/TIOA3_0/RTO13_1/ADTG_7 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control; alternate functions TIOA3_0, RTO13_1 (PPG12_1 in PPG output modes) and ADTG_7 (relocated functions selected via EPFR). |
| 31 | P44/TIOA4_0/RTO14_1/MAD00_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control; alternate functions TIOA4_0, RTO14_1 (PPG14_1 in PPG output modes) and MAD00_1 (relocated functions selected via EPFR). |
| 32 | P45/TIOA5_0/RTO15_1/MAD01_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control; alternate functions TIOA5_0, RTO15_1 (PPG14_1 in PPG output modes) and MAD01_1 (relocated functions selected via EPFR). |
| 33 | C | passive | Power stabilization capacitor pin; connect a smoothing capacitor CS of 1 μF to 10 μF for the built-in regulator. |
| 34 | VSS | power_in | Ground (0 V) reference pin. |
| 35 | VCC | power_in | Power supply pin; Vcc is 2.7 V to 5.5 V under the recommended operating conditions. |
| 36 | P46/X0A | input | Sub clock (oscillation) input pin X0A, also general-purpose I/O port 4 pin P46. |
| 37 | P47/X1A | bidirectional | Sub clock (oscillation) I/O pin X1A, also general-purpose I/O port 4 pin P47. |
| 38 | INITX | input | External reset input; a reset is valid when INITX is Low. |
| 39 | P48/DTTI1X_1/INT14_1/SIN3_2/MAD02_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control; alternate functions DTTI1X_1, INT14_1, SIN3_2 and MAD02_1 (relocated functions selected via EPFR). |
| 40 | P49/TIOB0_0/IC10_1/AIN0_1/SOT3_2/MAD03_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control; alternate functions TIOB0_0, IC10_1, AIN0_1, SOT3_2 and MAD03_1 (relocated functions selected via EPFR). |
| 41 | P4A/TIOB1_0/IC11_1/BIN0_1/SCK3_2/MAD04_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control; alternate functions TIOB1_0, IC11_1, BIN0_1, SCK3_2 and MAD04_1 (relocated functions selected via EPFR). |
| 42 | P4B/TIOB2_0/IC12_1/ZIN0_1/MAD05_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control; alternate functions TIOB2_0, IC12_1, ZIN0_1 and MAD05_1 (relocated functions selected via EPFR). |
| 43 | P4C/TIOB3_0/IC13_1/SCK7_1/AIN1_2/MAD06_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control, 5 V tolerant only on CY9AF315MA/NA and CY9AF316MA/NA; alternate functions TIOB3_0, IC13_1, SCK7_1, AIN1_2 and MAD06_1. |
| 44 | P4D/TIOB4_0/FRCK1_1/SOT7_1/BIN1_2/MAD07_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control, 5 V tolerant only on CY9AF315MA/NA and CY9AF316MA/NA; alternate functions TIOB4_0, FRCK1_1, SOT7_1, BIN1_2 and MAD07_1. |
| 45 | P4E/TIOB5_0/INT06_2/SIN7_1/ZIN1_2/MAD08_1 | bidirectional | General-purpose I/O port 4 with per-pin pull-up control, 5 V tolerant only on CY9AF315MA/NA and CY9AF316MA/NA; alternate functions TIOB5_0, INT06_2, SIN7_1, ZIN1_2 and MAD08_1. |
| 46 | PE0/MD1 | input | Mode 1 pin; MD1 must be Low during serial programming to flash memory. |
| 47 | MD0 | input | Mode 0 pin; MD0 must be Low during normal operation and High during serial programming to flash memory. |
| 48 | PE2/X0 | input | Main clock (oscillation) input pin X0, also general-purpose I/O port E pin PE2. |
| 49 | PE3/X1 | bidirectional | Main clock (oscillation) I/O pin X1, also general-purpose I/O port E pin PE3. |
| 50 | VSS | power_in | Ground (0 V) reference pin. |
| 51 | VCC | power_in | Power supply pin; Vcc is 2.7 V to 5.5 V under the recommended operating conditions. |
| 52 | P10/AN00 | bidirectional | General-purpose I/O port 1 also serving 12-bit A/D converter analog input AN00. |
| 53 | P11/AN01/SIN1_1/INT02_1/FRCK0_2/MAD09_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN01 and alternate functions SIN1_1, INT02_1, FRCK0_2 and MAD09_1 (relocated functions selected via EPFR). |
| 54 | P12/AN02/SOT1_1/IC00_2/MAD10_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN02 and alternate functions SOT1_1, IC00_2 and MAD10_1 (relocated functions selected via EPFR). |
| 55 | P13/AN03/SCK1_1/IC01_2/MAD11_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN03 and alternate functions SCK1_1, IC01_2 and MAD11_1 (relocated functions selected via EPFR). |
| 56 | P14/AN04/SIN0_1/INT03_1/IC02_2/MAD12_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN04 and alternate functions SIN0_1, INT03_1, IC02_2 and MAD12_1 (relocated functions selected via EPFR). |
| 57 | P15/AN05/SOT0_1/IC03_2/MAD13_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN05 and alternate functions SOT0_1, IC03_2 and MAD13_1 (relocated functions selected via EPFR). |
| 58 | P16/AN06/SCK0_1/MAD14_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN06 and alternate functions SCK0_1 and MAD14_1 (relocated functions selected via EPFR). |
| 59 | P17/AN07/SIN2_2/INT04_1/MAD15_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN07 and alternate functions SIN2_2, INT04_1 and MAD15_1 (relocated functions selected via EPFR). |
| 60 | AVCC | power_in | A/D converter analog power supply pin; AVcc equals Vcc and is 2.7 V to 5.5 V. |
| 61 | AVRH | input | A/D converter analog reference voltage input pin; AVRH is 2.7 V to AVcc. |
| 62 | AVSS | power_in | A/D converter analog ground pin. |
| 63 | P18/AN08/SOT2_2/MAD16_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN08 and alternate functions SOT2_2 and MAD16_1 (relocated functions selected via EPFR). |
| 64 | P19/AN09/SCK2_2/MAD17_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN09 and alternate functions SCK2_2 and MAD17_1 (relocated functions selected via EPFR). |
| 65 | P1A/AN10/SIN4_1/INT05_1/IC00_1/MAD18_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN10 and alternate functions SIN4_1, INT05_1, IC00_1 and MAD18_1 (relocated functions selected via EPFR). |
| 66 | P1B/AN11/SOT4_1/IC01_1/MAD19_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN11 and alternate functions SOT4_1, IC01_1 and MAD19_1 (relocated functions selected via EPFR). |
| 67 | P1C/AN12/SCK4_1/IC02_1/MAD20_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN12 and alternate functions SCK4_1, IC02_1 and MAD20_1 (relocated functions selected via EPFR). |
| 68 | P1D/AN13/CTS4_1/IC03_1/MAD21_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN13 and alternate functions CTS4_1, IC03_1 and MAD21_1 (relocated functions selected via EPFR). |
| 69 | P1E/AN14/RTS4_1/DTTI0X_1/MAD22_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN14 and alternate functions RTS4_1, DTTI0X_1 and MAD22_1 (relocated functions selected via EPFR). |
| 70 | P1F/AN15/ADTG_5/FRCK0_1/MAD23_1 | bidirectional | General-purpose I/O port 1 with per-pin pull-up control; A/D analog input AN15 and alternate functions ADTG_5, FRCK0_1 and MAD23_1 (relocated functions selected via EPFR). |
| 71 | P23/SCK0_0/TIOA7_1/RTO00_1 | bidirectional | General-purpose I/O port 2 with per-pin pull-up control; alternate functions SCK0_0, TIOA7_1 and RTO00_1 (PPG00_1 in PPG output modes) (relocated functions selected via EPFR). |
| 72 | P22/SOT0_0/TIOB7_1/ZIN1_1 | bidirectional | General-purpose I/O port 2 with per-pin pull-up control; alternate functions SOT0_0, TIOB7_1 and ZIN1_1 (relocated functions selected via EPFR). |
| 73 | P21/SIN0_0/INT06_1/BIN1_1 | bidirectional | General-purpose I/O port 2 with per-pin pull-up control; alternate functions SIN0_0, INT06_1 and BIN1_1 (relocated functions selected via EPFR). |
| 74 | P20/INT05_0/CROUT_0/AIN1_1/MAD24_1 | bidirectional | General-purpose I/O port 2 with per-pin pull-up control; alternate functions INT05_0, CROUT_0, AIN1_1 and MAD24_1 (relocated functions selected via EPFR). |
| 75 | VSS | power_in | Ground (0 V) reference pin. |
| 76 | VCC | power_in | Power supply pin; Vcc is 2.7 V to 5.5 V under the recommended operating conditions. |
| 77 | P00/TRSTX/MCSX7_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; JTAG test reset input TRSTX and external bus chip select MCSX7_1. |
| 78 | P01/TCK/SWCLK | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; JTAG test clock input TCK, which is also the serial wire debug clock SWCLK. |
| 79 | P02/TDI/MCSX6_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; JTAG test data input TDI and external bus chip select MCSX6_1. |
| 80 | P03/TMS/SWDIO | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; JTAG test mode state input/output TMS, which is also the serial wire data I/O SWDIO. |
| 81 | P04/TDO/SWO | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; JTAG debug data output TDO, which is also the serial wire viewer output SWO. |
| 82 | P05/TRACED0/TIOA5_2/SIN4_2/INT00_1/MCSX5_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; ETM trace data output TRACED0 and alternate functions TIOA5_2, SIN4_2, INT00_1 and MCSX5_1 (relocated functions selected via EPFR). |
| 83 | P06/TRACED1/TIOB5_2/SOT4_2/INT01_1/MCSX4_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; ETM trace data output TRACED1 and alternate functions TIOB5_2, SOT4_2, INT01_1 and MCSX4_1 (relocated functions selected via EPFR). |
| 84 | P07/TRACED2/ADTG_0/SCK4_2/MCLKOUT_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; ETM trace data output TRACED2 and alternate functions ADTG_0, SCK4_2 and MCLKOUT_1 (external bus clock output). |
| 85 | P08/TRACED3/TIOA0_2/CTS4_2/MCSX3_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; ETM trace data output TRACED3 and alternate functions TIOA0_2, CTS4_2 and MCSX3_1 (relocated functions selected via EPFR). |
| 86 | P09/TRACECLK/TIOB0_2/RTS4_2/MCSX2_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; ETM trace clock output TRACECLK and alternate functions TIOB0_2, RTS4_2 and MCSX2_1 (relocated functions selected via EPFR). |
| 87 | P0A/SIN4_0/INT00_2/FRCK1_0/MCSX1_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control, 5 V tolerant only on CY9AF315MA/NA and CY9AF316MA/NA; alternate functions SIN4_0, INT00_2, FRCK1_0 and MCSX1_1. |
| 88 | P0B/SOT4_0/TIOB6_1/IC10_0/MCSX0_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control, 5 V tolerant only on CY9AF315MA/NA and CY9AF316MA/NA; alternate functions SOT4_0, TIOB6_1, IC10_0 and MCSX0_1. |
| 89 | P0C/SCK4_0/TIOA6_1/IC11_0/MALE_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control, 5 V tolerant only on CY9AF315MA/NA and CY9AF316MA/NA; alternate functions SCK4_0, TIOA6_1, IC11_0 and MALE_1 (address latch enable). |
| 90 | P0D/RTS4_0/TIOA3_2/IC12_0/MDQM0_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; alternate functions RTS4_0, TIOA3_2, IC12_0 and MDQM0_1 (external bus byte mask output). |
| 91 | P0E/CTS4_0/TIOB3_2/IC13_0/MDQM1_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; alternate functions CTS4_0, TIOB3_2, IC13_0 and MDQM1_1 (external bus byte mask output). |
| 92 | P0F/NMIX/CROUT_1 | bidirectional | General-purpose I/O port 0 with per-pin pull-up control; non-maskable interrupt input NMIX and built-in high-speed CR clock output CROUT_1. |
| 93 | P63/INT03_0/MWEX_1 | bidirectional | General-purpose I/O port 6 with per-pin pull-up control; external interrupt request input INT03_0 and external bus write enable output MWEX_1 for SRAM. |
| 94 | P62/SCK5_0/ADTG_3/MOEX_1 | bidirectional | General-purpose I/O port 6 with per-pin pull-up control; alternate functions SCK5_0, ADTG_3 and MOEX_1 (external bus read enable output for SRAM). |
| 95 | P61/SOT5_0/TIOB2_2/UHCONX | bidirectional | General-purpose I/O port 6 with per-pin pull-up control; alternate functions SOT5_0, TIOB2_2 and UHCONX (USB external pull-up control). |
| 96 | P60/SIN5_0/TIOA2_2/INT15_1/MRDY_1 | bidirectional | General-purpose I/O port 6 with per-pin pull-up control, 5 V tolerant only on CY9AF315MA/NA and CY9AF316MA/NA; alternate functions SIN5_0, TIOA2_2, INT15_1 and MRDY_1 (external RDY input). |
| 97 | USBVCC | power_in | 3.3 V power supply for USB I/O: USBVcc is 3.0 V to 3.6 V when USB is used, and 2.7 V to 5.5 V when the pin is used as GPIO. |
| 98 | P80/UDM0 | bidirectional | General-purpose I/O port 8 pin P80, also USB Device/Host D- pin UDM0. |
| 99 | P81/UDP0 | bidirectional | General-purpose I/O port 8 pin P81, also USB Device/Host D+ pin UDP0. |
| 100 | VSS | power_in | Ground (0 V) reference pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | LQFP-100(14x14) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 100 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage | Vcc | 2.7 | 5.5 | V | 62 | ||
| Power supply voltage (3V power supply) for USB | USBVcc | 3 | 3.6 | V | When P81/UDP0 and P80/UDM0 are used as USB (UDP0, UDM0) | 62 | |
| Power supply voltage for USB (GPIO use) | USBVcc | 2.7 | 5.5 | V | When P81/UDP0 and P80/UDM0 are used as GPIO (P81, P80); max ≤ Vcc | 62 | |
| Analog power supply voltage | AVcc | 2.7 | 5.5 | V | AVcc = Vcc | 62 | |
| Analog reference voltage | AVRH | 2.7 | V | Max printed as AVcc | 62 | ||
| Smoothing capacitor | CS | 1 | 10 | μF | For built-in regulator | 62 | |
| Operating temperature | TA | -40 | 105 | °C | LQI100 package | 62 | |
| Power supply voltage | Vcc | -0.5 | 6.5 | V | Vss = 0.0 V (Vss - 0.5 to Vss + 6.5) | 60 | |
| Power supply voltage (for USB) | USBVcc | -0.5 | 6.5 | V | Vss = 0.0 V | 60 | |
| Analog power supply voltage | AVcc | -0.5 | 6.5 | V | Vss = 0.0 V | 60 | |
| Analog reference voltage | AVRH | -0.5 | 6.5 | V | Vss = 0.0 V | 60 | |
| L level maximum output current (4 mA type) | IOL | 10 | mA | 4 mA type | 60 | ||
| L level maximum output current (12 mA type) | IOL | 20 | mA | 12 mA type | 60 | ||
| L level maximum output current (P80, P81) | IOL | 39 | mA | P80, P81 | 60 | ||
| H level maximum output current (4 mA type) | IOH | -10 | mA | 4 mA type | 60 | ||
| H level maximum output current (12 mA type) | IOH | -20 | mA | 12 mA type | 60 | ||
| H level maximum output current (P80, P81) | IOH | -39 | mA | P80, P81 | 60 | ||
| L level total maximum output current | ∑IOL | 100 | mA | 60 | |||
| H level total maximum output current | ∑IOH | -100 | mA | 60 | |||
| Power consumption | PD | 300 | mW | 60 | |||
| Storage temperature | TSTG | -55 | 150 | °C | 60 | ||
| RUN mode current (PLL, Flash 0 wait) | Icc | 32 | 41 | mA | CPU 40 MHz, Peripheral 40 MHz, Flash 0 wait, PLL RUN mode | 63 | |
| RUN mode current (PLL, Flash 3 wait) | Icc | 21 | 28 | mA | CPU 40 MHz, Peripheral 40 MHz, Flash 3 wait, PLL RUN mode | 63 | |
| RUN mode current (High-speed CR) | Icc | 3.9 | 7.7 | mA | CPU/Peripheral 4 MHz, Flash 0 wait | 63 | |
| RUN mode current (Sub) | Icc | 0.15 | 3.2 | mA | CPU/Peripheral 32 kHz, Flash 0 wait | 63 | |
| RUN mode current (Low-speed CR) | Icc | 0.2 | 3.3 | mA | CPU/Peripheral 100 kHz, Flash 0 wait | 63 | |
| SLEEP mode current (PLL) | Iccs | 10 | 15 | mA | Peripheral 40 MHz, PLL SLEEP mode | 63 | |
| SLEEP mode current (High-speed CR) | Iccs | 1.2 | 4.4 | mA | Peripheral 4 MHz | 63 | |
| SLEEP mode current (Sub) | Iccs | 0.1 | 3.1 | mA | Peripheral 32 kHz | 63 | |
| SLEEP mode current (Low-speed CR) | Iccs | 0.1 | 3.1 | mA | Peripheral 100 kHz | 63 | |
| TIMER mode current (Main) | ICCT | 2.5 | 3 | mA | TA = +25°C, LVD off, 4 MHz crystal | 64 | |
| TIMER mode current (Main) | ICCT | 6 | mA | TA = +105°C, LVD off, 4 MHz crystal | 64 | ||
| TIMER mode current (Sub) | ICCT | 60 | 230 | μA | TA = +25°C, LVD off, 32 kHz crystal | 64 | |
| TIMER mode current (Sub) | ICCT | 3.1 | mA | TA = +105°C, LVD off, 32 kHz crystal | 64 | ||
| STOP mode current | ICCH | 35 | 200 | μA | TA = +25°C, LVD off | 64 | |
| STOP mode current | ICCH | 3 | mA | TA = +105°C, LVD off | 64 | ||
| Low-voltage detection circuit power supply current | ICCLVD | 4 | 7 | μA | VCC = 5.5 V, at operation for interrupt | 64 | |
| Flash memory write/erase current | ICCFLASH | 11.4 | 13.1 | mA | At write/erase | 64 | |
| A/D converter power supply current | ICCAD | 0.57 | 0.72 | mA | AVCC, at 1 unit operation | 64 | |
| A/D converter power supply current at stop | ICCAD | 0.06 | 20 | μA | AVCC, at stop | 64 | |
| A/D reference power supply current | ICCAVRH | 1.1 | 1.96 | mA | AVRH at 1 unit operation, AVRH = 5.5 V | 64 | |
| A/D reference power supply current at stop | ICCAVRH | 0.06 | 4 | μA | AVRH, at stop | 64 | |
| "L" level input voltage (hysteresis input) | VILS | -0.3 | V | CMOS hysteresis input pin, MD0, MD1; Vss = 0.0 V | 65 | ||
| "H" level input voltage (5V tolerant I/O) | VIHS | 5.5 | V | 5V tolerant I/O pin; Vss + 5.5 V | 65 | ||
| Input leak current | IIL | -5 | 5 | μA | 65 | ||
| Pull-up resistor value | RPU | 25 | 50 | 100 | kΩ | Pull-up pin, Vcc ≥ 4.5 V | 65 |
| Pull-up resistor value | RPU | 30 | 80 | 200 | kΩ | Pull-up pin, Vcc < 4.5 V | 65 |
| Input capacitance | CIN | 5 | 15 | pF | Other than Vcc, Vss, AVcc, AVss, AVRH | 65 | |
| Input frequency (crystal oscillator) | FCH | 4 | 48 | MHz | Vcc ≥ 4.5 V, when crystal oscillator is connected | 66 | |
| Input frequency (crystal oscillator) | FCH | 4 | 20 | MHz | Vcc < 4.5 V, when crystal oscillator is connected | 66 | |
| Input frequency (external clock) | FCL | 32 | 100 | kHz | When using external clock (X0A) | 67 | |
| Clock frequency (built-in high-speed CR, trimmed) | FCRH | 3.8 | 4 | 4.2 | MHz | TA = -40°C to +105°C, when trimming | 67 |
| Clock frequency (built-in low-speed CR) | FCRL | 50 | 100 | 150 | kHz | 67 | |
| Reset input time | tINITX | 500 | ns | 69 | |||
| Integral nonlinearity | -4.5 | 1.7 | 4.5 | LSB | AVRH = 2.7 V to 5.5 V | 92 | |
| Differential nonlinearity | -2.5 | 1.7 | 2.5 | LSB | 92 | ||
| Zero transition voltage | VZT | -15 | 8 | 15 | mV | ANxx | 92 |
| Interchannel disparity | 4 | LSB | 92 | ||||
| Analog port input leak current | 5 | μA | ANxx | 92 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | abs | Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of | 47 | |
| contacts | tin | Lead-Free Packaging CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength | 47 |
CAD (KiCad official)
- Symbol:
CY9AF314NAPMC-GNE2 - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
cy9af314napmc-gne2-etched.step/cy9af314napmc-gne2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy9af314napmc-gne2.step/cy9af314napmc-gne2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Cypress Semicon datasheet (117 pp, sha256
b6290af955d0d298, retrieved 2026-10-28, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).