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CY8C5868AXI-LP035

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Cypress Semicon CYPRESS, TQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY8C5868AXI-LP035

Cypress Semicon · CYPRESS · TQFP-100(14x14)

CY8C5868AXI-LP035 from Cypress Semicon, in a TQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2[5] bidirectional GPIO on port 2 (TRACEDATA[1] alternate), powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
2 P2[6] bidirectional GPIO on port 2 (TRACEDATA[2] alternate), powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
3 P2[7] bidirectional GPIO on port 2 (TRACEDATA[3] alternate), powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
4 P12[4] bidirectional SIO (I2C0 SCL alternate) powered from VDDIO2; SIO sink current is 25 mA and the pin is high-impedance when the device is unpowered.
5 P12[5] bidirectional SIO (I2C0 SDA alternate) powered from VDDIO2; SIO sink current is 25 mA and the pin is high-impedance when the device is unpowered.
6 P6[4] bidirectional GPIO on port 6 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
7 P6[5] bidirectional GPIO on port 6 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
8 P6[6] bidirectional GPIO on port 6 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
9 P6[7] bidirectional GPIO on port 6 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
10 VSSB power_in Ground connection for the boost pump.
11 IND passive Inductor connection to the boost pump.
12 VBOOST power_out Boost pump output and power-sense connection; the boost output can power other devices in the application.
13 VBAT power_in Battery supply to the boost pump; the boost converter can power the device from supply voltages as low as 0.5 V.
14 VSSD power_in Ground for all digital logic and I/O pins.
15 XRES input External reset, active low with internal pull-up.
16 P5[0] bidirectional GPIO on port 5 powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
17 P5[1] bidirectional GPIO on port 5 powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
18 P5[2] bidirectional GPIO on port 5 powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
19 P5[3] bidirectional GPIO on port 5 powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
20 P1[0] bidirectional GPIO on port 1 (TMS/SWDIO alternate) powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
21 P1[1] bidirectional GPIO on port 1 (TCK/SWDCK alternate) powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
22 P1[2] bidirectional GPIO on port 1 powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
23 P1[3] bidirectional GPIO on port 1 (TDO/SWV alternate) powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
24 P1[4] bidirectional GPIO on port 1 (TDI alternate) powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
25 P1[5] bidirectional GPIO on port 1 (NTRST alternate) powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
26 VDDIO1 power_in Supply for the port 1, port 5 and P12[7:6] I/O pins; must be 1.71 V to 5.5 V and less than or equal to VDDA.
27 P1[6] bidirectional GPIO on port 1 powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
28 P1[7] bidirectional GPIO on port 1 powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
29 P12[6] bidirectional SIO powered from VDDIO1; SIO sink current is 25 mA and the pin is high-impedance when the device is unpowered.
30 P12[7] bidirectional SIO powered from VDDIO1; SIO sink current is 25 mA and the pin is high-impedance when the device is unpowered.
31 P5[4] bidirectional GPIO on port 5 powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
32 P5[5] bidirectional GPIO on port 5 powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
33 P5[6] bidirectional GPIO on port 5 powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
34 P5[7] bidirectional GPIO on port 5 powered from VDDIO1; overvoltage input must be limited to 100 µA with a series resistor.
35 P15[6] bidirectional USBIO D+ connection to the USB 2.0 bus; powered from VDDD rather than a VDDIO and usable as a digital I/O when USB is not used.
36 P15[7] bidirectional USBIO D- connection to the USB 2.0 bus; powered from VDDD rather than a VDDIO and usable as a digital I/O when USB is not used.
37 VDDD power_in Supply for all digital peripherals and the digital core regulator; must be less than or equal to VDDA.
38 VSSD power_in Ground for all digital logic and I/O pins.
39 VCCD power_out Output of the digital core regulator (or input in external regulated mode); must be shorted to the other VCCD pin with a 1 µF capacitor to VSSD.
40 NC unconnected No connection.
41 NC unconnected No connection.
42 P15[0] passive 4 to 25 MHz crystal oscillator output pin (XO), also GPIO on port 15 powered from VDDIO3.
43 P15[1] passive 4 to 25 MHz crystal oscillator input pin (XI), also GPIO on port 15 powered from VDDIO3.
44 P3[0] bidirectional GPIO on port 3 with high-current IDAC1 output, powered from VDDIO3; overvoltage input must be limited to 100 µA with a series resistor.
45 P3[1] bidirectional GPIO on port 3 with high-current IDAC3 output, powered from VDDIO3; overvoltage input must be limited to 100 µA with a series resistor.
46 P3[2] bidirectional GPIO on port 3 with inverting input to uncommitted opamp 3 and external reference 1, powered from VDDIO3; overvoltage input must be limited to 100 µA.
47 P3[3] bidirectional GPIO on port 3 with non-inverting input to uncommitted opamp 3, powered from VDDIO3; overvoltage input must be limited to 100 µA.
48 P3[4] bidirectional GPIO on port 3 with inverting input to uncommitted opamp 1, powered from VDDIO3; overvoltage input must be limited to 100 µA.
49 P3[5] bidirectional GPIO on port 3 with non-inverting input to uncommitted opamp 1, powered from VDDIO3; overvoltage input must be limited to 100 µA.
50 VDDIO3 power_in Supply for the port 3, P12[1:0] and P15[3:0] I/O pins; must be 1.71 V to 5.5 V and less than or equal to VDDA.
51 P3[6] bidirectional GPIO on port 3 with high-current output of uncommitted opamp 1, powered from VDDIO3; not recommended for CapSense use.
52 P3[7] bidirectional GPIO on port 3 with high-current output of uncommitted opamp 3, powered from VDDIO3; not recommended for CapSense use.
53 P12[0] bidirectional SIO carrying the I2C1 SCL line, powered from VDDIO3; SIO sink current is 25 mA and the pin is high-impedance when unpowered.
54 P12[1] bidirectional SIO carrying the I2C1 SDA line, powered from VDDIO3; SIO sink current is 25 mA and the pin is high-impedance when unpowered.
55 P15[2] passive 32.768 kHz crystal oscillator output pin (XO), also GPIO on port 15 powered from VDDIO3.
56 P15[3] passive 32.768 kHz crystal oscillator input pin (XI), also GPIO on port 15 powered from VDDIO3.
57 NC unconnected No connection.
58 NC unconnected No connection.
59 NC unconnected No connection.
60 NC unconnected No connection.
61 NC unconnected No connection.
62 NC unconnected No connection.
63 VCCA power_out Output of the analog core regulator (or input in external regulated mode); requires a 1 µF capacitor to VSSA and is not designed to drive external circuits.
64 VSSA power_in Ground for all analog peripherals.
65 VDDA power_in Supply for all analog peripherals and the analog core regulator; must be the highest voltage present on the device.
66 VSSD power_in Ground for all digital logic and I/O pins.
67 P12[2] bidirectional SIO powered from VDDIO0; SIO sink current is 25 mA and the pin is high-impedance when the device is unpowered.
68 P12[3] bidirectional SIO powered from VDDIO0; SIO sink current is 25 mA and the pin is high-impedance when the device is unpowered.
69 P4[0] bidirectional GPIO on port 4 powered from VDDIO0; overvoltage input must be limited to 100 µA with a series resistor.
70 P4[1] bidirectional GPIO on port 4 powered from VDDIO0; overvoltage input must be limited to 100 µA with a series resistor.
71 P0[0] bidirectional GPIO on port 0 with high-current output of uncommitted opamp 2, powered from VDDIO0; not recommended for CapSense use.
72 P0[1] bidirectional GPIO on port 0 with high-current output of uncommitted opamp 0, powered from VDDIO0; not recommended for CapSense use.
73 P0[2] bidirectional GPIO on port 0 with non-inverting input to opamp 0 and external reference for SAR1, powered from VDDIO0; overvoltage input must be limited to 100 µA.
74 P0[3] bidirectional GPIO on port 0 with inverting input to opamp 0 and external reference 0, powered from VDDIO0; overvoltage input must be limited to 100 µA.
75 VDDIO0 power_in Supply for the port 0, port 4 and P12[3:2] I/O pins; must be 1.71 V to 5.5 V and less than or equal to VDDA.
76 P0[4] bidirectional GPIO on port 0 with non-inverting input to opamp 2 and external reference for SAR0, powered from VDDIO0; overvoltage input must be limited to 100 µA.
77 P0[5] bidirectional GPIO on port 0 with inverting input to opamp 2, powered from VDDIO0; overvoltage input must be limited to 100 µA.
78 P0[6] bidirectional GPIO on port 0 with high-current IDAC0 output, powered from VDDIO0; overvoltage input must be limited to 100 µA.
79 P0[7] bidirectional GPIO on port 0 with high-current IDAC2 output, powered from VDDIO0; overvoltage input must be limited to 100 µA.
80 P4[2] bidirectional GPIO on port 4 powered from VDDIO0; overvoltage input must be limited to 100 µA with a series resistor.
81 P4[3] bidirectional GPIO on port 4 powered from VDDIO0; overvoltage input must be limited to 100 µA with a series resistor.
82 P4[4] bidirectional GPIO on port 4 powered from VDDIO0; overvoltage input must be limited to 100 µA with a series resistor.
83 P4[5] bidirectional GPIO on port 4 powered from VDDIO0; overvoltage input must be limited to 100 µA with a series resistor.
84 P4[6] bidirectional GPIO on port 4 powered from VDDIO0; overvoltage input must be limited to 100 µA with a series resistor.
85 P4[7] bidirectional GPIO on port 4 powered from VDDIO0; overvoltage input must be limited to 100 µA with a series resistor.
86 VCCD power_out Output of the digital core regulator (or input in external regulated mode); must be shorted to the other VCCD pin with a 1 µF capacitor to VSSD.
87 VSSD power_in Ground for all digital logic and I/O pins.
88 VDDD power_in Supply for all digital peripherals and the digital core regulator; must be less than or equal to VDDA.
89 P6[0] bidirectional GPIO on port 6 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
90 P6[1] bidirectional GPIO on port 6 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
91 P6[2] bidirectional GPIO on port 6 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
92 P6[3] bidirectional GPIO on port 6 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
93 P15[4] bidirectional GPIO on port 15 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
94 P15[5] bidirectional GPIO on port 15 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
95 P2[0] bidirectional GPIO on port 2 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
96 P2[1] bidirectional GPIO on port 2 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
97 P2[2] bidirectional GPIO on port 2 powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
98 P2[3] bidirectional GPIO on port 2 (TRACECLK alternate) powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
99 P2[4] bidirectional GPIO on port 2 (TRACEDATA[0] alternate) powered from VDDIO2; overvoltage input must be limited to 100 µA with a series resistor.
100 VDDIO2 power_in Supply for the port 2, port 6, P12[5:4] and P15[5:4] I/O pins; must be 1.71 V to 5.5 V and less than or equal to VDDA.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage relative to VSSA VDDA -0.5 6 V 68
Digital supply voltage relative to VSSD VDDD -0.5 6 V 68
I/O supply voltage relative to VSSD VDDIO -0.5 6 V 68
Direct analog core voltage input VCCA -0.5 1.95 V 68
Direct digital core voltage input VCCD -0.5 1.95 V 68
DC input voltage on SIO VSIO 7 V Output disabled 68
DC input voltage on SIO VSIO 6 V Output enabled 68
Voltage at boost converter input VIND 0.5 5.5 V 68
Boost converter supply VBAT 5.5 V 68
Current per VDDIO supply pin IVDDIO 100 mA 68
GPIO current IGPIO -30 41 mA 68
SIO current ISIO -49 28 mA 68
USBIO current IUSBIO -56 59 mA 68
ADC external reference inputs VEXTREF 2 V Pins P0[3], P3[2] 68
Latch up current LU -100 100 mA 68
Electrostatic discharge voltage, human body model ESDHBM 1000 V Human body model 68
ESD voltage, charge device model ESDCDM 500 V Charge device model 68
Analog supply voltage and input to analog core regulator VDDA 1.8 5.5 V Analog core regulator enabled 69
Analog supply voltage, analog regulator bypassed VDDA 1.71 1.8 1.89 V Analog core regulator disabled 69
Digital supply voltage relative to VSSD VDDD 1.8 V Digital core regulator enabled 69
Digital supply voltage, digital regulator bypassed VDDD 1.71 1.8 1.89 V Digital core regulator disabled 69
I/O supply voltage relative to VSSIO VDDIO 1.71 V 69
Direct analog core voltage input (analog regulator bypass) VCCA 1.71 1.8 1.89 V Analog core regulator disabled 69
Direct digital core voltage input (digital regulator bypass) VCCD 1.71 1.8 1.89 V Digital core regulator disabled 69
Active mode supply current IDD 2 3.8 mA VDDX = 2.7 V to 5.5 V; FCPU = 3 MHz; T = 105 °C 69
Active mode supply current IDD 3.2 5 mA VDDX = 2.7 V to 5.5 V; FCPU = 6 MHz; T = 105 °C 69
Active mode supply current IDD 5.6 7 mA VDDX = 2.7 V to 5.5 V; FCPU = 12 MHz; T = 105 °C 69
Active mode supply current IDD 9.1 10.5 mA VDDX = 2.7 V to 5.5 V; FCPU = 24 MHz; T = 105 °C 69
Active mode supply current IDD 15.7 17.25 mA VDDX = 2.7 V to 5.5 V; FCPU = 48 MHz; T = 105 °C 69
Active mode supply current IDD 19 21 mA VDDX = 2.7 V to 5.5 V; FCPU = 62 MHz; T = 105 °C 69
Active mode supply current IDD 27 30 mA VDDX = 2.7 V to 5.5 V; FCPU = 74 MHz; T = 105 °C 69
Active mode supply current IDD 22.5 25.5 mA VDDX = 2.7 V to 5.5 V; FCPU = 80 MHz, IMO = 3 MHz with PLL; T = 105 °C 69
CPU frequency FCPU 80.01 MHz 1.71 V to 5.5 V VDDD 72
Bus frequency FBUSCLK 80.01 MHz 1.71 V to 5.5 V VDDD 72
VDD ramp rate SVDD 0.066 V/µs 72
Time from VDDD/VDDA/VCCD/VCCA IPOR to I/O ports set to their reset states TIO_INIT 10 µs 72
Time from VDDD/VDDA/VCCD/VCCA PRES to CPU executing code at reset vector TSTARTUP 33 µs VCCA/VDDA = regulated from VDDA/VDDD, no PLL used, fast IMO boot mode (48 MHz typ.) 72
Time from VDDD/VDDA/VCCD/VCCA PRES to CPU executing code at reset vector TSTARTUP 66 µs VCCA/VCCD = regulated from VDDA/VDDD, no PLL used, slow IMO boot mode (12 MHz typ.) 72
Wakeup from sleep mode TSLEEP 25 µs Application of non-LVD interrupt to beginning of execution of next CPU instruction 72
Wakeup from hibernate mode THIBERNATE 150 µs Application of external interrupt to beginning of execution of next CPU instruction 72
Digital core regulator input voltage VDDD 1.8 5.5 V 72
Regulator output capacitor (digital core regulator) 0.9 1 1.1 µF ±10%, X5R ceramic or better 72
Analog core regulator input voltage VDDA 1.8 5.5 V 73
Regulator output capacitor (analog core regulator) 0.9 1 1.1 µF ±10%, X5R ceramic or better 73
Boost output voltage VOUT 1.71 1.8 1.89 V vsel = 1.8 V in register BOOST_CR0 73
Boost output voltage VOUT 1.81 1.9 2 V vsel = 1.9 V in register BOOST_CR0 73
Boost output voltage VOUT 1.9 2 2.1 V vsel = 2.0 V in register BOOST_CR0 73
Boost output voltage VOUT 2.16 2.4 2.64 V vsel = 2.4 V in register BOOST_CR0 73
Boost output voltage VOUT 2.43 2.7 2.97 V vsel = 2.7 V in register BOOST_CR0 73
Boost output voltage VOUT 2.7 3 3.3 V vsel = 3.0 V in register BOOST_CR0 73
Boost output voltage VOUT 2.97 3.3 3.63 V vsel = 3.3 V in register BOOST_CR0 73
Boost output voltage VOUT 3.24 3.6 3.96 V vsel = 3.6 V in register BOOST_CR0 73
Boost output voltage VOUT 4.5 5 5.5 V vsel = 5.0 V in register BOOST_CR0 73
Inductor peak current ILPK 700 mA 74
Load regulation RegLOAD 10 % 74
Line regulation RegLINE 10 % 74
XRES pull-up resistor Rpullup 3.5 5.6 8.5 kΩ 85
Reset pulse width (XRES) TRESET 1 µs 85
SIO pull-up resistor Rpullup 3.5 5.6 8.5 kΩ 79
SIO pull-down resistor Rpulldown 3.5 5.6 8.5 kΩ 79

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts gold lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the ma 129

CAD (KiCad official)

  • Symbol: CY8C5868AXI-LP035
  • Footprint: Package_QFP:TQFP-100_14x14mm_P0.5mm
  • 3D model: TQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: cy8c5868axi-lp035-etched.step / cy8c5868axi-lp035-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c5868axi-lp035.step / cy8c5868axi-lp035.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (140 pp, sha256 44169b47450fe803, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF