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CY8C5667AXI-LP040

Public Made by Adom

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Cypress Semicon Pre-ordered Products, LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentelectronic tools-instruments-consumablescy8c5667axi-lp040factory-2.0.0extractor-text

Verified CY8C5667AXI-LP040

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 100 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY8C5667AXI-LP040 · LQFP-100(14x14) · 100 pins
  • ✓copper: 100 copper pads, none touching another net
  • ✓datasheet: all 100 pin names found in the 133-page datasheet
  • ✓distributor: lcsc C2948830, digikey CY8C5667AXI-LP040-ND, mouser 727-CY8C5667AXILP040
  • ✓family: LQFP-100_14x14mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-l4_rwaj_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 100 pins = 100 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 100 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy8c5667axi-lp040.kicad_sym✓ cy8c5667axi-lp040.kicad_mod✓ cy8c5667axi-lp040.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
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docs Publish 0.1.0 · Ray
viewers cy8c5667axi-lp040: viewers · Ray
cy8c5667axi-lp040-etched.glb Publish 0.1.0 · Ray
cy8c5667axi-lp040-etched.step cy8c5667axi-lp040: factory component page (tier=mfr) · Ray
cy8c5667axi-lp040-hero.glb cy8c5667axi-lp040: hero GLB from the etched model (keeps the MPN mark) · Ray
cy8c5667axi-lp040-hero.overlay.json Publish 0.1.0 · Ray
cy8c5667axi-lp040.glb Publish 0.1.0 · Ray
cy8c5667axi-lp040.kicad_mod Publish 0.1.0 · Ray
cy8c5667axi-lp040.kicad_sym Publish 0.1.0 · Ray
cy8c5667axi-lp040.lbr Publish 0.1.0 · Ray
cy8c5667axi-lp040.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 100 pins · Ray

CY8C5667AXI-LP040

Cypress Semicon · Pre-ordered Products · LQFP-100(14x14)

CY8C5667AXI-LP040 from Cypress Semicon, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2[5] bidirectional General-purpose I/O on the VDDIO2 supply, also usable as Cortex-M3 TRACEDATA[1] output.
2 P2[6] bidirectional General-purpose I/O on the VDDIO2 supply, also usable as Cortex-M3 TRACEDATA[2] output.
3 P2[7] bidirectional General-purpose I/O on the VDDIO2 supply, also usable as Cortex-M3 TRACEDATA[3] output.
4 P12[4] bidirectional SIO pin used for I2C0 SCL, which provides wake from sleep on an address match; SIO has programmable high threshold and up to 25 mA current sink.
5 P12[5] bidirectional SIO pin used for I2C0 SDA, which provides wake from sleep on an address match; SIO has programmable high threshold and up to 25 mA current sink.
6 P6[4] bidirectional General-purpose I/O on the VDDIO2 supply; pin P6[4] is also the delta-sigma ADC input route noted in the analog globals section.
7 P6[5] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
8 P6[6] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
9 P6[7] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
10 VSSB power_in Ground connection for the boost pump.
11 IND passive Inductor connection to the boost pump.
12 VBOOST power_in Power sense connection to the boost pump; the boost output is available on this pin.
13 VBAT power_in Battery supply to the boost pump; the boost converter can operate from supply voltages as low as 0.5 V.
14 VSSD power_in Ground for all digital logic and I/O pins.
15 XRES input External reset pin, active low with internal pull-up.
16 P5[0] bidirectional General-purpose I/O on the VDDIO1 supply with analog, CapSense and LCD drive capability.
17 P5[1] bidirectional General-purpose I/O on the VDDIO1 supply with analog, CapSense and LCD drive capability.
18 P5[2] bidirectional General-purpose I/O on the VDDIO1 supply with analog, CapSense and LCD drive capability.
19 P5[3] bidirectional General-purpose I/O on the VDDIO1 supply with analog, CapSense and LCD drive capability.
20 P1[0] bidirectional JTAG TMS / Serial Wire Debug SWDIO programming and debug port connection; also a GPIO.
21 P1[1] input JTAG TCK / Serial Wire Debug SWDCK programming and debug clock connection; also a GPIO.
22 P1[2] bidirectional General-purpose I/O on the VDDIO1 supply.
23 P1[3] output JTAG TDO / Single Wire Viewer SWV output for programming and debug; also a GPIO.
24 P1[4] input JTAG Test Data In programming and debug port connection; also a GPIO.
25 P1[5] input Optional JTAG Test Reset programming and debug port connection; also a GPIO.
26 VDDIO1 power_in Supply for the VDDIO1 I/O pins; must be 1.71 V to 5.5 V and less than or equal to VDDA.
27 P1[6] bidirectional General-purpose I/O on the VDDIO1 supply.
28 P1[7] bidirectional General-purpose I/O on the VDDIO1 supply.
29 P12[6] bidirectional SIO pin on the VDDIO1 domain with programmable input threshold, comparator capability, and high-impedance when unpowered.
30 P12[7] bidirectional SIO pin on the VDDIO1 domain with programmable input threshold, comparator capability, and high-impedance when unpowered.
31 P5[4] bidirectional General-purpose I/O on the VDDIO1 supply with analog, CapSense and LCD drive capability.
32 P5[5] bidirectional General-purpose I/O on the VDDIO1 supply with analog, CapSense and LCD drive capability.
33 P5[6] bidirectional General-purpose I/O on the VDDIO1 supply with analog, CapSense and LCD drive capability.
34 P5[7] bidirectional General-purpose I/O on the VDDIO1 supply with analog, CapSense and LCD drive capability.
35 P15[6] bidirectional Provides D+ connection directly to a USB 2.0 bus; may be used as digital I/O powered from VDDD instead of VDDIO.
36 P15[7] bidirectional Provides D- connection directly to a USB 2.0 bus; may be used as digital I/O powered from VDDD instead of VDDIO.
37 VDDD power_in Supply for all digital peripherals and the digital core regulator; must be less than or equal to VDDA.
38 VSSD power_in Ground for all digital logic and I/O pins.
39 VCCD passive Output of the digital core regulator or input to the digital core; must be shorted to the other VCCD pin with a 1 µF capacitor to VSSD.
40 NC unconnected Not connected per the 100-pin TQFP pinout.
41 NC unconnected Not connected per the 100-pin TQFP pinout.
42 P15[0] passive 4 to 25 MHz crystal oscillator pin (XO); also a GPIO.
43 P15[1] passive 4 to 25 MHz crystal oscillator pin (XI); also a GPIO.
44 P3[0] output Low resistance output pin for high current DAC (IDAC1); also a GPIO.
45 P3[1] output Low resistance output pin for high current DAC (IDAC3); also a GPIO.
46 P3[2] input Inverting input to uncommitted opamp 3 and external reference 1 input to the analog system; also a GPIO.
47 P3[3] input Noninverting input to uncommitted opamp 3; also a GPIO.
48 P3[4] input Inverting input to uncommitted opamp 1; also a GPIO.
49 P3[5] input Noninverting input to uncommitted opamp 1; also a GPIO.
50 VDDIO3 power_in Supply for the VDDIO3 I/O pins; must be 1.71 V to 5.5 V and less than or equal to VDDA.
51 P3[6] output High current output of uncommitted opamp 1; also a GPIO.
52 P3[7] output High current output of uncommitted opamp 3; also a GPIO.
53 P12[0] bidirectional SIO pin used for I2C1 SCL, which provides wake from sleep on an address match.
54 P12[1] bidirectional SIO pin used for I2C1 SDA, which provides wake from sleep on an address match.
55 P15[2] passive 32.768-kHz crystal oscillator pin (XO); also a GPIO.
56 P15[3] passive 32.768-kHz crystal oscillator pin (XI); also a GPIO.
57 NC unconnected Not connected per the 100-pin TQFP pinout.
58 NC unconnected Not connected per the 100-pin TQFP pinout.
59 NC unconnected Not connected per the 100-pin TQFP pinout.
60 NC unconnected Not connected per the 100-pin TQFP pinout.
61 NC unconnected Not connected per the 100-pin TQFP pinout.
62 NC unconnected Not connected per the 100-pin TQFP pinout.
63 VCCA power_in Output of the analog core regulator or input to the analog core; requires a 1 µF capacitor to VSSA and is not designed to drive external circuits.
64 VSSA power_in Ground for all analog peripherals.
65 VDDA power_in Supply for all analog peripherals and the analog core regulator; must be the highest voltage present on the device.
66 VSSD power_in Ground for all digital logic and I/O pins.
67 P12[2] (SIO) bidirectional SIO pin on the VDDIO0 domain with programmable input threshold, comparator capability, and high-impedance when unpowered.
68 P12[3] (SIO) bidirectional SIO pin on the VDDIO0 domain with programmable input threshold, comparator capability, and high-impedance when unpowered.
69 P4[0] bidirectional General-purpose I/O on the VDDIO0 supply with analog, CapSense and LCD drive capability.
70 P4[1] bidirectional General-purpose I/O on the VDDIO0 supply with analog, CapSense and LCD drive capability.
71 P0[0] output High current output of uncommitted opamp 2; also a GPIO on the VDDIO0 supply.
72 P0[1] output High current output of uncommitted opamp 0; also a GPIO on the VDDIO0 supply.
73 P0[2] input Noninverting input to uncommitted opamp 0 and external reference for SAR1 ADC; also a GPIO.
74 P0[3] input Inverting input to uncommitted opamp 0 and external reference 0 input; also a GPIO.
75 VDDIO0 power_in Supply for the VDDIO0 I/O pins; must be 1.71 V to 5.5 V and less than or equal to VDDA.
76 P0[4] input Noninverting input to uncommitted opamp 2 and external reference for SAR0 ADC; also a GPIO.
77 P0[5] input Inverting input to uncommitted opamp 2; also a GPIO.
78 P0[6] output Low resistance output pin for high current DAC (IDAC0); also a GPIO.
79 P0[7] output Low resistance output pin for high current DAC (IDAC2); also a GPIO.
80 P4[2] bidirectional General-purpose I/O on the VDDIO0 supply with analog, CapSense and LCD drive capability.
81 P4[3] bidirectional General-purpose I/O on the VDDIO0 supply with analog, CapSense and LCD drive capability.
82 P4[4] bidirectional General-purpose I/O on the VDDIO0 supply with analog, CapSense and LCD drive capability.
83 P4[5] bidirectional General-purpose I/O on the VDDIO0 supply with analog, CapSense and LCD drive capability.
84 P4[6] bidirectional General-purpose I/O on the VDDIO0 supply with analog, CapSense and LCD drive capability.
85 P4[7] bidirectional General-purpose I/O on the VDDIO0 supply with analog, CapSense and LCD drive capability.
86 VCCD passive Output of the digital core regulator or input to the digital core; must be shorted to pin 39 with a 1 µF capacitor to VSSD.
87 VSSD power_in Ground for all digital logic and I/O pins.
88 VDDD power_in Supply for all digital peripherals and the digital core regulator; must be less than or equal to VDDA.
89 P6[0] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
90 P6[1] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
91 P6[2] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
92 P6[3] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
93 P15[4] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
94 P15[5] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
95 P2[0] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
96 P2[1] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
97 P2[2] bidirectional General-purpose I/O on the VDDIO2 supply with analog, CapSense and LCD drive capability.
98 P2[3] bidirectional General-purpose I/O on the VDDIO2 supply; also Cortex-M3 TRACECLK output clocking the TRACEDATA pins.
99 P2[4] bidirectional General-purpose I/O on the VDDIO2 supply; also Cortex-M3 TRACEPORT TRACEDATA[0] output.
100 VDDIO2 power_in Supply for the VDDIO2 I/O pins; must be 1.71 V to 5.5 V and less than or equal to VDDA.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package LQFP-100(14x14)
Category Electronic Tools/Instruments/Consumables
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage relative to VSSA VDDA -0.5 6 V 68
Digital supply voltage relative to VSSD VDDD -0.5 6 V 68
I/O supply voltage relative to VSSD VDDIO -0.5 6 V 68
Direct analog core voltage input VCCA -0.5 1.95 V 68
Direct digital core voltage input VCCD -0.5 1.95 V 68
DC input voltage on SIO VSIO 7 V Output disabled 68
DC input voltage on SIO VSIO 6 V Output enabled 68
Voltage at boost converter input VIND 0.5 5.5 V 68
Boost converter supply VBAT 5.5 V 68
Current per VDDIO supply pin IVDDIO 100 mA 68
GPIO current IGPIO -30 41 mA 68
SIO current ISIO -49 28 mA 68
USBIO current IUSBIO -56 59 mA 68
Latch up current LU -100 100 mA 68
Electrostatic discharge voltage ESDHBM 1000 V Human Body Model 68
Electrostatic discharge voltage ESDCDM 500 V Charge Device Model 68
Maximum storage temperature 150 °C JEDEC JESD22-A103 high temperature storage life (stated in Table 11-1 note 14) 68
Analog supply voltage and input to analog core regulator VDDA 1.8 5.5 V Analog core regulator enabled 69
Analog supply voltage, analog regulator bypassed VDDA 1.71 1.8 1.89 V Analog core regulator disabled 69
Digital supply voltage relative to VSSD VDDD 1.8 V Digital core regulator enabled 69
Digital supply voltage, digital regulator bypassed VDDD 1.71 1.8 1.89 V Digital core regulator disabled 69
I/O supply voltage relative to VSSIO VDDIO 1.71 V 69
Direct analog core voltage input (Analog regulator bypass) VCCA 1.71 1.8 1.89 V Analog core regulator disabled 69
Direct digital core voltage input (Digital regulator bypass) VCCD 1.71 1.8 1.89 V Digital core regulator disabled 69
Ambient temperature specification range TA -40 105 °C Specifications valid range (general note to Section 11) 69
Junction temperature specification limit TJ 120 °C Specifications valid range (general note to Section 11) 69
Active mode current, sum of IDDD + IDDA IDD 2 3.8 mA T = 105 °C; VDDX = 2.7 V to 5.5 V; FCPU = 3 MHz 69
Active mode current, sum of IDDD + IDDA IDD 3.2 5 mA T = 105 °C; VDDX = 2.7 V to 5.5 V; FCPU = 6 MHz 69
Active mode current, sum of IDDD + IDDA IDD 5.6 7 mA T = 105 °C; VDDX = 2.7 V to 5.5 V; FCPU = 12 MHz 69
Active mode current, sum of IDDD + IDDA IDD 9.1 10.5 mA T = 105 °C; VDDX = 2.7 V to 5.5 V; FCPU = 24 MHz 69
Active mode current, sum of IDDD + IDDA IDD 15.7 17.25 mA T = 105 °C; VDDX = 2.7 V to 5.5 V; FCPU = 48 MHz 69
Active mode current, sum of IDDD + IDDA IDD 19 21 mA T = 105 °C; VDDX = 2.7 V to 5.5 V; FCPU = 62 MHz 69
Active mode current, sum of IDDD + IDDA IDD 27 30 mA T = 105 °C; VDDX = 2.7 V to 5.5 V; FCPU = 74 MHz 69
Active mode current, sum of IDDD + IDDA IDD 22.5 25.5 mA T = 105 °C; VDDX = 2.7 V to 5.5 V; FCPU = 80 MHz, IMO = 3 MHz with PLL 69
Input voltage VDDD 1.8 5.5 V 73
Regulator output capacitor 0.9 1 1.1 µF ±10%, X5R ceramic or better 73
Boost output voltage VOUT 1.71 1.8 1.89 V vsel = 1.8 V in register BOOST_CR0 74
Boost output voltage VOUT 1.81 1.9 2 V vsel = 1.9 V in register BOOST_CR0 74
Boost output voltage VOUT 1.9 2 2.1 V vsel = 2.0 V in register BOOST_CR0 74
Boost output voltage VOUT 2.16 2.4 2.64 V vsel = 2.4 V in register BOOST_CR0 74
Boost output voltage VOUT 2.43 2.7 2.97 V vsel = 2.7 V in register BOOST_CR0 74
Boost output voltage VOUT 2.7 3 3.3 V vsel = 3.0 V in register BOOST_CR0 74
Boost output voltage VOUT 2.97 3.3 3.63 V vsel = 3.3 V in register BOOST_CR0 74
Boost output voltage VOUT 3.24 3.6 3.96 V vsel = 3.6 V in register BOOST_CR0 74
Boost output voltage VOUT 4.5 5 5.5 V vsel = 5.0 V in register BOOST_CR0 74
Inductor peak current ILPK 700 mA 74
Load regulation RegLOAD 10 % 74
Line regulation RegLINE 10 % 74
Boost inductor LBOOST 3.7 4.7 5.7 µH 4.7 µH nominal 75
Boost inductor LBOOST 8 10 12 µH 10 µH nominal 75
Boost inductor LBOOST 17 22 27 µH 22 µH nominal 75
Total capacitance sum of VDDD, VDDA, VDDIO CBOOST 17 26 31 µF 75
Battery filter capacitor CBAT 17 22 27 µF 75
Schottky diode average forward current IF 1 A 75
Schottky reverse voltage VR 20 V 75
Pull up resistor Rpullup 3.5 5.6 8.5 kΩ 84
Current through protection diode to VDDIO and VSSIO Idiode 100 µA 84
Reset pulse width TRESET 1 µs 84

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts gold lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the ma 122

CAD (KiCad official)

  • Symbol: CY8C5667AXI-LP040
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: cy8c5667axi-lp040-etched.step / cy8c5667axi-lp040-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c5667axi-lp040.step / cy8c5667axi-lp040.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (133 pp, sha256 dcde538e135701d3, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF