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CY8C5468LTI-LP026

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Cypress Semicon Microcontrollers (MCU/MPU/SOC), QFN-68(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY8C5468LTI-LP026

Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · QFN-68(8x8)

CY8C5468LTI-LP026 from Cypress Semicon, in a QFN-68(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2[6] bidirectional GPIO port 2 bit 6, also TRACEDATA[2]; powered from VDDIO2.
2 P2[7] bidirectional GPIO port 2 bit 7, also TRACEDATA[3]; powered from VDDIO2.
3 P12[4] bidirectional SIO port 12 bit 4, also I2C0 SCL with wake from sleep on address match; powered from VDDIO2.
4 P12[5] bidirectional SIO port 12 bit 5, also I2C0 SDA with wake from sleep on address match; powered from VDDIO2.
5 VSSB power_in Ground connection for the boost pump.
6 IND passive Inductor connection to the boost pump.
7 VBOOST power_out Power sense connection to the boost pump; boost output available to power other devices.
8 VBAT power_in Battery supply to the boost pump.
9 VSSD power_in Ground for all digital logic and I/O pins.
10 XRES input External reset pin, active low with internal pull-up.
11 P1[0] bidirectional GPIO port 1 bit 0, also JTAG TMS and SWDIO; powered from VDDIO1.
12 P1[1] bidirectional GPIO port 1 bit 1, also JTAG TCK and SWDCK; powered from VDDIO1.
13 P1[2] bidirectional GPIO port 1 bit 2, also configurable XRES; powered from VDDIO1.
14 P1[3] bidirectional GPIO port 1 bit 3, also JTAG TDO and SWV; powered from VDDIO1.
15 P1[4] bidirectional GPIO port 1 bit 4, also JTAG TDI; powered from VDDIO1.
16 P1[5] bidirectional GPIO port 1 bit 5, also optional JTAG nTRST; powered from VDDIO1.
17 VDDIO1 power_in I/O supply for port 1 and P12[7:6]; 1.71 V to 5.5 V and must be less than or equal to VDDA.
18 P1[6] bidirectional GPIO port 1 bit 6; powered from VDDIO1.
19 P1[7] bidirectional GPIO port 1 bit 7; powered from VDDIO1.
20 P12[6] bidirectional SIO port 12 bit 6; powered from VDDIO1.
21 P12[7] bidirectional SIO port 12 bit 7; powered from VDDIO1.
22 P15[6] bidirectional USBIO D+ (also SWDIO), usable as digital I/O and powered from VDDD; Do Not Use and left floating on devices without USB.
23 P15[7] bidirectional USBIO D- (also SWDCK), usable as digital I/O and powered from VDDD; Do Not Use and left floating on devices without USB.
24 VDDD power_in Supply for all digital peripherals and digital core regulator; must be less than or equal to VDDA.
25 VSSD power_in Ground for all digital logic and I/O pins.
26 VCCD power_out Digital core regulator output; needs 1 uF to VSSD, shorted to the other VCCD pin, not to drive external circuits or be powered when internally regulated.
27 P15[0] bidirectional GPIO port 15 bit 0, also MHz crystal XO (4 to 25 MHz oscillator); powered from VDDIO3.
28 P15[1] bidirectional GPIO port 15 bit 1, also MHz crystal XI (4 to 25 MHz oscillator); powered from VDDIO3.
29 P3[0] bidirectional GPIO port 3 bit 0; powered from VDDIO3.
30 P3[1] bidirectional GPIO port 3 bit 1; powered from VDDIO3.
31 P3[2] bidirectional GPIO port 3 bit 2, also EXTREF1 external reference input to the analog system; powered from VDDIO3.
32 P3[3] bidirectional GPIO port 3 bit 3; powered from VDDIO3.
33 P3[4] bidirectional GPIO port 3 bit 4; powered from VDDIO3.
34 P3[5] bidirectional GPIO port 3 bit 5; powered from VDDIO3.
35 VDDIO3 power_in I/O supply for port 3, P12[1:0] and P15[3:0]; 1.71 V to 5.5 V and must be less than or equal to VDDA.
36 P3[6] bidirectional GPIO port 3 bit 6; powered from VDDIO3.
37 P3[7] bidirectional GPIO port 3 bit 7; powered from VDDIO3.
38 P12[0] bidirectional SIO port 12 bit 0, also I2C1 SCL with wake from sleep on address match; powered from VDDIO3.
39 P12[1] bidirectional SIO port 12 bit 1, also I2C1 SDA with wake from sleep on address match; powered from VDDIO3.
40 P15[2] bidirectional GPIO port 15 bit 2, also kHz crystal XO (32.768 kHz oscillator); powered from VDDIO3.
41 P15[3] bidirectional GPIO port 15 bit 3, also kHz crystal XI (32.768 kHz oscillator); powered from VDDIO3.
42 VCCA power_out Analog core regulator output needing 1 uF to VSSA; not to drive external circuits, and no power tied to it when internally regulated (external range 1.71 V to 1.89 V).
43 VSSA power_in Ground for all analog peripherals.
44 VDDA power_in Supply for all analog peripherals and analog core regulator; must be the highest voltage present on the device.
45 VSSD power_in Ground for all digital logic and I/O pins.
46 P12[2] bidirectional SIO port 12 bit 2; powered from VDDIO0.
47 P12[3] bidirectional SIO port 12 bit 3; powered from VDDIO0.
48 P0[0] bidirectional GPIO port 0 bit 0, also OPAMP2 OUT high-current opamp output; powered from VDDIO0.
49 P0[1] bidirectional GPIO port 0 bit 1, also OPAMP0 OUT high-current opamp output; powered from VDDIO0.
50 P0[2] bidirectional GPIO port 0 bit 2, also OPAMP0+ noninverting input and SAR1 EXTREF; powered from VDDIO0.
51 P0[3] bidirectional GPIO port 0 bit 3, also OPAMP0- inverting input and EXTREF0; powered from VDDIO0.
52 VDDIO0 power_in I/O supply for port 0, P4 and P12[3:2]; 1.71 V to 5.5 V and must be less than or equal to VDDA.
53 P0[4] bidirectional GPIO port 0 bit 4, also OPAMP2+ noninverting input and SAR0 EXTREF; powered from VDDIO0.
54 P0[5] bidirectional GPIO port 0 bit 5, also OPAMP2- inverting input; powered from VDDIO0.
55 P0[6] bidirectional GPIO port 0 bit 6, also IDAC0 low-resistance current DAC output; powered from VDDIO0.
56 P0[7] bidirectional GPIO port 0 bit 7, also IDAC2 low-resistance current DAC output; powered from VDDIO0.
57 VCCD power_out Digital core regulator output; needs 1 uF to VSSD, shorted to the other VCCD pin, not to drive external circuits or be powered when internally regulated.
58 VSSD power_in Ground for all digital logic and I/O pins.
59 VDDD power_in Supply for all digital peripherals and digital core regulator; must be less than or equal to VDDA.
60 P15[4] bidirectional GPIO port 15 bit 4; powered from VDDIO2.
61 P15[5] bidirectional GPIO port 15 bit 5; powered from VDDIO2.
62 P2[0] bidirectional GPIO port 2 bit 0; powered from VDDIO2.
63 P2[1] bidirectional GPIO port 2 bit 1; powered from VDDIO2.
64 P2[2] bidirectional GPIO port 2 bit 2; powered from VDDIO2.
65 P2[3] bidirectional GPIO port 2 bit 3, also TRACECLK; powered from VDDIO2.
66 P2[4] bidirectional GPIO port 2 bit 4, also TRACEDATA[0]; powered from VDDIO2.
67 VDDIO2 power_in I/O supply for port 2, P12[5:4] and P15[5:4]; 1.71 V to 5.5 V and must be less than or equal to VDDA.
68 P2[5] bidirectional GPIO port 2 bit 5, also TRACEDATA[1]; powered from VDDIO2.
69 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-68(8x8)
Category Embedded Processors & Controllers
Pins 69

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage relative to VSSA VDDA -0.5 6 V 66
Digital supply voltage relative to VSSD VDDD -0.5 6 V 66
I/O supply voltage relative to VSSD VDDIO -0.5 6 V 66
Direct analog core voltage input VCCA -0.5 1.95 V 66
Direct digital core voltage input VCCD -0.5 1.95 V 66
DC input voltage on SIO, output disabled VSIO 7 V Output disabled 66
DC input voltage on SIO, output enabled VSIO 6 V Output enabled 66
Voltage at boost converter input VIND 0.5 5.5 V 66
Boost converter supply VBAT 5.5 V 66
Current per VDDIO supply pin IVDDIO 100 mA 66
GPIO current IGPIO -30 41 mA 66
SIO current ISIO -49 28 mA 66
USBIO current IUSBIO -56 59 mA 66
Latch up current LU -140 140 mA 66
Electrostatic discharge voltage ESDHBM 2000 V Human body model 66
ESD voltage ESDCDM 500 V Charge device model 66
Maximum storage temperature 150 °C JEDEC JESD22-A103 66
Analog supply voltage and input to analog core regulator VDDA 1.8 5.5 V Analog core regulator enabled 67
Analog supply voltage, analog regulator bypassed VDDA 1.71 1.8 1.89 V Analog core regulator disabled 67
Digital supply voltage relative to VSSD VDDD 1.8 V Digital core regulator enabled 67
Digital supply voltage, digital regulator bypassed VDDD 1.71 1.8 1.89 V Digital core regulator disabled 67
I/O supply voltage relative to VSSIO VDDIO 1.71 V 67
Direct analog core voltage input (analog regulator bypass) VCCA 1.71 1.8 1.89 V Analog core regulator disabled 67
Direct digital core voltage input (digital regulator bypass) VCCD 1.71 1.8 1.89 V Digital core regulator disabled 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 1.9 3.8 mA VDDX = 2.7 V to 5.5 V; FCPU = 3 MHz; T = -40 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 2 3.8 mA VDDX = 2.7 V to 5.5 V; FCPU = 3 MHz; T = 85 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 3.1 5 mA VDDX = 2.7 V to 5.5 V; FCPU = 6 MHz; T = -40 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 3.2 5 mA VDDX = 2.7 V to 5.5 V; FCPU = 6 MHz; T = 85 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 5.4 7 mA VDDX = 2.7 V to 5.5 V; FCPU = 12 MHz; T = -40 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 5.6 7 mA VDDX = 2.7 V to 5.5 V; FCPU = 12 MHz; T = 85 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 8.9 10.5 mA VDDX = 2.7 V to 5.5 V; FCPU = 24 MHz; T = -40 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 9.1 10.5 mA VDDX = 2.7 V to 5.5 V; FCPU = 24 MHz; T = 85 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 15.5 17 mA VDDX = 2.7 V to 5.5 V; FCPU = 48 MHz; T = -40 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 15.4 17 mA VDDX = 2.7 V to 5.5 V; FCPU = 48 MHz; T = 25 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 15.7 17 mA VDDX = 2.7 V to 5.5 V; FCPU = 48 MHz; T = 85 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 18 19.5 mA VDDX = 2.7 V to 5.5 V; FCPU = 62 MHz; T = -40 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 18.5 19.5 mA VDDX = 2.7 V to 5.5 V; FCPU = 62 MHz; T = 85 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 26.5 30 mA VDDX = 2.7 V to 5.5 V; FCPU = 74 MHz; T = -40 °C 67
Active mode supply current (IDDD + IDDA), IMO enabled IDD 27 30 mA VDDX = 2.7 V to 5.5 V; FCPU = 74 MHz; T = 85 °C 67
Active mode supply current (IDDD + IDDA), PLL enabled IDD 22 25.5 mA VDDX = 2.7 V to 5.5 V; FCPU = 80 MHz, IMO = 3 MHz with PLL; T = -40 °C 67
Active mode supply current (IDDD + IDDA), PLL enabled IDD 22.5 25.5 mA VDDX = 2.7 V to 5.5 V; FCPU = 80 MHz, IMO = 3 MHz with PLL; T = 85 °C 67
Ambient temperature, specification validity range TA -40 85 °C 66
Junction temperature, specification validity limit TJ 100 °C 66
Digital core regulator output capacitor 0.9 1 1.1 µF ±10%, X5R ceramic or better 70
Analog core regulator output capacitor 0.9 1 1.1 µF ±10%, X5R ceramic or better 70
Inductor peak current ILPK 700 mA 71
XRES pull-up resistor Rpullup 3.5 5.6 8.5 kΩ 81
XRES reset pulse width TRESET 1 µs 81
Boost output voltage VOUT 4.5 5 5.5 V vsel = 5.0 V in register BOOST_CR0 71
Load regulation RegLOAD 10 % 71
Line regulation RegLINE 10 % 71
Boost inductor LBOOST 3.7 4.7 5.7 µH 4.7 µH nominal 72
Total boost capacitance (sum of VDDD, VDDA, VDDIO) CBOOST 17 26 31 µF 72

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts gold lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the ma 118

CAD (KiCad official)

  • Symbol: CY8C5468LTI-LP026
  • Footprint: Package_DFN_QFN:QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm
  • 3D model: QFN-68(8x8) (KiCad packages3D, STEP)
  • 3D model files: cy8c5468lti-lp026-etched.step / cy8c5468lti-lp026-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c5468lti-lp026.step / cy8c5468lti-lp026.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (127 pp, sha256 10a3b3b224eaca54, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF