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CY8C5268LTI-LP030

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-68(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy8c5268lti-lp030factory-2.0.0extractor-text

Verified CY8C5268LTI-LP030

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 69 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY8C5268LTI-LP030 · QFN-68(8x8) · 69 pins
  • ✓copper: 69 copper pads, none touching another net
  • ✓datasheet: all 69 pin names found in the 117-page datasheet
  • ✓distributor: lcsc C2959467, digikey 448-CY8C5268LTI-LP030-ND, mouser 727-CY8C5268LTILP030
  • ✓family: QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-t18dul1i/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): the datasheet dimensions give no height or body size to compare (datasheet p.109)
  • ✓pads: 69 pins = 69 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 69 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy8c5268lti-lp030.kicad_sym✓ cy8c5268lti-lp030.kicad_mod✓ cy8c5268lti-lp030.step
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Ray Publish 0.1.0 9c6e012

CY8C5268LTI-LP030

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-68(8x8)

CY8C5268LTI-LP030 from Cypress Semicon, in a QFN-68(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2[6] bidirectional GPIO port 2 bit 6, powered from VDDIO2, with TRACEDATA2 trace output function.
2 P2[7] bidirectional GPIO port 2 bit 7, powered from VDDIO2, with TRACEDATA3 trace output function.
3 P12[4] bidirectional SIO port 12 bit 4, powered from VDDIO2, with I2C0 SCL function that provides wake from sleep on address match.
4 P12[5] bidirectional SIO port 12 bit 5, powered from VDDIO2, with I2C0 SDA function that provides wake from sleep on address match.
5 VSSB power_in Ground connection for the boost pump.
6 IND passive Inductor connection to the boost pump.
7 VBOOST power_out Power sense connection to the boost pump.
8 VBAT power_in Battery supply to the boost pump.
9 VSSD power_in Ground for all digital logic and I/O pins.
10 XRES input External reset pin, active low with internal pull-up.
11 P1[0] bidirectional GPIO port 1 bit 0, powered from VDDIO1, with TMS (JTAG) and SWDIO programming/debug function.
12 P1[1] bidirectional GPIO port 1 bit 1, powered from VDDIO1, with TCK (JTAG) and SWDCK programming/debug function.
13 P1[2] bidirectional GPIO port 1 bit 2, powered from VDDIO1, usable as configurable XRES.
14 P1[3] bidirectional GPIO port 1 bit 3, powered from VDDIO1, with TDO (JTAG) and SWV function.
15 P1[4] bidirectional GPIO port 1 bit 4, powered from VDDIO1, with TDI (JTAG) function.
16 P1[5] bidirectional GPIO port 1 bit 5, powered from VDDIO1, with nTRST (JTAG test reset) function.
17 VDDIO1 power_in Supply for I/O pins of port 1 and P12[7:6]; must be 1.71 V to 5.5 V and not exceed VDDA.
18 P1[6] bidirectional GPIO port 1 bit 6, powered from VDDIO1.
19 P1[7] bidirectional GPIO port 1 bit 7, powered from VDDIO1.
20 P12[6] bidirectional SIO port 12 bit 6, powered from VDDIO1.
21 P12[7] bidirectional SIO port 12 bit 7, powered from VDDIO1.
22 P15[6] bidirectional USBIO D+ connecting directly to a USB 2.0 bus (also SWDIO), powered from VDDD; may be used as digital I/O.
23 P15[7] bidirectional USBIO D- connecting directly to a USB 2.0 bus (also SWDCK), powered from VDDD; may be used as digital I/O.
24 VDDD power_in Supply for digital peripherals and digital core regulator; must be less than or equal to VDDA.
25 VSSD power_in Ground for all digital logic and I/O pins.
26 VCCD passive Digital core regulator output or input; must be shorted to the other VCCD pin with a 1 uF capacitor to VSSD and not driven in internally regulated mode.
27 P15[0] bidirectional GPIO port 15 bit 0, powered from VDDIO3, with 4 to 25 MHz crystal oscillator XO function.
28 P15[1] bidirectional GPIO port 15 bit 1, powered from VDDIO3, with 4 to 25 MHz crystal oscillator XI function.
29 P3[0] bidirectional GPIO port 3 bit 0, powered from VDDIO3.
30 P3[1] bidirectional GPIO port 3 bit 1, powered from VDDIO3.
31 P3[2] bidirectional GPIO port 3 bit 2, powered from VDDIO3, with EXTREF1 external reference input to the analog system.
32 P3[3] bidirectional GPIO port 3 bit 3, powered from VDDIO3.
33 P3[4] bidirectional GPIO port 3 bit 4, powered from VDDIO3.
34 P3[5] bidirectional GPIO port 3 bit 5, powered from VDDIO3.
35 VDDIO3 power_in Supply for I/O pins of port 3, P12[1:0] and P15[3:0]; must be 1.71 V to 5.5 V and not exceed VDDA.
36 P3[6] bidirectional GPIO port 3 bit 6, powered from VDDIO3.
37 P3[7] bidirectional GPIO port 3 bit 7, powered from VDDIO3.
38 P12[0] bidirectional SIO port 12 bit 0, powered from VDDIO3, with I2C1 SCL function.
39 P12[1] bidirectional SIO port 12 bit 1, powered from VDDIO3, with I2C1 SDA function.
40 P15[2] bidirectional GPIO port 15 bit 2, powered from VDDIO3, with 32.768 kHz crystal oscillator XO function.
41 P15[3] bidirectional GPIO port 15 bit 3, powered from VDDIO3, with 32.768 kHz crystal oscillator XI function.
42 VCCA power_in Analog core regulator output or input; requires a 1 uF capacitor to VSSA, and no power should be applied in internally regulated mode.
43 VSSA power_in Ground for all analog peripherals.
44 VDDA power_in Supply for all analog peripherals and analog core regulator; must be the highest voltage present on the device.
45 VSSD power_in Ground for all digital logic and I/O pins.
46 P12[2] bidirectional SIO port 12 bit 2, powered from VDDIO0.
47 P12[3] bidirectional SIO port 12 bit 3, powered from VDDIO0.
48 P0[0] bidirectional GPIO port 0 bit 0, powered from VDDIO0.
49 P0[1] bidirectional GPIO port 0 bit 1, powered from VDDIO0.
50 P0[2] bidirectional GPIO port 0 bit 2, powered from VDDIO0.
51 P0[3] bidirectional GPIO port 0 bit 3, powered from VDDIO0, with EXTREF0 external reference input to the analog system.
52 VDDIO0 power_in Supply for I/O pins of port 0 and P12[3:2]; must be 1.71 V to 5.5 V and not exceed VDDA.
53 P0[4] bidirectional GPIO port 0 bit 4, powered from VDDIO0.
54 P0[5] bidirectional GPIO port 0 bit 5, powered from VDDIO0.
55 P0[6] bidirectional GPIO port 0 bit 6, powered from VDDIO0, with IDAC0 low resistance high-current DAC output.
56 P0[7] bidirectional GPIO port 0 bit 7, powered from VDDIO0.
57 VCCD passive Digital core regulator output or input; must be shorted to the other VCCD pin with a 1 uF capacitor to VSSD and not driven in internally regulated mode.
58 VSSD power_in Ground for all digital logic and I/O pins.
59 VDDD power_in Supply for digital peripherals and digital core regulator; must be less than or equal to VDDA.
60 P15[4] bidirectional GPIO port 15 bit 4, powered from VDDIO2.
61 P15[5] bidirectional GPIO port 15 bit 5, powered from VDDIO2.
62 P2[0] bidirectional GPIO port 2 bit 0, powered from VDDIO2.
63 P2[1] bidirectional GPIO port 2 bit 1, powered from VDDIO2.
64 P2[2] bidirectional GPIO port 2 bit 2, powered from VDDIO2.
65 P2[3] bidirectional GPIO port 2 bit 3, powered from VDDIO2, with TRACECLK trace clock output function.
66 P2[4] bidirectional GPIO port 2 bit 4, powered from VDDIO2, with TRACEDATA0 trace output function.
67 VDDIO2 power_in Supply for I/O pins of port 2, P12[5:4] and P15[5:4]; must be 1.71 V to 5.5 V and not exceed VDDA.
68 P2[5] bidirectional GPIO port 2 bit 5, powered from VDDIO2, with TRACEDATA1 trace output function.
69 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-68(8x8)
Category Single Chip Microcomputer/Microcontroller
Pins 69

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog supply voltage relative to VSSA VDDA -0.5 6 V 62
Digital supply voltage relative to VSSD VDDD -0.5 6 V 62
I/O supply voltage relative to VSSD VDDIO -0.5 6 V 62
Direct analog core voltage input VCCA -0.5 1.95 V 62
Direct digital core voltage input VCCD -0.5 1.95 V 62
DC input voltage on SIO, output disabled VSIO 7 V Output disabled 62
DC input voltage on SIO, output enabled VSIO 6 V Output enabled 62
Boost converter supply VBAT 5.5 V 62
Current per VDDIO supply pin IVDDIO 100 mA 62
GPIO current IGPIO -30 41 mA 62
SIO current ISIO -49 28 mA 62
USBIO current IUSBIO -56 59 mA 62
Latch up current LU -100 100 mA 62
ESD voltage HBM ESDHBM 1000 V Human body model 62
ESD voltage CDM ESDCDM 500 V Charge device model 62
Analog supply voltage, regulator enabled VDDA 1.8 5.5 V Analog core regulator enabled 63
Analog supply voltage, regulator bypassed VDDA 1.71 1.8 1.89 V Analog core regulator disabled 63
Digital supply voltage, regulator bypassed VDDD 1.71 1.8 1.89 V Digital core regulator disabled 63
Active mode current, 6 MHz IDD 3.1 5 mA VDDX = 2.7 V to 5.5 V; FCPU = 6 MHz; T = 25 °C 63
Active mode current, 48 MHz IDD 15.4 17 mA VDDX = 2.7 V to 5.5 V; FCPU = 48 MHz; T = 25 °C 63
Active mode current, 80 MHz IDD 22 25.5 mA VDDX = 2.7 V to 5.5 V; FCPU = 80 MHz, IMO = 3 MHz with PLL; T = 25 °C 63
Digital regulator input voltage VDDD 1.8 5.5 V 66
Digital regulator output capacitor 0.9 1 1.1 µF ±10%, X5R ceramic or better 66
Boost output voltage VOUT 4.5 5 5.5 V vsel = 5.0 V in register BOOST_CR0 67
Boost inductor peak current ILPK 700 mA 67
Boost IQ active IQ 250 µA Boost active mode 67
VREF initial VREF 1.013 1.024 1.035 V Initial trimming, 25 °C 77
XRES pull up resistor Rpullup 3.5 5.6 8.5 kΩ 77
Operating ambient temperature TA -40 85 °C 2

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts gold lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the ma 107

CAD (KiCad official)

  • Symbol: CY8C5268LTI-LP030
  • Footprint: Package_DFN_QFN:QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm
  • 3D model: QFN-68(8x8) (KiCad packages3D, STEP)
  • 3D model files: cy8c5268lti-lp030-etched.step / cy8c5268lti-lp030-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c5268lti-lp030.step / cy8c5268lti-lp030.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (117 pp, sha256 87963dfadfc60af9, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF