component

CY8C4248AZI-L485

Public Made by Adom

by adom

Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy8c4248azi-l485factory-2.0.0extractor-text

Verified CY8C4248AZI-L485

by Ray · last 2 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

2 Nov 2026RayPublished by the parts factory: tier mfr, 64 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY8C4248AZI-L485 · TQFP-64(10x10) · 64 pins
  • ✓copper: 64 copper pads, none touching another net
  • ✓datasheet: all 64 pin names found in the 72-page datasheet
  • ✓distributor: lcsc C2959371, digikey 448-CY8C4248AZI-L485-ND, mouser 727-CY8C4248AZI-L485
  • ✓family: TQFP-64_10x10mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-x2xz6hu7/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 64 pins = 64 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 64 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy8c4248azi-l485.kicad_sym✓ cy8c4248azi-l485.kicad_mod✓ cy8c4248azi-l485.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cy8c4248azi-l485: viewers · Ray
cy8c4248azi-l485-etched.glb Publish 0.1.0 · Ray
cy8c4248azi-l485-etched.step cy8c4248azi-l485: factory component page (tier=mfr) · Ray
cy8c4248azi-l485-hero.glb cy8c4248azi-l485: hero GLB from the etched model (keeps the MPN mark) · Ray
cy8c4248azi-l485-hero.overlay.json Publish 0.1.0 · Ray
cy8c4248azi-l485.glb Publish 0.1.0 · Ray
cy8c4248azi-l485.kicad_mod Publish 0.1.0 · Ray
cy8c4248azi-l485.kicad_sym Publish 0.1.0 · Ray
cy8c4248azi-l485.lbr Publish 0.1.0 · Ray
cy8c4248azi-l485.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 64 pins · Ray

CY8C4248AZI-L485

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-64(10x10)

CY8C4248AZI-L485 from Cypress Semicon, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7/VREF bidirectional GPIO pin P1.7 that also serves as CTB0 pad 7 and the external SAR reference input sar_ext_vref, which can be used for an external bypass of the internal reference.
2 P2.0 bidirectional GPIO pin P2.0 connected to SARMUX pad 0 of the 8-input SAR sequencer, with TCPWM and SCB alternate functions.
3 P2.1 bidirectional GPIO pin P2.1 connected to SARMUX pad 1 of the SAR sequencer, with TCPWM and SCB alternate functions.
4 P2.2 bidirectional GPIO pin P2.2 connected to SARMUX pad 2 of the SAR sequencer, with TCPWM and SCB alternate functions.
5 P2.3 bidirectional GPIO pin P2.3 connected to SARMUX pad 3 of the SAR sequencer, with TCPWM and SCB alternate functions.
6 P2.4 bidirectional GPIO pin P2.4 connected to SARMUX pad 4 of the SAR sequencer, with TCPWM and SCB alternate functions.
7 P2.5 bidirectional GPIO pin P2.5 connected to SARMUX pad 5 of the SAR sequencer, with TCPWM and SCB alternate functions.
8 P2.6 bidirectional GPIO pin P2.6 connected to SARMUX pad 6 of the SAR sequencer, with TCPWM and SCB alternate functions.
9 P2.7 bidirectional GPIO pin P2.7 connected to SARMUX pad 7 of the SAR sequencer, with TCPWM alternate function.
10 VSSA power_in Analog ground pin, shorted to VSS where the package does not provide a separate pin.
11 VDDA power_in Analog VDD pin that should be present before or concurrently with VDDD, and whose value must be equal to or higher than VDDD and VDDIO.
12 P6.0 bidirectional Overvoltage-tolerant GPIO pin P6.0 (GPIO_OVT) with TCPWM, SCB and CAN alternate functions.
13 P6.1 bidirectional Overvoltage-tolerant GPIO pin P6.1 (GPIO_OVT) with TCPWM, SCB and CAN alternate functions.
14 P6.2 bidirectional Overvoltage-tolerant GPIO pin P6.2 (GPIO_OVT) with TCPWM, SCB and CAN alternate functions.
15 P6.4/P12.0 bidirectional Overvoltage-tolerant GPIO pin P6.4 that is shared with SIO pin P12.0, with TCPWM and SCB alternate functions.
16 P6.5/P12.1 bidirectional Overvoltage-tolerant GPIO pin P6.5 that is shared with SIO pin P12.1, with TCPWM and SCB alternate functions.
17 VSSIO power_in I/O ground pin for the VDDIO power domain.
18 P3.0 bidirectional GPIO pin P3.0 with TCPWM and SCB alternate functions, including SCB UART RX.
19 P3.1 bidirectional GPIO pin P3.1 with TCPWM and SCB alternate functions, including SCB UART TX.
20 P3.2 bidirectional GPIO pin P3.2 with TCPWM and SCB alternate functions, and the SWD data alternate function.
21 P3.3 bidirectional GPIO pin P3.3 with TCPWM and SCB alternate functions, and the SWD clock alternate function.
22 P3.4 bidirectional GPIO pin P3.4 with TCPWM and SCB SPI select alternate functions.
23 P3.5 bidirectional GPIO pin P3.5 with TCPWM and SCB SPI select alternate functions.
24 P3.6 bidirectional GPIO pin P3.6 with TCPWM and SCB SPI select alternate functions.
25 P3.7 bidirectional GPIO pin P3.7 with TCPWM alternate function.
26 VDDIO power_in I/O pin power domain that should not be present without VDDD.
27 P4.0 bidirectional GPIO pin P4.0 with SCB, CAN and I2C alternate functions.
28 P4.1 bidirectional GPIO pin P4.1 with SCB and CAN alternate functions.
29 P4.2 bidirectional GPIO pin P4.2 with CSD C_mod, SCB, CAN and LPCOMP alternate functions.
30 P4.3 bidirectional GPIO pin P4.3 with CSD C_sh_tank, SCB and LPCOMP alternate functions.
31 P4.4 bidirectional GPIO pin P4.4 with CAN TX enable and SCB SPI select alternate functions.
32 P4.5 bidirectional GPIO pin P4.5 with CAN RX and SCB SPI select alternate functions.
33 P4.6 bidirectional GPIO pin P4.6 with CAN TX and SCB SPI select alternate functions.
34 D+/P13.0 bidirectional USB Full-Speed D+ data line shared with GPIO P13.0, which requires VBUS (P13.2) to be powered.
35 D-/P13.1 bidirectional USB Full-Speed D- data line shared with GPIO P13.1, which requires VBUS (P13.2) to be powered.
36 VBUS/P13.2 power_in USB VBUS input, typically 5 V with a range of 4.35 V to 5.5 V, with no constraint relative to VDDD.
37 P7.0 bidirectional GPIO pin P7.0 that is also the external crystal oscillator input srss.eco_in, with TCPWM and SCB alternate functions.
38 P7.1 bidirectional GPIO pin P7.1 that is also the external crystal oscillator output srss.eco_out, with TCPWM and SCB alternate functions.
39 P0.0 bidirectional GPIO pin P0.0 with LPCOMP input, CAN RX and USB VBUS-valid alternate functions.
40 P0.1 bidirectional GPIO pin P0.1 with LPCOMP input, CAN TX and SCB alternate functions.
41 P0.2 bidirectional GPIO pin P0.2 with LPCOMP input and SCB alternate functions.
42 P0.3 bidirectional GPIO pin P0.3 with LPCOMP input.
43 P0.4 bidirectional GPIO pin P0.4 that is also the watch crystal oscillator input wco_in, with SCB alternate functions.
44 P0.5 bidirectional GPIO pin P0.5 that is also the watch crystal oscillator output wco_out, with SCB alternate functions.
45 P0.6 bidirectional GPIO pin P0.6 that is also the external clock input srss.ext_clk, with SCB alternate functions.
46 P0.7 bidirectional GPIO pin P0.7 with SCB RTS, CAN TX enable and wakeup alternate functions.
47 XRES input External reset input reserved for external reset to avoid complications with configuration and multiple pin functions during power-on or reconfiguration.
48 VCCD power_out Regulated digital supply output of 1.8 V ±5% that must be bypassed to VSS with a 1 µF ceramic capacitor.
49 VSSD power_in Digital ground pin.
50 VDDD power_in Power supply for both analog and digital sections where there is no VDDA pin, operating over 1.71 V to 5.5 V.
51 P5.0 bidirectional GPIO pin P5.0 with CTB1 pad, CSD C_mod, TCPWM and SCB alternate functions.
52 P5.1 bidirectional GPIO pin P5.1 with CTB1 pad, CSD C_sh_tank, TCPWM and SCB alternate functions.
53 P5.2 bidirectional GPIO pin P5.2 with CTB1 pad, CTB1 opamp output, TCPWM, SCB and LPCOMP alternate functions.
54 P5.3 bidirectional GPIO pin P5.3 with CTB1 pad, CTB1 opamp output, TCPWM, SCB and LPCOMP alternate functions.
55 P5.5 bidirectional GPIO pin P5.5 with CTB1 pad, TCPWM and SCB SPI select alternate functions.
56 VDDA power_in Analog VDD pin where package pins allow, which must be equal to or higher than VDDD and VDDIO.
57 VSSA power_in Analog ground pin where package pins allow, shorted to VSS otherwise.
58 P1.0 bidirectional GPIO pin P1.0 with CTB0 pad, TCPWM and SCB alternate functions.
59 P1.1 bidirectional GPIO pin P1.1 with CTB0 pad, TCPWM and SCB alternate functions.
60 P1.2 bidirectional GPIO pin P1.2 with CTB0 opamp output, TCPWM and SCB alternate functions.
61 P1.3 bidirectional GPIO pin P1.3 with CTB0 opamp output, TCPWM and SCB alternate functions.
62 P1.4 bidirectional GPIO pin P1.4 with CTB0 pad, TCPWM and SCB SPI select alternate functions.
63 P1.5 bidirectional GPIO pin P1.5 with CTB0 pad, TCPWM and SCB SPI select alternate functions.
64 P1.6 bidirectional GPIO pin P1.6 with CTB0 pad, TCPWM and SCB SPI select alternate functions.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TQFP-64(10x10)
Category Single Chip Microcomputer/Microcontroller
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog or digital supply relative to VSS VDD_ABS -0.5 6 V Absolute maximum 27
Direct digital core voltage input relative to VSSD VCCD_ABS -0.5 1.95 V Absolute maximum 27
GPIO voltage; VDDD or VDDA VGPIO_ABS -0.5 V Absolute maximum; max printed as VDD + 0.5 27
Current per GPIO IGPIO_ABS -25 25 mA Absolute maximum 27
GPIO injection current per pin IG-PIO_injection -0.5 0.5 mA Absolute maximum 27
Electrostatic discharge human body model ESD_HBM 2200 V 27
Electrostatic discharge charged device model ESD_CDM 500 V 27
Pin current for latch-up LU -140 140 mA 27
Power Supply Input Voltage (VDDA = VDDD = VDD) VDDD 1.8 5.5 V With regulator enabled 28
Power supply input voltage unregulated VDDD 1.71 1.8 1.89 V Internally unregulated Supply 28
External Regulator voltage (VCCD) bypass CEFC 1 1.3 1.6 µF X5R ceramic or better 28
Operating ambient temperature TA -40 25 105 °C 58
Operating junction temperature TJ -40 125 °C 58
Active mode execute from flash, CPU at 6 MHz IDD1 2.2 3.1 mA Execute from flash; CPU at 6 MHz 28
Active mode execute from flash, CPU at 12 MHz IDD2 3.7 4.8 mA Execute from flash; CPU at 12 MHz 28
Active mode execute from flash, CPU at 24 MHz IDD3 6.7 8 mA Execute from flash; CPU at 24 MHz 28
Active mode execute from flash, CPU at 48 MHz IDD4 12.8 14.5 mA Execute from flash; CPU at 48 MHz 28
Sleep mode I2C wakeup, WDT and Comparators on, regulator off IDD16 1.8 2.2 mA I2C wakeup, WDT, and Comparators on. Regulator Off. VDD = 1.71 V to 1.89 V, 6 MHz 28
Sleep mode I2C wakeup, WDT and Comparators on IDD17 1.7 2.1 mA I2C wakeup, WDT, and Comparators on. VDD = 1.8 V to 5.5 V, 6 MHz 28
Sleep mode I2C wakeup, WDT and Comparators on, regulator off IDD18 2.4 2.9 mA I2C wakeup, WDT, and Comparators on. Regulator Off. VDD = 1.71 V to 1.89 V, 12 MHz 28
Sleep mode I2C wakeup, WDT and Comparators on IDD19 2.3 2.8 mA I2C wakeup, WDT, and Comparators on. VDD = 1.8 V to 5.5 V, 12 MHz 28
Deep Sleep mode I2C wakeup and WDT on, regulator off IDD25 13.5 µA Deep Sleep Mode, -40°C to +60°C. I2C wakeup and WDT on. Regulator Off. VDD = 1.71 V to 1.89 V 28
Deep Sleep mode I2C wakeup and WDT on IDD26 1.3 20 µA Deep Sleep Mode, -40°C to +60°C. I2C wakeup and WDT on. VDD = 1.8 V to 3.6 V 28
Deep Sleep mode I2C wakeup and WDT on IDD27 20 µA Deep Sleep Mode, -40°C to +60°C. I2C wakeup and WDT on. VDD = 3.6 V to 5.5 V 28
Frequency variation with IMO set to 3 MHz (WCO-PLL calibrated) IMOWCO1 -0.6 0.6 % Does not include WCO tolerance. 50
Frequency variation with IMO set to 5 MHz (WCO-PLL calibrated) IMOWCO2 -0.4 0.4 % Does not include WCO tolerance. 50
Frequency variation with IMO set to 7 MHz or 9 MHz (WCO-PLL calibrated) IMOWCO3 -0.3 0.3 % Does not include WCO tolerance. 50
All other IMO frequency settings (WCO-PLL calibrated) IMOWCO4 -0.2 0.2 % Does not include WCO tolerance. 50
Duty cycle WCO TILODUTY 40 50 60 % Guaranteed by characterization. 49
32 kHz trimmed frequency FILOTRIM1 15 32 50 kHz ±60% with trim. 49
Trimmed internal reference to SAR VREFSAR -1 1 % Percentage of Vbg (1.024 V). Guaranteed by characterization. 51
Max frequency of 16-bit timer in a UDB pair FMAX-TIMER 48 MHz 51
Max frequency of 16-bit adder in a UDB pair FMAX-ADDER 48 MHz 51
Max frequency of 16-bit CRC/PRS in a UDB pair FMAX_CRC 48 MHz 51
Max frequency of 2-pass PLD function in a UDB pair FMAX_PLD 48 MHz 51
Clock switching from clk1 to clk2 in clk1 periods TCLKSWITCH 3 4 Periods Guaranteed by design. 51
PLL DC current In = 3 MHz, Out = 48 MHz IDD_PLL_48 530 610 µA In = 3 MHz, Out = 48 MHz 49
PLL DC current In = 3 MHz, Out = 24 MHz IDD_PLL_24 300 405 µA In = 3 MHz, Out = 24 MHz 49
PLL input frequency FPLLIN 1 48 MHz 49
PLL intermediate frequency; prescaler out FPLLINT 1 3 MHz 49
VCO output frequency before post-divide FPLLVCO 22.5 104 MHz 49
Lock time at startup PLLlocktime 250 µs 49
Period jitter for VCO ≥ 67 MHz Jperiod_1 150 ps Guaranteed By design. 49
Period jitter for VCO ≤ 67 MHz Jperiod_2 200 ps Guaranteed By design. 49
ILO operating current at 32 kHz IILO1 0.3 1.05 µA Guaranteed by characterization. 49
ILO startup time TSTARTILO1 2 ms Guaranteed by characterization. 49
External Clock input Frequency ExtClkFreq 0 48 MHz Guaranteed by characterization. 50
Duty cycle measured at VDD/2 ExtClkDuty 45 55 % Guaranteed by characterization. 50
Frequency tolerance FTOL 50 250 ppm With 20-ppm crystal. 50
Drive Level PD 1 µW 50
Startup time TSTART 500 ms 50
Crystal load capacitance CL 6 12.5 pF 50
Operating current (high power mode) IWCO1 8 uA 50
Block operating current IECO1 1.5 mA 50
Crystal frequency range FECO 4 33 MHz 50
Block current consumption IDD_CAN 200 µA 55
CAN Bit rate CAN_bits 1 Mbps Min 8-MHz clock 55
Package JA (64-pin TQFP) TJA 54 °C/W 58

CAD (KiCad official)

  • Symbol: CY8C4248AZI-L485
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: cy8c4248azi-l485-etched.step / cy8c4248azi-l485-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4248azi-l485.step / cy8c4248azi-l485.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (72 pp, sha256 f1b627a0d51ff44b, retrieved 2026-11-02, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF