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CY8C4247LTI-L475

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-68(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY8C4247LTI-L475

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-68(8x8)

CY8C4247LTI-L475 from Cypress Semicon, in a QFN-68(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7/VREF bidirectional GPIO P1.7 that also carries CTB0 pad 7 and the optional external SAR reference input sar_ext_vref.
2 P2.0 bidirectional GPIO P2.0 connected to SARMUX Port 2 input sarmux_pads[0], with TCPWM and SCB alternate functions per Table 2.
3 P2.1 bidirectional GPIO P2.1 connected to SARMUX Port 2 input sarmux_pads[1], with TCPWM and SCB alternate functions per Table 2.
4 P2.2 bidirectional GPIO P2.2 connected to SARMUX Port 2 input sarmux_pads[2], with TCPWM and SCB alternate functions per Table 2.
5 P2.3 bidirectional GPIO P2.3 connected to SARMUX Port 2 input sarmux_pads[3], with TCPWM and SCB alternate functions per Table 2.
6 P2.4 bidirectional GPIO P2.4 connected to SARMUX Port 2 input sarmux_pads[4], with TCPWM and SCB alternate functions per Table 2.
7 P2.5 bidirectional GPIO P2.5 connected to SARMUX Port 2 input sarmux_pads[5], with TCPWM and SCB alternate functions per Table 2.
8 P2.6 bidirectional GPIO P2.6 connected to SARMUX Port 2 input sarmux_pads[6], with TCPWM and SCB alternate functions per Table 2.
9 P2.7 bidirectional GPIO P2.7 connected to SARMUX Port 2 input sarmux_pads[7], with TCPWM alternate function per Table 2.
10 VSSA power_in Analog ground pin where package pins allow; shorted to VSS otherwise.
11 VDDA power_in Analog VDD pin that should be present before or concurrently with VDDD, and whose value must be equal to or higher than VDDD and VDDIO.
12 P6.0 bidirectional Overvoltage-tolerant GPIO (GPIO_OVT) P6.0 with TCPWM, SCB and CAN alternate functions per Table 2.
13 P6.1 bidirectional Overvoltage-tolerant GPIO (GPIO_OVT) P6.1 with TCPWM, SCB and CAN alternate functions per Table 2.
14 P6.2 bidirectional Overvoltage-tolerant GPIO (GPIO_OVT) P6.2 with TCPWM, SCB and CAN alternate functions per Table 2.
15 P6.3 bidirectional Overvoltage-tolerant GPIO (GPIO_OVT) P6.3 with TCPWM and SCB alternate functions per Table 2.
16 P6.4/P12.0 bidirectional Overvoltage-tolerant GPIO P6.4 shared with Port 12.0, which is an SIO pin, with TCPWM and SCB alternate functions per Table 2.
17 P6.5/P12.1 bidirectional Overvoltage-tolerant GPIO P6.5 shared with Port 12.1, which is an SIO pin, with TCPWM and SCB alternate functions per Table 2.
18 VSSIO power_in Ground pin for the I/O power domain (VSS ground pin per the datasheet power pin definitions).
19 P3.0 bidirectional GPIO P3.0 with TCPWM and SCB alternate functions per Table 2.
20 P3.1 bidirectional GPIO P3.1 with TCPWM and SCB alternate functions per Table 2.
21 P3.2 bidirectional GPIO P3.2 with TCPWM, SCB and SWD data (cpuss.swd_data) alternate functions per Table 2.
22 P3.3 bidirectional GPIO P3.3 with TCPWM, SCB and SWD clock (cpuss.swd_clk) alternate functions per Table 2.
23 P3.4 bidirectional GPIO P3.4 with TCPWM and SCB SPI select alternate functions per Table 2.
24 P3.5 bidirectional GPIO P3.5 with TCPWM and SCB SPI select alternate functions per Table 2.
25 P3.6 bidirectional GPIO P3.6 with TCPWM and SCB SPI select alternate functions per Table 2.
26 P3.7 bidirectional GPIO P3.7 with TCPWM alternate function per Table 2.
27 VDDIO power_in I/O pin power domain; it should not be present without VDDD.
28 P4.0 bidirectional GPIO P4.0 with SCB and CAN alternate functions per Table 2.
29 P4.1 bidirectional GPIO P4.1 with SCB and CAN alternate functions per Table 2.
30 P4.2 bidirectional GPIO P4.2 with CSD c_mod, SCB, CAN and LPCOMP alternate functions per Table 2.
31 P4.3 bidirectional GPIO P4.3 with CSD c_sh_tank, SCB and LPCOMP alternate functions per Table 2.
32 P4.4 bidirectional GPIO P4.4 with CAN and SCB SPI select alternate functions per Table 2.
33 P4.5 bidirectional GPIO P4.5 with CAN and SCB SPI select alternate functions per Table 2.
34 P4.6 bidirectional GPIO P4.6 with CAN and SCB SPI select alternate functions per Table 2.
35 P4.7 bidirectional GPIO P4.7 with no listed alternate function in Table 2.
36 D+/P13.0 bidirectional USB Full-Speed D+ data line, also GPIO P13.0; Port 13 pins require VBUS (P13.2) to be powered.
37 D-/P13.1 bidirectional USB Full-Speed D- data line, also GPIO P13.1; Port 13 pins require VBUS (P13.2) to be powered.
38 VBUS/P13.2 power_in USB VBUS voltage input, typically 5 V (4.35 V to 5.5 V range), with no constraint on VBUS relative to VDDD; also GPIO P13.2.
39 P7.0 bidirectional GPIO P7.0 that also carries the external crystal input srss.eco_in, with TCPWM and SCB alternate functions per Table 2.
40 P7.1 bidirectional GPIO P7.1 that also carries the external crystal output srss.eco_out, with TCPWM and SCB alternate functions per Table 2.
41 P7.2 bidirectional GPIO P7.2 with TCPWM and SCB alternate functions per Table 2.
42 P0.0 bidirectional GPIO P0.0 with LPCOMP analog input lpcomp.in_p[0] and CAN, USB VBUS-valid and SCB alternate functions per Table 2.
43 P0.1 bidirectional GPIO P0.1 with LPCOMP analog input lpcomp.in_n[0] and CAN and SCB alternate functions per Table 2.
44 P0.2 bidirectional GPIO P0.2 with LPCOMP analog input lpcomp.in_p[1] and SCB alternate function per Table 2.
45 P0.3 bidirectional GPIO P0.3 with LPCOMP analog input lpcomp.in_n[1] per Table 2.
46 P0.4 bidirectional GPIO P0.4 that also carries the watch crystal input wco_in, with SCB alternate functions per Table 2.
47 P0.5 bidirectional GPIO P0.5 that also carries the watch crystal output wco_out, with SCB alternate functions per Table 2.
48 P0.6 bidirectional GPIO P0.6 that also carries the external clock input srss.ext_clk, with SCB alternate functions per Table 2.
49 P0.7 bidirectional GPIO P0.7 that also carries the wakeup input srss.wakeup, with SCB and CAN alternate functions per Table 2.
50 XRES input External reset pin, reserved for external reset to avoid configuration conflicts during power-on or reconfiguration.
51 VCCD power_out Regulated digital supply at 1.8 V ±5%, to be bypassed to VSS with a 1 µF ceramic capacitor at the pin (1 µF to 1.6 µF X5R or better in unregulated supply mode).
52 VSSD power_in Ground pin for the digital section (VSS).
53 VDDD power_in Power supply for both analog and digital sections where no VDDA pin exists; supply range is 1.71 V to 5.5 V.
54 P5.0 bidirectional GPIO P5.0 connected to CTB1 pad 0 and CSD c_mod, with TCPWM and SCB alternate functions per Table 2.
55 P5.1 bidirectional GPIO P5.1 connected to CTB1 pad 1 and CSD c_sh_tank, with TCPWM and SCB alternate functions per Table 2.
56 P5.2 bidirectional GPIO P5.2 connected to CTB1 pad 2 and CTB1 opamp 0 output, with TCPWM, SCB and LPCOMP alternate functions per Table 2.
57 P5.3 bidirectional GPIO P5.3 connected to CTB1 pad 3 and CTB1 opamp 1 output, with TCPWM, SCB and LPCOMP alternate functions per Table 2.
58 P5.4 bidirectional GPIO P5.4 connected to CTB1 pad 4, with TCPWM and SCB SPI select alternate functions per Table 2.
59 P5.5 bidirectional GPIO P5.5 connected to CTB1 pad 5, with TCPWM and SCB SPI select alternate functions per Table 2.
60 VDDA power_in Analog VDD pin that should be present before or concurrently with VDDD, and whose value must be equal to or higher than VDDD and VDDIO.
61 VSSA power_in Analog ground pin where package pins allow; shorted to VSS otherwise.
62 P1.0 bidirectional GPIO P1.0 connected to CTB0 pad 0, with TCPWM and SCB alternate functions per Table 2.
63 P1.1 bidirectional GPIO P1.1 connected to CTB0 pad 1, with TCPWM and SCB alternate functions per Table 2.
64 P1.2 bidirectional GPIO P1.2 connected to CTB0 pad 2 and CTB0 opamp 0 output, with TCPWM and SCB alternate functions per Table 2.
65 P1.3 bidirectional GPIO P1.3 connected to CTB0 pad 3 and CTB0 opamp 1 output, with TCPWM and SCB alternate functions per Table 2.
66 P1.4 bidirectional GPIO P1.4 connected to CTB0 pad 4, with TCPWM and SCB SPI select alternate functions per Table 2.
67 P1.5 bidirectional GPIO P1.5 connected to CTB0 pad 5, with TCPWM and SCB SPI select alternate functions per Table 2.
68 P1.6 bidirectional GPIO P1.6 connected to CTB0 pad 6, with TCPWM and SCB SPI select alternate functions per Table 2.
69 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-68(8x8)
Category Single Chip Microcomputer/Microcontroller
Pins 69

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog or digital supply relative to VSS (VSSD = VSSA) VDD_ABS -0.5 6 V Absolute maximum 27
Direct digital core voltage input relative to VSSD VCCD_ABS -0.5 1.95 V Absolute maximum 27
GPIO voltage; VDDD or VDDA VGPIO_ABS -0.5 V Absolute maximum 27
Current per GPIO IGPIO_ABS -25 25 mA Absolute maximum 27
GPIO injection current per pin IG-PIO_injection -0.5 0.5 mA Absolute maximum 27
Electrostatic discharge human body model ESD_HBM 2200 V 27
Electrostatic discharge charged device model ESD_CDM 500 V 27
Pin current for latch-up LU -140 140 mA 27
Power Supply Input Voltage (VDDA = VDDD = VDD) VDDD 1.8 5.5 V With regulator enabled 28
Power supply input voltage unregulated VDDD 1.71 1.8 1.89 V Internally unregulated Supply 28
External Regulator voltage (VCCD) bypass CEFC 1 1.3 1.6 µF X5R ceramic or better 28
Active mode current, execute from flash IDD1 2.2 3.1 mA Execute from flash; CPU at 6 MHz 28
Active mode current, execute from flash IDD2 3.7 4.8 mA Execute from flash; CPU at 12 MHz 28
Active mode current, execute from flash IDD3 6.7 8 mA Execute from flash; CPU at 24 MHz 28
Active mode current, execute from flash IDD4 12.8 14.5 mA Execute from flash; CPU at 48 MHz 28
Sleep mode current IDD16 1.8 2.2 mA I2C wakeup, WDT, and Comparators on. Regulator Off. VDD = 1.71 V to 1.89 V, 6 MHz 28
Sleep mode current IDD17 1.7 2.1 mA I2C wakeup, WDT, and Comparators on. VDD = 1.8 V to 5.5 V, 6 MHz 28
Sleep mode current IDD18 2.4 2.9 mA I2C wakeup, WDT, and Comparators on. Regulator Off. VDD = 1.71 V to 1.89 V, 12 MHz 28
Sleep mode current IDD19 2.3 2.8 mA I2C wakeup, WDT, and Comparators on. VDD = 1.8 V to 5.5 V, 12 MHz 28
Deep Sleep mode current IDD25 13.5 µA Deep Sleep Mode, -40°C to +60°C. I2C wakeup and WDT on. Regulator Off. VDD = 1.71 V to 1.89 V 28
Deep Sleep mode current IDD26 1.3 20 µA Deep Sleep Mode, -40°C to +60°C. I2C wakeup and WDT on. VDD = 1.8 V to 3.6 V 28
Deep Sleep mode current IDD27 20 µA Deep Sleep Mode, -40°C to +60°C. I2C wakeup and WDT on. VDD = 3.6 V to 5.5 V 28
ILO operating current at 32 kHz IILO1 0.3 1.05 µA Guaranteed by characterization. 49
ILO leakage current IILOLEAK 2 15 nA Guaranteed by design. 49
ILO startup time TSTARTILO1 2 ms Guaranteed by characterization. 49
ILO duty cycle TILODUTY 40 50 60 % Guaranteed by characterization. 49
32 kHz trimmed frequency FILOTRIM1 15 32 50 kHz ±60% with trim. 49
PLL DC supply current, output 48 MHz IDD_PLL_48 530 610 µA In = 3 MHz, Out = 48 MHz 49
PLL DC supply current, output 24 MHz IDD_PLL_24 300 405 µA In = 3 MHz, Out = 24 MHz 49
PLL input frequency FPLLIN 1 48 MHz 49
PLL intermediate frequency; prescaler out FPLLINT 1 3 MHz 49
VCO output frequency before post-divide FPLLVCO 22.5 104 MHz 49
Lock time at startup PLLlocktime 250 µs 49
Period jitter for VCO ≥ 67 MHz Jperiod_1 150 ps Guaranteed By design. 49
Period jitter for VCO ≤ 67 MHz Jperiod_2 200 ps Guaranteed By design. 49
External Clock input Frequency ExtClkFreq 0 48 MHz Guaranteed by characterization. 50
Duty cycle; measured at VDD/2 ExtClkDuty 45 55 % Guaranteed by characterization. 50
Frequency variation with IMO set to 3 MHz (WCO-PLL calibrated) IMOWCO1 -0.6 0.6 % Does not include WCO tolerance. 50
Frequency variation with IMO set to 5 MHz (WCO-PLL calibrated) IMOWCO2 -0.4 0.4 % Does not include WCO tolerance. 50
Frequency variation with IMO set to 7 MHz or 9 MHz (WCO-PLL calibrated) IMOWCO3 -0.3 0.3 % Does not include WCO tolerance. 50
Frequency variation, all other IMO frequency settings (WCO-PLL calibrated) IMOWCO4 -0.2 0.2 % Does not include WCO tolerance. 50
Frequency tolerance FTOL 50 250 ppm With 20-ppm crystal. 50
Drive Level PD 1 µW 50
Startup time (WCO) TSTART 500 ms 50
Crystal load capacitance CL 6 12.5 pF 50
Operating current (WCO, high power mode) IWCO1 8 µA 50
ECO block operating current IECO1 1.5 mA 50
Crystal frequency range (ECO) FECO 4 33 MHz 50
Max frequency of 16-bit timer in a UDB pair FMAX-TIMER 48 MHz 51
Max frequency of 16-bit adder in a UDB pair FMAX-ADDER 48 MHz 51
Max frequency of 16-bit CRC/PRS in a UDB pair FMAX_CRC 48 MHz 51
Max frequency of 2-pass PLD function in a UDB pair FMAX_PLD 48 MHz 51
Number of wait states at 48 MHz TWS48 2 CPU execution from Flash. Guaranteed by characterization. 51
Number of wait states at 24 MHz TWS24 1 CPU execution from Flash. Guaranteed by characterization. 51
Trimmed internal reference to SAR VREFSAR -1 1 % Percentage of Vbg (1.024 V). Guaranteed by characterization. 51
CAN block current consumption IDD_CAN 200 µA 55
CAN bit rate (min 8-MHz clock) CAN_bits 1 Mbps Min 8-MHz clock 55
Operating ambient temperature TA -40 25 105 °C 58
Operating junction temperature TJ -40 125 °C 58
Package thermal resistance junction-to-ambient, 68-pin QFN TJA 17 °C/W 58

CAD (KiCad official)

  • Symbol: CY8C4247LTI-L475
  • Footprint: Package_DFN_QFN:QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm
  • 3D model: QFN-68(8x8) (KiCad packages3D, STEP)
  • 3D model files: cy8c4247lti-l475-etched.step / cy8c4247lti-l475-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4247lti-l475.step / cy8c4247lti-l475.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (72 pp, sha256 f1b627a0d51ff44b, retrieved 2026-10-29, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF