CY8C4246PVI-DS402 from Cypress Semicon, in a SSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P1.0	bidirectional	GPIO port 1 bit 0 with alternate functions TCPWM2 line, SCB0 UART RX, I2C SCL or SPI MOSI.
2	P1.1	bidirectional	GPIO port 1 bit 1 with alternate functions TCPWM2 complementary line, SCB0 UART TX, I2C SDA or SPI MISO.
3	P1.2	bidirectional	GPIO port 1 bit 2 with alternate functions TCPWM3 line, SCB0 UART CTS or SPI clock.
4	P1.3	bidirectional	GPIO port 1 bit 3 with alternate functions TCPWM3 complementary line, SCB0 UART RTS or SPI select0.
5	P2.2	bidirectional	GPIO port 2 bit 2 with PRGIO io[2] and SCB2 UART RX, I2C SCL or SPI MOSI.
6	P2.3	bidirectional	GPIO port 2 bit 3 with PRGIO io[3] and SCB2 UART TX, I2C SDA or SPI MISO.
7	P2.4	bidirectional	GPIO port 2 bit 4 with PRGIO io[4], TCPWM0 line, SCB2 UART CTS or SPI clock, and lpcomp comp[0] output.
8	P2.5	bidirectional	GPIO port 2 bit 5 with PRGIO io[5], TCPWM0 complementary line, SCB2 UART RTS or SPI select0.
9	P2.6	bidirectional	GPIO port 2 bit 6 with PRGIO io[6], TCPWM1 line or SCB2 SPI select1.
10	P2.7	bidirectional	GPIO port 2 bit 7 with PRGIO io[7], TCPWM1 complementary line or SCB2 SPI select2.
11	P3.0	bidirectional	GPIO port 3 bit 0 with TCPWM0 line and SCB1 UART RX, I2C SCL or SPI MOSI.
12	P3.1	bidirectional	GPIO port 3 bit 1 with TCPWM0 complementary line and SCB1 UART TX, I2C SDA or SPI MISO.
13	P3.2	bidirectional	GPIO port 3 bit 2 with TCPWM1 line, SCB1 UART CTS or SPI clock, and SWD_IO (swd_data).
14	P3.3	bidirectional	GPIO port 3 bit 3 with TCPWM1 complementary line, SCB1 UART RTS or SPI select0, and SWD_CLK (swd_clk).
15	P3.4	bidirectional	GPIO port 3 bit 4 with SCB1 SPI select1 alternate function.
16	NC	unconnected	No-connect in the 28-pin SSOP package.
17	NC	unconnected	No-connect in the 28-pin SSOP package.
18	NC	unconnected	No-connect in the 28-pin SSOP package.
19	P0.0	bidirectional	GPIO port 0 bit 0 with lpcomp in_p[0] analog input, TCPWM2 line or SCB0 SPI select1.
20	P0.1	bidirectional	GPIO port 0 bit 1 with lpcomp in_n[0] analog input, TCPWM2 complementary line or SCB0 SPI select2.
21	P0.2	bidirectional	GPIO port 0 bit 2 with TCPWM3 line or SCB0 SPI select3.
22	P0.4	bidirectional	GPIO port 0 bit 4 with SCB1 UART RX, I2C SCL or SPI MOSI.
23	P0.5	bidirectional	GPIO port 0 bit 5 with SCB1 UART TX, I2C SDA or SPI MISO.
24	P0.6	bidirectional	GPIO port 0 bit 6 with external clock input, SCB1 UART CTS or SPI clock.
25	XRES	input	Dedicated external reset pin reserved to avoid configuration conflicts with multiple pin functions during power-on or reconfiguration.
26	VCCD	power_out	Regulated digital supply output, 1.8 V ±5% if supplied externally, bypassed with a 0.1-µF ceramic capacitor to VSS.
27	VDDD	power_in	Power supply for the chip, 1.71 to 5.5 V, bypassed with 0.1-µF ceramic at each pin plus a 1 to 10 µF bulk capacitor.
28	VSSD	power_in	Ground pin.

Key specifications

Parameter	Value
Manufacturer	Cypress Semicon
Package	SSOP-28
Category	Solders / Accessories / Batteries
Pins	28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog or digital supply relative to VSS	VDD_ABS	-0.5		6	V	VSSD = VSSA	12
Direct digital core voltage input relative to VSSD	VCCD_ABS	-0.5		1.95	V		12
GPIO voltage (min only; max is VDD+0.5)	VGPIO_ABS	-0.5			V	VDDD or VDDA	12
Current per GPIO	IGPIO_ABS	-25		25	mA		12
GPIO injection current per pin	IG-PIO_injection	-0.5		0.5	mA		12
ESD human body model	ESD_HBM	2200			V		12
ESD charged device model	ESD_CDM	500			V		12
Pin current for latch-up	LU	-140		140	mA		12
Power supply input voltage unregulated	VDDD	1.8		5.5	V	With on-chip internal regulator enabled	12
Power supply input voltage externally regulated	VDDD	1.71	1.8	1.89	V	Externally regulated within this range	12
Output voltage (for core logic)	VCCD		1.8		V		12
External regulator voltage bypass	CEFC		0.1		µF	X5R ceramic or better	12
Power supply decoupling capacitor	CEXC		1		µF	X5R ceramic or better	12
Active mode current, CPU at 6 MHz	IDD1		2.1	2.85	mA	Execute from flash; CPU at 6 MHz	12
Active mode current, CPU at 12 MHz	IDD2		3.6	4	mA	Execute from flash; CPU at 12 MHz	12
Active mode current, CPU at 24 MHz	IDD3		5.3	6	mA	Execute from flash; CPU at 24 MHz	12
Active mode current, CPU at 48 MHz	IDD4		9.8	13	mA	Execute from flash; CPU at 48 MHz	12
Sleep current, regulator off, 6 MHz	IDD16		1.45	1.65	mA	I2C wakeup, WDT, and comparators on. Regulator off. VDD = 1.71 to 1.89, 6 MHz	12
Sleep current, 6 MHz	IDD17		1.8	2.45	mA	I2C wakeup, WDT, and comparators on. VDD = 1.8 to 5.5, 6 MHz	12
Sleep current, regulator off, 12 MHz	IDD18		1.6	1.9	mA	I2C wakeup, WDT, and comparators on. Regulator off. VDD = 1.71 to 1.89, 12 MHz	12
Sleep current, 12 MHz	IDD19		2	2.7	mA	I2C wakeup, WDT, and comparators on. VDD = 1.8 to 5.5, 12 MHz	13
Deep Sleep current, regulator off, -40 to +60 °C	IDD25		2	15	µA	I2C wakeup and WDT on. Regulator off. VDD = 1.71 to 1.89	13
Deep Sleep current, -40 to +60 °C, VDD 1.8 to 3.6 V	IDD26		2	15	µA	I2C wakeup and WDT on. VDD = 1.8 to 3.6	13
Deep Sleep current, -40 to +60 °C, VDD 3.6 to 5.5 V	IDD27		2	15	µA	I2C wakeup and WDT on. VDD = 3.6 to 5.5	13
Deep Sleep current, +85 °C, regulator off	IDD28		4	45	µA	I2C wakeup and WDT on. Regulator off. VDD = 1.71 to 1.89	13
Deep Sleep current, +85 °C, VDD 1.8 to 3.6 V	IDD29		4	45	µA	I2C wakeup and WDT on. VDD = 1.8 to 3.6	13
Deep Sleep current, +85 °C, VDD 3.6 to 5.5 V	IDD30		4	45	µA	I2C wakeup and WDT on. VDD = 3.6 to 5.5	13
Supply current while XRES asserted	IDD_XR		2	5	mA		13
CPU frequency	FCPU			48	MHz	1.71 ≤ VDD ≤ 5.5	13
Wakeup from sleep mode	TSLEEP		0		µs	Guaranteed by characterization	13
Wakeup from Deep Sleep mode	TDEEPSLEEP			35	µs	Guaranteed by characterization	13
External reset pulse width	TRESETWIDTH	1			µs	Guaranteed by characterization	13
LVTTL input high threshold	VIH	2			V	LVTTL input, VDDD ≥ 2.7 V	13
LVTTL input low threshold	VIL			0.8	V	LVTTL input, VDDD ≥ 2.7 V	13
Output voltage low level	VOL			0.6	V	IOL = 4 mA at 1.8 V VDDD	13
ILO startup time	TSTARTILO1			2	ms	Guaranteed by characterization	20
ILO duty cycle	TILODUTY	40	50	60	%	Guaranteed by characterization	20
ILO operating frequency	FILOTRIM1	20	40	80	kHz		20
External clock input frequency	ExtClkFreq	0		48	MHz	Guaranteed by characterization	20
External clock duty cycle	ExtClkDuty	45		55	%	Measured at VDD/2; Guaranteed by characterization	20
Max frequency of 16-bit timer in a UDB pair	FMAX-TIMER			48	MHz		20
Max frequency of 16-bit adder in a UDB pair	FMAX-ADDER			48	MHz		20
Max frequency of 16-bit CRC/PRS in a UDB pair	FMAX_CRC			48	MHz		20
Max frequency of 2-pass PLD function in a UDB pair	FMAX_PLD			48	MHz		20
Prop. delay clock in to data out	TCLK_OUT_UDB1		15		ns	at 25 °C, Typ.	20
Prop. delay clock in to data out, worst case	TCLK_OUT_UDB2		25		ns	Worst case	20
Number of wait states at 48 MHz	TWS48	2				CPU execution from Flash	20
Number of wait states at 24 MHz	TWS24	1				CPU execution from Flash	20
Operating ambient temperature	TA	-40	25	85	°C		23
Operating junction temperature	TJ	-40		100	°C		23
Package θJA (28-pin SSOP)	TJA		67		°C/Watt		23
Package θJC (28-pin SSOP)	TJC		26		°C/Watt		23

CAD (KiCad official)

Symbol: CY8C4246PVI-DS402
Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
3D model: SSOP-28 (KiCad packages3D, STEP)
3D model files: cy8c4246pvi-ds402-etched.step / cy8c4246pvi-ds402-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4246pvi-ds402.step / cy8c4246pvi-ds402.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cypress Semicon datasheet (29 pp, sha256 7313ee9c00c7c45d, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CY8C4246PVI-DS402

Verified CY8C4246PVI-DS402

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README