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CY8C4246AZI-L433

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy8c4246azi-l433factory-2.0.0extractor-text

Verified CY8C4246AZI-L433

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY8C4246AZI-L433 · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 72-page datasheet
  • ✓distributor: lcsc C2944636, digikey 448-CY8C4246AZI-L433-ND, mouser 727-CY8C4246AZI-L433
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-fyhmoc6_/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy8c4246azi-l433.kicad_sym✓ cy8c4246azi-l433.kicad_mod✓ cy8c4246azi-l433.step
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3D Model

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Symbol & Footprint

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Contents

README

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CY8C4246AZI-L433

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-48(7x7)

CY8C4246AZI-L433 from Cypress Semicon, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7/VREF bidirectional GPIO P1.7, which also carries CTB0 pad 7 and the external SAR reference input sar_ext_vref (Table 2).
2 P2.0 bidirectional GPIO P2.0 with analog input sarmux_pads[0] to the SAR ADC mux, plus SCB1 UART RX / I2C SCL / SPI MOSI alternates.
3 P2.1 bidirectional GPIO P2.1 with analog input sarmux_pads[1] to the SAR ADC mux, plus SCB1 UART TX / I2C SDA / SPI MISO alternates.
4 P2.2 bidirectional GPIO P2.2 with analog input sarmux_pads[2] to the SAR ADC mux, plus SCB1 UART CTS / SPI CLK alternates.
5 P2.3 bidirectional GPIO P2.3 with analog input sarmux_pads[3] to the SAR ADC mux, plus SCB1 UART RTS / SPI SELECT0 alternates.
6 P2.4 bidirectional GPIO P2.4 with analog input sarmux_pads[4] to the SAR ADC mux, plus TCPWM line[0] and SCB1 SPI SELECT1 alternates.
7 P2.5 bidirectional GPIO P2.5 with analog input sarmux_pads[5] to the SAR ADC mux, plus TCPWM line_compl[0] and SCB1 SPI SELECT2 alternates.
8 P2.6 bidirectional GPIO P2.6 with analog input sarmux_pads[6] to the SAR ADC mux, plus TCPWM line[1] and SCB1 SPI SELECT3 alternates.
9 P2.7 bidirectional GPIO P2.7 with analog input sarmux_pads[7] to the SAR ADC mux, plus TCPWM line_compl[1] alternate.
10 VSSD power_in Ground pin for the digital section.
11 NC unconnected No connect on the 48-pin TQFP packages.
12 P3.0 bidirectional GPIO P3.0 with TCPWM line[0] and SCB1 UART RX / I2C SCL / SPI MOSI alternates.
13 P3.1 bidirectional GPIO P3.1 with TCPWM line_compl[0] and SCB1 UART TX / I2C SDA / SPI MISO alternates.
14 P3.2 bidirectional GPIO P3.2 with TCPWM line[1], SCB1 UART CTS / SPI CLK, and the cpuss.swd_data alternate.
15 NC unconnected No connect on the 48-pin TQFP packages.
16 P3.3 bidirectional GPIO P3.3 with TCPWM line_compl[1], SCB1 UART RTS / SPI SELECT0, and the cpuss.swd_clk alternate.
17 P3.4 bidirectional GPIO P3.4 with TCPWM line[2] and SCB1 SPI SELECT1 alternates.
18 P3.5 bidirectional GPIO P3.5 with TCPWM line_compl[2] and SCB1 SPI SELECT2 alternates.
19 P3.6 bidirectional GPIO P3.6 with TCPWM line[3] and SCB1 SPI SELECT3 alternates.
20 P3.7 bidirectional GPIO P3.7 with TCPWM line_compl[3] alternate.
21 VDDIO power_in I/O pin power domain; it should not be present without VDDD.
22 P4.0 bidirectional GPIO P4.0 with SCB0 UART RX / I2C SCL / SPI MOSI and CAN0 RX alternates.
23 D+/P13.0 bidirectional USB full-speed D+ data line (USBDP) on GPIO P13.0; Port 13 pins require VBUS (P13.2) to be powered.
24 D-/P13.1 bidirectional USB full-speed D- data line (USBDM) on GPIO P13.1; Port 13 pins require VBUS (P13.2) to be powered.
25 VBUS/P13.2 power_in USB VBUS input, typically 5 V (4.35 V to 5.5 V range), with no constraint relative to VDDD; it must be powered for Port 13 operation.
26 P7.0 bidirectional GPIO P7.0 with ECO input srss.eco_in, TCPWM line[0] and SCB3 UART RX / I2C SCL / SPI MOSI alternates.
27 P7.1 bidirectional GPIO P7.1 with ECO output srss.eco_out, TCPWM line_compl[0] and SCB3 UART TX / I2C SDA / SPI MISO alternates.
28 P0.0 bidirectional GPIO P0.0 with analog input lpcomp.in_p[0] and alternates can[1].can_rx and usb.vbus_valid.
29 P0.1 bidirectional GPIO P0.1 with analog input lpcomp.in_n[0] and alternates can[1].can_tx and scb[0].spi_select2.
30 P0.2 bidirectional GPIO P0.2 with analog input lpcomp.in_p[1] and alternate scb[0].spi_select3.
31 P0.3 bidirectional GPIO P0.3 with analog input lpcomp.in_n[1].
32 P0.4 bidirectional GPIO P0.4 with watch crystal input wco_in and SCB1 UART RX / I2C SCL / SPI MOSI alternates.
33 P0.5 bidirectional GPIO P0.5 with watch crystal output wco_out and SCB1 UART TX / I2C SDA / SPI MISO alternates.
34 P0.6 bidirectional GPIO P0.6 with external clock input srss.ext_clk and SCB1 UART CTS / SPI CLK alternates.
35 P0.7 bidirectional GPIO P0.7 with SCB1 UART RTS, CAN1 tx_enb_n, srss.wakeup and SCB1 SPI SELECT0 alternates.
36 XRES input External reset pin, reserved for external reset to avoid configuration and multiple-pin-function conflicts during power-on or reconfiguration.
37 VCCD power_out Regulated digital supply of 1.8 V ±5%; in unregulated supply mode it must be bypassed to ground with an external 1 µF to 1.6 µF X5R ceramic capacitor.
38 VSSD power_in Ground pin for the digital section.
39 VDDD power_in Power supply for both analog and digital sections where there is no VDDA pin, operating over 1.71 V to 5.5 V.
40 VDDA power_in Analog VDD pin where package pins allow; it should be present before or concurrently with VDDD and be equal to or higher than VDDD and VDDIO.
41 VSSA power_in Analog ground pin where package pins allow; shorted to VSS otherwise.
42 P1.0 bidirectional GPIO P1.0 with CTB0 pad 0, TCPWM line[2] and SCB0 UART RX / I2C SCL / SPI MOSI alternates.
43 P1.1 bidirectional GPIO P1.1 with CTB0 pad 1, TCPWM line_compl[2] and SCB0 UART TX / I2C SDA / SPI MISO alternates.
44 P1.2 bidirectional GPIO P1.2 with CTB0 pad 2, CTB0 OA0 output (10x), TCPWM line[3] and SCB0 UART CTS / SPI CLK alternates.
45 P1.3 bidirectional GPIO P1.3 with CTB0 pad 3, CTB0 OA1 output (10x), TCPWM line_compl[3] and SCB0 UART RTS / SPI SELECT0 alternates.
46 P1.4 bidirectional GPIO P1.4 with CTB0 pad 4, TCPWM line[6] and SCB0 SPI SELECT1 alternates.
47 P1.5 bidirectional GPIO P1.5 with CTB0 pad 5, TCPWM line_compl[6] and SCB0 SPI SELECT2 alternates.
48 P1.6 bidirectional GPIO P1.6 with CTB0 pad 6, TCPWM line[7] and SCB0 SPI SELECT3 alternates.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TQFP-48(7x7)
Category Single Chip Microcomputer/Microcontroller
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Absolute maximum supply voltage (analog or digital) relative to VSS VDD_ABS -0.5 6 V Absolute maximum 27
Direct digital core voltage input relative to VSSD VCCD_ABS -0.5 1.95 V Absolute maximum 27
GPIO voltage; VDDD or VDDA VGPIO_ABS -0.5 V Absolute maximum 27
Current per GPIO IGPIO_ABS -25 25 mA Absolute maximum 27
GPIO injection current per pin IGPIO_injection -0.5 0.5 mA Absolute maximum 27
Electrostatic discharge human body model ESD_HBM 2200 V 27
Electrostatic discharge charged device model ESD_CDM 500 V 27
Pin current for latch-up LU -140 140 mA 27
Power supply input voltage (VDDA = VDDD = VDD) VDDD 1.8 5.5 V VDDA = VDDD = VDD; with regulator enabled 28
Power supply input voltage unregulated VDDD 1.71 1.8 1.89 V Internally unregulated supply 28
External regulator voltage (VCCD) bypass CEFC 1 1.3 1.6 µF X5R ceramic or better 28
Active mode current, execute from flash, CPU at 6 MHz IDD1 2.2 3.1 mA Execute from flash; CPU at 6 MHz 28
Active mode current, execute from flash, CPU at 12 MHz IDD2 3.7 4.8 mA Execute from flash; CPU at 12 MHz 28
Active mode current, execute from flash, CPU at 24 MHz IDD3 6.7 8 mA Execute from flash; CPU at 24 MHz 28
Active mode current, execute from flash, CPU at 48 MHz IDD4 12.8 14.5 mA Execute from flash; CPU at 48 MHz 28
Sleep mode current, I2C wakeup, WDT and comparators on IDD16 1.8 2.2 mA Sleep mode; I2C wakeup, WDT, comparators on; regulator off; VDD = 1.71 V to 1.89 V, 6 MHz 28
Sleep mode current, I2C wakeup, WDT and comparators on IDD17 1.7 2.1 mA Sleep mode; I2C wakeup, WDT, comparators on; VDD = 1.8 V to 5.5 V, 6 MHz 28
Sleep mode current, I2C wakeup, WDT and comparators on IDD18 2.4 2.9 mA Sleep mode; I2C wakeup, WDT, comparators on; regulator off; VDD = 1.71 V to 1.89 V, 12 MHz 28
Sleep mode current, I2C wakeup, WDT and comparators on IDD19 2.3 2.8 mA Sleep mode; I2C wakeup, WDT, comparators on; VDD = 1.8 V to 5.5 V, 12 MHz 28
Deep Sleep mode current, I2C wakeup and WDT on IDD25 13.5 µA Deep Sleep mode, -40°C to +60°C; I2C wakeup and WDT on; regulator off; VDD = 1.71 V to 1.89 V 28
Deep Sleep mode current, I2C wakeup and WDT on IDD26 1.3 20 µA Deep Sleep mode, -40°C to +60°C; I2C wakeup and WDT on; VDD = 1.8 V to 3.6 V 28
Deep Sleep mode current, I2C wakeup and WDT on IDD27 20 µA Deep Sleep mode, -40°C to +60°C; I2C wakeup and WDT on; VDD = 3.6 V to 5.5 V 28
ILO operating current at 32 kHz IILO1 0.3 1.05 µA Guaranteed by characterization. 49
ILO leakage current IILOLEAK 2 15 nA Guaranteed by design. 49
ILO startup time TSTARTILO1 2 ms Guaranteed by characterization. 49
ILO duty cycle TILODUTY 40 50 60 % Guaranteed by characterization. 49
32 kHz trimmed frequency FILOTRIM1 15 32 50 kHz ±60% with trim. 49
PLL current, In = 3 MHz, Out = 48 MHz IDD_PLL_48 530 610 µA In = 3 MHz, Out = 48 MHz 49
PLL current, In = 3 MHz, Out = 24 MHz IDD_PLL_24 300 405 µA In = 3 MHz, Out = 24 MHz 49
PLL input frequency FPLLIN 1 48 MHz 49
PLL intermediate frequency; prescaler out FPLLINT 1 3 MHz 49
VCO output frequency before post-divide FPLLVCO 22.5 104 MHz 49
VCO output post-divider range; PLL output frequency is FPLLVCO/DIVVCO DIVVCO 1 8 , 49
Lock time at startup PLLlocktime 250 µs 49
Period jitter for VCO ≥ 67 MHz Jperiod_1 150 ps For VCO ≥ 67 MHz. Guaranteed by design. 49
Period jitter for VCO ≤ 67 MHz Jperiod_2 200 ps For VCO ≤ 67 MHz. Guaranteed by design. 49
External clock input frequency ExtClkFreq 0 48 MHz Guaranteed by characterization. 50
External clock duty cycle; measured at VDD/2 ExtClkDuty 45 55 % Guaranteed by characterization. 50
IMO WCO-PLL calibrated frequency variation, IMO set to 3 MHz IMOWCO1 -0.6 0.6 % IMO WCO-PLL calibrated mode; IMO set to 3 MHz; does not include WCO tolerance. 50
IMO WCO-PLL calibrated frequency variation, IMO set to 5 MHz IMOWCO2 -0.4 0.4 % IMO WCO-PLL calibrated mode; IMO set to 5 MHz; does not include WCO tolerance. 50
IMO WCO-PLL calibrated frequency variation, IMO set to 7 MHz or 9 MHz IMOWCO3 -0.3 0.3 % IMO WCO-PLL calibrated mode; IMO set to 7 MHz or 9 MHz; does not include WCO tolerance. 50
IMO WCO-PLL calibrated frequency variation, all other IMO settings IMOWCO4 -0.2 0.2 % IMO WCO-PLL calibrated mode; all other IMO frequency settings; does not include WCO tolerance. 50
Crystal frequency tolerance FTOL 50 250 ppm With 20-ppm crystal. 50
WCO drive level PD 1 µW 50
WCO startup time TSTART 500 ms 50
WCO crystal load capacitance CL 6 12.5 pF 50
WCO operating current (high power mode) IWCO1 8 µA High power mode 50
ECO block operating current IECO1 1.5 mA 50
ECO crystal frequency range FECO 4 33 MHz 50
Max frequency of 16-bit timer in a UDB pair FMAX-TIMER 48 MHz 51
Max frequency of 16-bit adder in a UDB pair FMAX-ADDER 48 MHz 51
Max frequency of 16-bit CRC/PRS in a UDB pair FMAX_CRC 48 MHz 51
Max frequency of 2-pass PLD function in a UDB pair FMAX_PLD 48 MHz 51
Number of wait states at 48 MHz TWS48 2 CPU execution from flash. Guaranteed by characterization. 51
Number of wait states at 24 MHz TWS24 1 CPU execution from flash. Guaranteed by characterization. 51
Trimmed internal reference to SAR VREFSAR -1 1 % Percentage of Vbg (1.024 V). Guaranteed by characterization. 51
Clock switching from clk1 to clk2 in clk1 periods TCLKSWITCH 3 4 Periods Guaranteed by design. 51
Operating ambient temperature TA -40 25 105 °C 58
Operating junction temperature TJ -40 125 °C 58
Package thermal resistance junction-to-ambient (48-pin TQFP) TJA 67 °C/W 58

CAD (KiCad official)

  • Symbol: CY8C4246AZI-L433
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: cy8c4246azi-l433-etched.step / cy8c4246azi-l433-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4246azi-l433.step / cy8c4246azi-l433.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (72 pp, sha256 f1b627a0d51ff44b, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF