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CY8C4245AXI-483

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Infineon Cypress Semicon Microcontrollers (MCU/MPU/SOC), TQFP-44(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY8C4245AXI-483

Infineon Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · TQFP-44(10x10)

CY8C4245AXI-483 from Infineon Cypress Semicon, in a TQFP-44(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSS power_in Ground pin for the device.
2 P2.0 bidirectional Port 2 Pin 0 GPIO, also usable for LCD, CSD CapSense and SAR mux input sarmux.0; Port 2 comprises the high-speed analog inputs for the SAR mux.
3 P2.1 bidirectional Port 2 Pin 1 GPIO, also usable for LCD, CSD CapSense and SAR mux input sarmux.1.
4 P2.2 bidirectional Port 2 Pin 2 GPIO, also usable for LCD, CSD CapSense and SAR mux input sarmux.2.
5 P2.3 bidirectional Port 2 Pin 3 GPIO, also usable for LCD, CSD CapSense and SAR mux input sarmux.3.
6 P2.4 bidirectional Port 2 Pin 4 GPIO, also usable for LCD, CSD CapSense, SAR mux input sarmux.4, and TCPWM0 positive output tcpwm0_p[1].
7 P2.5 bidirectional Port 2 Pin 5 GPIO, also usable for LCD, CSD CapSense, SAR mux input sarmux.5, and TCPWM0 negative output tcpwm0_n[1].
8 P2.6 bidirectional Port 2 Pin 6 GPIO, also usable for LCD, CSD CapSense, SAR mux input sarmux.6, and TCPWM1 positive output tcpwm1_p[1].
9 P2.7 bidirectional Port 2 Pin 7 GPIO, also usable for LCD, CSD CapSense, SAR mux input sarmux.7, and TCPWM1 negative output tcpwm1_n[1].
10 VSS power_in Ground pin for the device.
11 P3.0 bidirectional Port 3 Pin 0 GPIO, also usable for LCD, CSD, TCPWM0 positive output, and SCB1 UART RX, I2C SCL or SPI MOSI.
12 P3.1 bidirectional Port 3 Pin 1 GPIO, also usable for LCD, CSD, TCPWM0 negative output, and SCB1 UART TX, I2C SDA or SPI MISO.
13 P3.2 bidirectional Port 3 Pin 2 GPIO, also usable for LCD, CSD, TCPWM1 positive output, SWD I/O (swd_io[0]) and SCB1 SPI clock; this pin is an SWD pin after boot (reset).
14 P3.3 bidirectional Port 3 Pin 3 GPIO, also usable for LCD, CSD, TCPWM1 negative output, SWD clock (swd_clk[0]) and SCB1 SPI slave select 0; this pin is an SWD pin after boot (reset).
15 P3.4 bidirectional Port 3 Pin 4 GPIO, also usable for LCD, CSD, TCPWM2 positive output, and SCB1 SPI slave select 1.
16 P3.5 bidirectional Port 3 Pin 5 GPIO, also usable for LCD, CSD, TCPWM2 negative output, and SCB1 SPI slave select 2.
17 P3.6 bidirectional Port 3 Pin 6 GPIO, also usable for LCD, CSD, TCPWM3 positive output, and SCB1 SPI slave select 3.
18 P3.7 bidirectional Port 3 Pin 7 GPIO, also usable for LCD, CSD and TCPWM3 negative output.
19 VDDD power_in Digital supply, 1.8 to 5.5 V; supplies both analog and digital sections where no VDDA pin is present.
20 P4.0 bidirectional Port 4 Pin 0 GPIO, also usable for LCD, CSD, and SCB0 UART RX, I2C SCL or SPI MOSI.
21 P4.1 bidirectional Port 4 Pin 1 GPIO, also usable for LCD, CSD, and SCB0 UART TX, I2C SDA or SPI MISO.
22 P4.2 bidirectional Port 4 Pin 2 GPIO, also usable for LCD, CSD (csd_c_mod modulator capacitor connection), and SCB0 SPI clock.
23 P4.3 bidirectional Port 4 Pin 3 GPIO, also usable for LCD, CSD (csd_c_sh_tank connection), and SCB0 SPI slave select 0.
24 P0.0 bidirectional Port 0 Pin 0 GPIO, also usable for LCD, CSD, SCB0 SPI slave select 1, and comparator 1 positive input comp1_inp.
25 P0.1 bidirectional Port 0 Pin 1 GPIO, also usable for LCD, CSD, SCB0 SPI slave select 2, and comparator 1 negative input comp1_inn.
26 P0.2 bidirectional Port 0 Pin 2 GPIO, also usable for LCD, CSD, SCB0 SPI slave select 3, and comparator 2 positive input comp2_inp.
27 P0.3 bidirectional Port 0 Pin 3 GPIO, also usable for LCD, CSD, and comparator 2 negative input comp2_inn.
28 P0.4 bidirectional Port 0 Pin 4 GPIO, also usable for LCD, CSD, and SCB1 UART RX, I2C SCL or SPI MOSI (alternate [1] mapping).
29 P0.5 bidirectional Port 0 Pin 5 GPIO, also usable for LCD, CSD, and SCB1 UART TX, I2C SDA or SPI MISO (alternate [1] mapping).
30 P0.6 bidirectional Port 0 Pin 6 GPIO, also usable for LCD, CSD, SCB1 SPI clock (alternate [1] mapping), and external clock input ext_clk.
31 P0.7 bidirectional Port 0 Pin 7 GPIO, also usable for LCD, CSD, SCB1 SPI slave select 0 (alternate [1] mapping), and wakeup input.
32 XRES input Active-low chip reset input with an internal pull-up resistor that is always enabled; reset pulse width must be at least 1 µs.
33 VCCD power_out Regulated 1.8 V digital core supply output (1.8 V ±5%) that must be bypassed with a 1-µF to 1.6-µF X5R ceramic capacitor.
34 VDDD power_in Digital supply, 1.8 to 5.5 V; must be shorted to VDDA in unregulated external supply mode and VDDA must be equal to or higher than VDDD at power-up.
35 VDDA power_in Analog supply, 1.8 to 5.5 V, equal to VDDD.
36 VSSA power_in Analog ground pin.
37 P1.0 bidirectional Port 1 Pin 0 GPIO, also usable for LCD, CSD, CTB opamp 0 non-inverting input ctb.oa0.inp, and TCPWM2 positive output tcpwm2_p[1].
38 P1.1 bidirectional Port 1 Pin 1 GPIO, also usable for LCD, CSD, CTB opamp 0 inverting input ctb.oa0.inm, and TCPWM2 negative output tcpwm2_n[1].
39 P1.2 bidirectional Port 1 Pin 2 GPIO, also usable for LCD, CSD, CTB opamp 0 output ctb.oa0.out, and TCPWM3 positive output tcpwm3_p[1].
40 P1.3 bidirectional Port 1 Pin 3 GPIO, also usable for LCD, CSD, CTB opamp 1 output ctb.oa1.out, and TCPWM3 negative output tcpwm3_n[1].
41 P1.4 bidirectional Port 1 Pin 4 GPIO, also usable for LCD, CSD, and CTB opamp 1 inverting input ctb.oa1.inm.
42 P1.5 bidirectional Port 1 Pin 5 GPIO, also usable for LCD, CSD, and CTB opamp 1 non-inverting input ctb.oa1.inp.
43 P1.6 bidirectional Port 1 Pin 6 GPIO, also usable for LCD, CSD, and CTB opamp 0 alternate non-inverting input ctb.oa0.inp_alt.
44 P1.7/VREF bidirectional Port 1 Pin 7 GPIO, also usable as external SAR reference input/bypass ext_vref, LCD, CSD, and CTB opamp 1 alternate non-inverting input ctb.oa1.inp_alt.

Key specifications

Parameter Value
Manufacturer Infineon Cypress Semicon
Package TQFP-44(10x10)
Category Embedded Processors & Controllers
Pins 44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSSD VDDD_ABS -0.5 6 V Absolute max 19
Direct digital core voltage input relative to Vssd VCCD_ABS -0.5 1.95 V Absolute max 19
GPIO voltage VGPIO_ABS -0.5 V Absolute max 19
Maximum current per GPIO IGPIO_ABS -25 25 mA Absolute max 19
GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS IGPIO_injection -0.5 0.5 mA Absolute max, current injected per pin 19
Electrostatic discharge human body model ESD_HBM 2200 V 19
Electrostatic discharge charged device model ESD_CDM 500 V 19
Pin current for latch-up LU -200 200 mA 19
Power Supply Input Voltage (VDDA = VDDD = VDD) VDD 1.8 5.5 V With regulator enabled 19
Power Supply Input Voltage unregulated VDDD 1.71 1.8 1.89 V Internally unregulated supply 19
External Regulator voltage bypass CEFC 1 1.3 1.6 µF X5R ceramic or better 19
Power supply decoupling capacitor CEXC 1 µF X5R ceramic or better 19
Execute from Flash; CPU at 6 MHz IDD4 2.8 mA 19
Execute from Flash; CPU at 12 MHz IDD7 4.2 mA 19
Execute from Flash; CPU at 24 MHz IDD12 7.2 mA 19
Execute from Flash; CPU at 48 MHz IDD15 13.8 mA 19
Sleep mode I2C wakeup, WDT, and Comparators on, 6 MHz IDD20 1.8 mA I2C wakeup, WDT, and Comparators on. 6 MHz. VDD = 1.71 to 5.5 V. 19
Sleep mode I2C wakeup, WDT, and Comparators on, 12 MHz IDD20A 2.2 mA I2C wakeup, WDT, and Comparators on. 12 MHz. VDD = 1.71 to 5.5 V. 19
Deep Sleep current, I2C wakeup and WDT on IDD27 45 µA I2C wakeup and WDT on. T = 85 °C 20
Deep Sleep current, VDD = 3.6 V to 5.5 V IDD29 1.5 15 µA I2C wakeup and WDT on. Typ. at 25 °C. Max at 85 °C. 20
Deep Sleep current, regulator bypassed IDD33 60 µA I2C wakeup and WDT on. T = 85 °C 20
Deep Sleep current, +105 °C, regulator off IDD28Q 135 µA I2C wakeup and WDT on. Regulator Off. VDD = 1.71 to 1.89 20
Deep Sleep current, +105 °C IDD29Q 180 µA I2C wakeup and WDT on. VDD = 1.8 to 3.6 20
Deep Sleep current, +105 °C IDD30Q 140 µA I2C wakeup and WDT on. VDD = 3.6 to 5.5 20
Hibernate current, GPIO and Reset active IDD36 1000 nA GPIO and Reset active. T = 85 °C 20
Hibernate current, GPIO and Reset active, regulator bypassed IDD42 1000 nA GPIO and Reset active. T = 85 °C 20
Hibernate current, +105 °C, regulator off IDD37Q 19.4 µA Regulator Off. VDD = 1.71 to 1.89 20
Hibernate current, +105 °C IDD38Q 17 µA VDD = 1.8 to 3.6 20
Hibernate current, +105 °C IDD39Q 16 µA VDD = 3.6 to 5.5 20
Stop Mode current IDD43A 20 80 nA Stop Mode current; VDD = 3.3 V. Typ. at 25 °C. Max at 85 °C. 20
Stop Mode current, +105 °C IDD43AQ 5645 nA Stop Mode current; VDD = 3.6 V 20
Supply current while XRES asserted IDD_XR 2 5 mA 20
CPU frequency FCPU 48 MHz 1.71 VDD 5.5 19
Wakeup from Deep Sleep mode TDEEPSLEEP 25 µs 24 MHz IMO. Guaranteed by characterization 19
Wakeup from Hibernate and Stop modes THIBERNATE 2 ms Guaranteed by characterization 19
External reset pulse width TRESETWIDTH 1 µs Guaranteed by characterization 19
Number of wait states at 48 MHz TWS48 1 CPU execution from Flash. Guaranteed by characterization 34
Number of wait states at 24 MHz TWS24 0 CPU execution from Flash. Guaranteed by characterization 34
Trimmed internal reference to SAR VREFSAR -1 1 % Percentage of Vbg (1.024 V). Guaranteed by characterization 34
Clock switching from clk1 to clk2 in clk1 periods TCLKSWITCH 3 4 Periods Guaranteed by design 34
LCLK to output delay TLCLKDO 18 ns 34
Input setup time to LCLCK rising edge TDINLCLK 7 ns 34
Input hold time from LCLK rising edge TDINLCLKHLD 5 ns 34
LCLK to output tristated TLCLKHIZ 28 ns 34
LCLK frequency TFLCLK 33 MHz 34
LCLK duty cycle (percentage high) TLCLKDUTY 40 60 % 34
Operating ambient temperature TA -40 25 105 °C 37
Operating junction temperature TJ -40 125 °C 37
Package JA (44-pin TQFP) TJA 57.16 °C/Watt 37
Package JC (44-pin TQFP) TJC 17.47 °C/Watt 37

CAD (KiCad official)

  • Symbol: CY8C4245AXI-483
  • Footprint: Package_QFP:TQFP-44_10x10mm_P0.8mm
  • 3D model: TQFP-44(10x10) (KiCad packages3D, STEP)
  • 3D model files: cy8c4245axi-483-etched.step / cy8c4245axi-483-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4245axi-483.step / cy8c4245axi-483.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Cypress Semicon datasheet (45 pp, sha256 a1248f50e070da7c, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF