# CY8C4148AZI-S455

**Cypress Semicon** · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-64(10x10)

CY8C4148AZI-S455 from Cypress Semicon, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.7 | bidirectional | GPIO P1.7; Table 2 alternates include analog ctb0_oa1+, sar_ext_vref0 and sar_ext_vref1, plus tcpwm.line_compl[7]:1 and scb[2].spi_clk:1. |
| 2 | P2.0 | bidirectional | GPIO P2.0; Table 2 alternates include sarmux[0], SmartIo[0].io[0], tcpwm.line[4]:0, csd.comp, tcpwm.tr_in[4], scb[1].i2c_scl:1 and scb[1].spi_mosi:2. |
| 3 | P2.1 | bidirectional | GPIO P2.1; Table 2 alternates include sarmux[1], SmartIo[0].io[1], tcpwm.line_compl[4]:0, tcpwm.tr_in[5], scb[1].i2c_sda:1 and scb[1].spi_miso:2. |
| 4 | P2.2 | bidirectional | GPIO P2.2; Table 2 alternates include sarmux[2], SmartIo[0].io[2], tcpwm.line[5]:1 and scb[1].spi_clk:2. |
| 5 | P2.3 | bidirectional | GPIO P2.3; Table 2 alternates include sarmux[3], SmartIo[0].io[3], tcpwm.line_compl[5]:1 and scb[1].spi_select0:2. |
| 6 | P2.4 | bidirectional | GPIO P2.4; Table 2 alternates include sarmux[4], SmartIo[0].io[4], tcpwm.line[0]:1, scb[3].uart_rx:1 and scb[1].spi_select1:1. |
| 7 | P2.5 | bidirectional | GPIO P2.5; Table 2 alternates include sarmux[5], SmartIo[0].io[5], tcpwm.line_compl[0]:1, scb[3].uart_tx:1 and scb[1].spi_select2:1. |
| 8 | P2.6 | bidirectional | GPIO P2.6; Table 2 alternates include sarmux[6], SmartIo[0].io[6], tcpwm.line[1]:1, scb[3].uart_cts:1 and scb[1].spi_select3:1. |
| 9 | P2.7 | bidirectional | GPIO P2.7; Table 2 alternates include sarmux[7], SmartIo[0].io[7], tcpwm.line_compl[1]:1, scb[3].uart_rts:1, lpcomp.comp[0]:0 and scb[2].spi_mosi:1. |
| 10 | VSSD | power_in | Ground pin for the digital section. |
| 11 | DNC | unconnected | Do not connect; no connection should be made to this pin. |
| 12 | P6.0 | bidirectional | GPIO P6.0; Table 2 alternates include tcpwm.line[4]:1, scb[3].uart_rx:0, scb[3].i2c_scl:1 and scb[3].spi_mosi:0. |
| 13 | P6.1 | bidirectional | GPIO P6.1; Table 2 alternates include tcpwm.line_compl[4]:1, scb[3].uart_tx:0, scb[3].i2c_sda:1 and scb[3].spi_miso:0. |
| 14 | P6.2 | bidirectional | GPIO P6.2; Table 2 alternates include tcpwm.line[5]:0, scb[3].uart_cts:0 and scb[3].spi_clk:0. |
| 15 | P6.4 | bidirectional | GPIO P6.4; Table 2 alternates include tcpwm.line[6]:0, scb[4].i2c_scl and scb[3].spi_select1:0. |
| 16 | P6.5 | bidirectional | GPIO P6.5; Table 2 alternates include tcpwm.line_compl[6]:0, scb[4].i2c_sda and scb[3].spi_select2:0. |
| 17 | VSSD | power_in | Ground pin for the digital section. |
| 18 | P3.0 | bidirectional | GPIO P3.0; Table 2 alternates include SmartIo[1].io[0], tcpwm.line[0]:0, scb[1].uart_rx:1, scb[1].i2c_scl:2 and scb[1].spi_mosi:0. |
| 19 | P3.1 | bidirectional | GPIO P3.1; Table 2 alternates include SmartIo[1].io[1], tcpwm.line_compl[0]:0, scb[1].uart_tx:1, scb[1].i2c_sda:2 and scb[1].spi_miso:0. |
| 20 | P3.2 | bidirectional | GPIO P3.2; Table 2 alternates include SmartIo[1].io[2], tcpwm.line[1]:0, scb[1].uart_cts:1, cpuss.swd_data and scb[1].spi_clk:0. |
| 21 | P3.3 | bidirectional | GPIO P3.3; Table 2 alternates include SmartIo[1].io[3], tcpwm.line_compl[1]:0, scb[1].uart_rts:1, cpuss.swd_clk and scb[1].spi_select0:0. |
| 22 | P3.4 | bidirectional | GPIO P3.4; Table 2 alternates include SmartIo[1].io[4], tcpwm.line[2]:0, tcpwm.tr_in[6] and scb[1].spi_select1:0. |
| 23 | P3.5 | bidirectional | GPIO P3.5; Table 2 alternates include SmartIo[1].io[5], tcpwm.line_compl[2]:0 and scb[1].spi_select2:0. |
| 24 | P3.6 | bidirectional | GPIO P3.6; Table 2 alternates include SmartIo[1].io[6], tcpwm.line[3]:0, scb[4].spi_select3 and scb[1].spi_select3:0. |
| 25 | P3.7 | bidirectional | GPIO P3.7; Table 2 alternates include SmartIo[1].io[7], tcpwm.line_compl[3]:0, lpcomp.comp[1]:1 and scb[2].spi_miso:1. |
| 26 | VDDD | power_in | Power supply for the digital section. |
| 27 | P4.0 | bidirectional | GPIO P4.0; Table 2 alternates include csd.vref_ext, scb[0].uart_rx:0, scb[0].i2c_scl:1 and scb[0].spi_mosi:0. |
| 28 | P4.1 | bidirectional | GPIO P4.1; Table 2 alternates include csd.cshield, scb[0].uart_tx:0, scb[0].i2c_sda:1 and scb[0].spi_miso:0. |
| 29 | P4.2 | bidirectional | GPIO P4.2; Table 2 alternates include csd.cmod, scb[0].uart_cts:0, lpcomp.comp[0]:1 and scb[0].spi_clk:0. |
| 30 | P4.3 | bidirectional | GPIO P4.3; Table 2 alternates include csd.csh_tank, scb[0].uart_rts:0, lpcomp.comp[1]:2 and scb[0].spi_select0:0. |
| 31 | P4.4 | bidirectional | GPIO P4.4; Table 2 alternates include scb[4].uart_rx, scb[4].spi_mosi and scb[0].spi_select1:2. |
| 32 | P4.5 | bidirectional | GPIO P4.5; Table 2 alternates include scb[4].uart_tx, scb[4].spi_miso and scb[0].spi_select2:2. |
| 33 | P4.6 | bidirectional | GPIO P4.6; Table 2 alternates include scb[4].uart_cts, scb[4].spi_clk and scb[0].spi_select3:2. |
| 34 | P4.7 | bidirectional | GPIO P4.7; Table 2 alternates include scb[4].uart_rts and scb[4].spi_select0. |
| 35 | P5.6 | bidirectional | GPIO P5.6; Table 2 alternates include tcpwm.line[7]:0 and scb[4].spi_select1. |
| 36 | P5.7 | bidirectional | GPIO P5.7; Table 2 alternates include tcpwm.line_compl[7]:0 and scb[4].spi_select2. |
| 37 | P7.0 | bidirectional | GPIO P7.0; Table 2 alternates include tcpwm.line[0]:2, scb[3].uart_rx:2, scb[3].i2c_scl:2 and scb[3].spi_mosi:1. |
| 38 | P7.1 | bidirectional | GPIO P7.1; Table 2 alternates include tcpwm.line_compl[0]:2, scb[3].uart_tx:2, scb[3].i2c_sda:2 and scb[3].spi_miso:1. |
| 39 | P0.0 | bidirectional | GPIO P0.0; Table 2 alternates include analog lpcomp.in_p[0], tcpwm.tr_in[0], scb[2].uart_cts:0, scb[2].i2c_scl:0 and scb[0].spi_select1:0. |
| 40 | P0.1 | bidirectional | GPIO P0.1; Table 2 alternates include analog lpcomp.in_n[0], tcpwm.tr_in[1], scb[2].uart_rts:0, scb[2].i2c_sda:0 and scb[0].spi_select2:0. |
| 41 | P0.2 | bidirectional | GPIO P0.2; Table 2 alternates include analog lpcomp.in_p[1] and scb[0].spi_select3:0. |
| 42 | P0.3 | bidirectional | GPIO P0.3; Table 2 alternates include analog lpcomp.in_n[1] and scb[2].spi_select0:1. |
| 43 | P0.4 | bidirectional | GPIO P0.4; Table 2 alternates include analog wco.wco_in, scb[1].uart_rx:0, scb[2].uart_rx:0, scb[1].i2c_scl:0 and scb[1].spi_mosi:1. |
| 44 | P0.5 | bidirectional | GPIO P0.5; Table 2 alternates include analog wco.wco_out, scb[1].uart_tx:0, scb[2].uart_tx:0, scb[1].i2c_sda:0 and scb[1].spi_miso:1. |
| 45 | P0.6 | bidirectional | GPIO P0.6; Table 2 alternates include analog exco.eco_in, ext_clk:0, scb[1].uart_cts:0, scb[2].uart_tx:1 and scb[1].spi_clk:1. |
| 46 | P0.7 | bidirectional | GPIO P0.7; Table 2 alternates include analog exco.eco_out, tcpwm.line[0]:3, scb[1].uart_rts:0 and scb[1].spi_select0:1. |
| 47 | XRES | input | Reset pin named XRES in the pinout table; the supplied pages give no electrical description for it. |
| 48 | VCCD | power_out | Regulated digital supply output of the internal regulator, 1.8 V ±5%, which must not be connected to anything else in Mode 1. |
| 49 | VSSD | power_in | Ground pin for the digital section. |
| 50 | VDDD | power_in | Power supply for the digital section. |
| 51 | P5.0 | bidirectional | GPIO P5.0; Table 2 alternates include tcpwm.line[4]:2, scb[2].i2c_scl:1 and scb[2].spi_mosi:0. |
| 52 | P5.1 | bidirectional | GPIO P5.1; Table 2 alternates include tcpwm.line_compl[4]:2, scb[2].uart_tx:2, scb[2].i2c_sda:1 and scb[2].spi_miso:0. |
| 53 | P5.2 | bidirectional | GPIO P5.2; Table 2 alternates include tcpwm.line[5]:2, scb[2].uart_cts:1, lpcomp.comp[0]:2 and scb[2].spi_clk:0. |
| 54 | P5.3 | bidirectional | GPIO P5.3; Table 2 alternates include tcpwm.line_compl[5]:2, scb[2].uart_rts:1, lpcomp.comp[1]:0 and scb[2].spi_select0:0. |
| 55 | P5.5 | bidirectional | GPIO P5.5; Table 2 alternates include tcpwm.line_compl[6]:2 and scb[2].spi_select2:0. |
| 56 | VDDA | power_in | Power supply for the analog section. |
| 57 | VSSA | power_in | Ground pin for the analog section. |
| 58 | P1.0 | bidirectional | GPIO P1.0; Table 2 alternates include analog ctb0_oa0+, tcpwm.line[2]:1, scb[0].uart_rx:1, scb[0].i2c_scl:0 and scb[0].spi_mosi:1. |
| 59 | P1.1 | bidirectional | GPIO P1.1; Table 2 alternates include analog ctb0_oa0-, tcpwm.line_compl[2]:1, scb[0].uart_tx:1, scb[0].i2c_sda:0 and scb[0].spi_miso:1. |
| 60 | P1.2 | bidirectional | GPIO P1.2; Table 2 alternates include analog ctb0_oa0_out, tcpwm.line[3]:1, scb[0].uart_cts:1, tcpwm.tr_in[2], scb[2].i2c_scl:2 and scb[0].spi_clk:1. |
| 61 | P1.3 | bidirectional | GPIO P1.3; Table 2 alternates include analog ctb0_oa1_out, tcpwm.line_compl[3]:1, scb[0].uart_rts:1, tcpwm.tr_in[3], scb[2].i2c_sda:2 and scb[0].spi_select0:1. |
| 62 | P1.4 | bidirectional | GPIO P1.4; Table 2 alternates include analog ctb0_oa1-, tcpwm.line[6]:1, scb[3].i2c_scl:0 and scb[0].spi_select1:1. |
| 63 | P1.5 | bidirectional | GPIO P1.5; Table 2 alternates include analog ctb0_oa1+, tcpwm.line_compl[6]:1, scb[3].i2c_sda:0 and scb[0].spi_select2:1. |
| 64 | P1.6 | bidirectional | GPIO P1.6; Table 2 alternates include analog ctb0_oa0+, tcpwm.line[7]:1 and scb[0].spi_select3:1. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | TQFP-64(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Digital supply relative to VSS | VDDD_ABS | -0.5 |  | 6 | V |  | 22 |
| Direct digital core voltage input relative to VSS | VCCD_ABS | -0.5 |  | 1.95 | V |  | 22 |
| GPIO voltage | VGPIO_ABS | -0.5 |  |  | V |  | 22 |
| Maximum current per GPIO | IGPIO_ABS | -25 |  | 25 | mA |  | 22 |
| GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS | IGPIO_injection | -0.5 |  | 0.5 | mA | Current injected per pin | 22 |
| Electrostatic discharge human body model | ESD_HBM | 2200 |  |  | V |  | 22 |
| Electrostatic discharge charged device model | ESD_CDM | 500 |  |  | V |  | 22 |
| Pin current for latch-up | LU | -140 |  | 140 | mA |  | 22 |
| Power supply input voltage | VDD | 1.8 |  | 5.5 | V | Internally regulated supply | 22 |
| Power supply input voltage (VCCD = VDDD = VDDA) | VDD | 1.71 |  | 1.89 | V | Internally unregulated supply | 22 |
| Active mode, execute from flash; CPU at 6 MHz | IDD5 |  | 1.8 | 2.4 | mA | Active mode, VDD = 1.8 V to 5.5 V; typ at VDD = 3.3 V, 25°C | 22 |
| Active mode, execute from flash; CPU at 24 MHz | IDD8 |  | 3 | 4.6 | mA | Active mode, VDD = 1.8 V to 5.5 V; typ at VDD = 3.3 V, 25°C | 22 |
| Active mode, execute from flash; CPU at 48 MHz | IDD11 |  | 5.4 | 7.1 | mA | Active mode, VDD = 1.8 V to 5.5 V; typ at VDD = 3.3 V, 25°C | 22 |
| I2C wakeup, WDT, and Comparators ON | IDD17 |  | 1.1 | 2.1 | mA | Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator ON); 6 MHz | 22 |
| I2C wakeup, WDT, and Comparators ON | IDD20 |  | 1.5 | 2.8 | mA | Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator ON); 12 MHz | 22 |
| I2C wakeup, WDT, and Comparators ON | IDD23 |  | 1.1 | 2.1 | mA | Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed); 6 MHz | 23 |
| I2C wakeup, WDT, and Comparators ON | IDD23A |  | 1.5 | 2.8 | mA | Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed); 12 MHz | 23 |
| I2C wakeup and WDT ON | IDD25 |  | 2.5 | 40 | µA | Deep Sleep, VDD = 1.8 V to 3.6 V (Regulator ON); T = -40°C to 60°C | 23 |
| I2C wakeup and WDT ON | IDD26 |  | 2.5 | 125 | µA | Deep Sleep, VDD = 1.8 V to 3.6 V (Regulator ON); max at 3.6 V and 85°C | 23 |
| I2C wakeup and WDT ON | IDD31 |  | 2.5 | 60 | µA | Deep Sleep, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed); T = -40°C to 60°C | 23 |
| I2C wakeup and WDT ON | IDD32 |  | 2.5 | 180 | µA | Deep Sleep, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed); max at 1.89 V and 85°C | 23 |
| Supply current while XRES asserted | IDD_XR |  | 2 | 5 | mA |  | 23 |
| IMO operating current at 48 MHz | IIMO1 |  |  | 250 | µA | Guaranteed by design | 41 |
| IMO operating current at 24 MHz | IIMO2 |  |  | 180 | µA | Guaranteed by design | 41 |
| Frequency variation at 24, 32, and 48 MHz (trimmed) | FIMOTOL1 | -2 |  | 2 | % | At -40°C to 85°C, for industrial temperature range and original extended industrial range parts | 41 |
| IMO startup time | TSTARTIMO |  |  | 7 | µs |  | 41 |
| ILO operating current | IILO1 |  | 0.3 | 1.05 | µA | Guaranteed by design | 42 |
| ILO startup time | TSTARTILO1 |  |  | 2 | ms | Guaranteed by design | 42 |
| ILO duty cycle | TILODUTY | 40 | 50 | 60 | % |  | 42 |
| ILO frequency range | FILOTRIM1 | 20 | 40 | 80 | kHz |  | 42 |
| Frequency tolerance | FTOL |  | 50 | 250 | ppm | With 20-ppm crystal | 42 |
| Drive level | PD |  |  | 1 | µW |  | 42 |
| Startup time | TSTART |  |  | 500 | ms | WCO | 42 |
| Crystal load capacitance | CL | 6 |  | 12.5 | pF |  | 42 |
| Operating current (high power mode) | IWCO1 |  |  | 8 | µA |  | 42 |
| External clock input frequency | ExtClkFreq | 0 |  | 48 | MHz |  | 42 |
| Duty cycle; measured at VDD/2 | ExtClkDuty | 45 |  | 55 | % | Measured at VDD/2 | 42 |
| Block current | IECO1 |  |  | 1.5 | mA |  | 42 |
| Crystal frequency range | FECO | 4 |  | 33 | MHz |  | 42 |
| PLL current at 48 MHz output | IDD_PLL_48 |  | 530 | 610 | µA | In = 3 MHz, Out = 48 MHz | 43 |
| PLL current at 24 MHz output | IDD_PLL_24 |  | 300 | 405 | µA | In = 3 MHz, Out = 24 MHz | 43 |
| PLL input frequency | Fpllin | 1 |  | 48 | MHz |  | 43 |
| PLL intermediate frequency; prescaler out | Fpllint | 1 |  | 3 | MHz |  | 43 |
| VCO output frequency before post-divide | Fpllvco | 22.5 |  | 104 | MHz |  | 43 |
| VCO Output post-divider range; PLL output frequency is Fpplvco/Divvco | Divvco | 1 |  | 8 |, |  | 43 |
| Lock time at startup | Plllocktime |  |  | 250 | µs |  | 43 |
| Period jitter for VCO ≥ 67 MHz | Jperiod_1 |  |  | 150 | ps | Guaranteed by design | 43 |
| Period jitter for VCO ≤ 67 MHz | Jperiod_2 |  |  | 200 | ps | Guaranteed by design | 43 |
| System clock source switching time | TCLKSWITCH | 3 |  | 4 | Periods | Guaranteed by characterization | 43 |
| Max delay added by Smart I/O in Bypass mode | PRG_BYPASS |  |  | 1.6 | ns |  | 43 |
| Operating ambient temperature | TA | -40 |  | 85 | °C | Industrial (I) range for CY8C4148AZI-S455 per ordering table | 44 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 46 |
| External regulator voltage bypass | CEFC |  | 0.1 |  | µF | X5R ceramic or better | 22 |
| Power supply bypass capacitor | CEXC |  | 1 |  | µF | X5R ceramic or better | 22 |
| Crystal frequency | FWCO |  | 32.768 |  | kHz |  | 42 |
| Package θJA, 64-pin TQFP (0.5-mm pitch) | TJA |  | 46 |  | °C/Watt | 64-pin TQFP (0.5-mm pitch) | 46 |
| Package θJC, 64-pin TQFP (0.5-mm pitch) | TJC |  | 10 |  | °C/Watt | 64-pin TQFP (0.5-mm pitch) | 46 |

## CAD (KiCad official)

- Symbol: `CY8C4148AZI-S455`
- Footprint: `Package_QFP:TQFP-64_10x10mm_P0.5mm`
- 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `cy8c4148azi-s455-etched.step` / `cy8c4148azi-s455-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cy8c4148azi-s455.step` / `cy8c4148azi-s455.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Cypress Semicon datasheet](https://www.infineon.com/assets/row/public/documents/30/49/infineon-psoc-tm-4100s-plus-256kb-datasheet-en.pdf) (56 pp, sha256 `18bf0a9e56312bfa`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cy8c4148azi-s455-datasheet.pdf)