component

CY8C4148AZI-S453

Public Made by Adom

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy8c4148azi-s453factory-2.0.0extractor-text

Verified CY8C4148AZI-S453

by Ray · last 31 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

31 Oct 2026RayPublished by the parts factory: tier mfr, 48 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY8C4148AZI-S453 · TQFP-48(7x7) · 48 pins
  • ✓copper: 48 copper pads, none touching another net
  • ✓datasheet: all 48 pin names found in the 56-page datasheet
  • ✓distributor: lcsc C2948666, digikey 448-CY8C4148AZI-S453-ND, mouser 727-CY8C4148AZI-S453
  • ✓family: TQFP-48_7x7mm_P0.5mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-s9ynjqcp/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 48 pins = 48 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 48 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy8c4148azi-s453.kicad_sym✓ cy8c4148azi-s453.kicad_mod✓ cy8c4148azi-s453.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cy8c4148azi-s453: viewers · Ray
cy8c4148azi-s453-etched.glb Publish 0.1.0 · Ray
cy8c4148azi-s453-etched.step cy8c4148azi-s453: factory component page (tier=mfr) · Ray
cy8c4148azi-s453-hero.glb cy8c4148azi-s453: hero GLB from the etched model (keeps the MPN mark) · Ray
cy8c4148azi-s453-hero.overlay.json Publish 0.1.0 · Ray
cy8c4148azi-s453.glb Publish 0.1.0 · Ray
cy8c4148azi-s453.kicad_mod Publish 0.1.0 · Ray
cy8c4148azi-s453.kicad_sym Publish 0.1.0 · Ray
cy8c4148azi-s453.lbr Publish 0.1.0 · Ray
cy8c4148azi-s453.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier mfr, 48 pins · Ray

CY8C4148AZI-S453

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-48(7x7)

CY8C4148AZI-S453 from Cypress Semicon, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7 bidirectional GPIO port 1 bit 7 with analog ctb0_oa1+, sar_ext_vref0/sar_ext_vref1, tcpwm.line_compl[7]:1 and scb[2].spi_clk:1 alternate functions.
2 P2.0 bidirectional GPIO port 2 bit 0 with sarmux[0], SmartIo[0].io[0], tcpwm.line[4]:0, csd.comp and scb[1] I2C/SPI alternate functions.
3 P2.1 bidirectional GPIO port 2 bit 1 with sarmux[1], SmartIo[0].io[1], tcpwm.line_compl[4]:0 and scb[1] I2C/SPI alternate functions.
4 P2.2 bidirectional GPIO port 2 bit 2 with sarmux[2], SmartIo[0].io[2], tcpwm.line[5]:1 and scb[1].spi_clk:2 alternate functions.
5 P2.3 bidirectional GPIO port 2 bit 3 with sarmux[3], SmartIo[0].io[3], tcpwm.line_compl[5]:1 and scb[1].spi_select0:2 alternate functions.
6 P2.4 bidirectional GPIO port 2 bit 4 with sarmux[4], SmartIo[0].io[4], tcpwm.line[0]:1, scb[3].uart_rx:1 and scb[1].spi_select1:1 alternate functions.
7 P2.5 bidirectional GPIO port 2 bit 5 with sarmux[5], SmartIo[0].io[5], tcpwm.line_compl[0]:1, scb[3].uart_tx:1 and scb[1].spi_select2:1 alternate functions.
8 P2.6 bidirectional GPIO port 2 bit 6 with sarmux[6], SmartIo[0].io[6], tcpwm.line[1]:1, scb[3].uart_cts:1 and scb[1].spi_select3:1 alternate functions.
9 P2.7 bidirectional GPIO port 2 bit 7 with sarmux[7], SmartIo[0].io[7], tcpwm.line_compl[1]:1, scb[3].uart_rts:1, lpcomp.comp[0]:0 and scb[2].spi_mosi:1 alternate functions.
10 VSSD power_in Ground pin for the digital section.
11 DNC unconnected Do not connect; no connection should be made to this pin.
12 P3.0 bidirectional GPIO port 3 bit 0 with SmartIo[1].io[0], tcpwm.line[0]:0, scb[1].uart_rx:1 and scb[1] I2C/SPI alternate functions.
13 P3.1 bidirectional GPIO port 3 bit 1 with SmartIo[1].io[1], tcpwm.line_compl[0]:0, scb[1].uart_tx:1 and scb[1] I2C/SPI alternate functions.
14 P3.2 bidirectional GPIO port 3 bit 2 with SmartIo[1].io[2], tcpwm.line[1]:0, scb[1].uart_cts:1, cpuss.swd_data and scb[1].spi_clk:0 alternate functions.
15 DNC unconnected Do not connect; no connection should be made to this pin.
16 P3.3 bidirectional GPIO port 3 bit 3 with SmartIo[1].io[3], tcpwm.line_compl[1]:0, scb[1].uart_rts:1, cpuss.swd_clk and scb[1].spi_select0:0 alternate functions.
17 P3.4 bidirectional GPIO port 3 bit 4 with SmartIo[1].io[4], tcpwm.line[2]:0, tcpwm.tr_in[6] and scb[1].spi_select1:0 alternate functions.
18 P3.5 bidirectional GPIO port 3 bit 5 with SmartIo[1].io[5], tcpwm.line_compl[2]:0 and scb[1].spi_select2:0 alternate functions.
19 P3.6 bidirectional GPIO port 3 bit 6 with SmartIo[1].io[6], tcpwm.line[3]:0, scb[4].spi_select3 and scb[1].spi_select3:0 alternate functions.
20 P3.7 bidirectional GPIO port 3 bit 7 with SmartIo[1].io[7], tcpwm.line_compl[3]:0, lpcomp.comp[1]:1 and scb[2].spi_miso:1 alternate functions.
21 VDDD power_in Power supply for the digital section.
22 P4.0 bidirectional GPIO port 4 bit 0 with csd.vref_ext analog function, scb[0].uart_rx:0 and scb[0] I2C/SPI alternate functions.
23 P4.1 bidirectional GPIO port 4 bit 1 with csd.cshield analog function, scb[0].uart_tx:0 and scb[0] I2C/SPI alternate functions.
24 P4.2 bidirectional GPIO port 4 bit 2 with csd.cmod analog function, scb[0].uart_cts:0, lpcomp.comp[0]:1 and scb[0].spi_clk:0 alternate functions.
25 P4.3 bidirectional GPIO port 4 bit 3 with csd.csh_tank analog function, scb[0].uart_rts:0, lpcomp.comp[1]:2 and scb[0].spi_select0:0 alternate functions.
26 P7.0 bidirectional GPIO port 7 bit 0 with tcpwm.line[0]:2, scb[3].uart_rx:2 and scb[3] I2C/SPI alternate functions.
27 P7.1 bidirectional GPIO port 7 bit 1 with tcpwm.line_compl[0]:2, scb[3].uart_tx:2 and scb[3] I2C/SPI alternate functions.
28 P0.0 bidirectional GPIO port 0 bit 0 with lpcomp.in_p[0] analog function, tcpwm.tr_in[0] and scb[2]/scb[0] alternate functions.
29 P0.1 bidirectional GPIO port 0 bit 1 with lpcomp.in_n[0] analog function, tcpwm.tr_in[1] and scb[2]/scb[0] alternate functions.
30 P0.2 bidirectional GPIO port 0 bit 2 with lpcomp.in_p[1] analog function and scb[0].spi_select3:0 alternate function.
31 P0.3 bidirectional GPIO port 0 bit 3 with lpcomp.in_n[1] analog function and scb[2].spi_select0:1 alternate function.
32 P0.4 bidirectional GPIO port 0 bit 4 with wco.wco_in (32 kHz watch crystal) analog function and scb[1]/scb[2] UART, I2C, SPI alternate functions.
33 P0.5 bidirectional GPIO port 0 bit 5 with wco.wco_out (32 kHz watch crystal) analog function and scb[1]/scb[2] UART, I2C, SPI alternate functions.
34 P0.6 bidirectional GPIO port 0 bit 6 with exco.eco_in (external crystal oscillator) analog function, ext_clk:0 and scb[1] alternate functions.
35 P0.7 bidirectional GPIO port 0 bit 7 with exco.eco_out (external crystal oscillator) analog function, ext_clk tcpwm.line[0]:3 and scb[1] alternate functions.
36 XRES input External reset pin listed in the pin table; its function is not described in the provided pages.
37 VCCD power_out Regulated digital supply (1.8 V ±5%) that must be bypassed to ground with a 0.1 µF X5R ceramic or better capacitor and connected to nothing else in the 1.8 V to 5.5 V supply mode.
38 VSSD power_in Ground pin for the digital section.
39 VDDD power_in Power supply for the digital section, 1.8 V to 5.5 V in Mode 1 and bypassed to ground.
40 VDDA power_in Power supply for the analog section, which runs directly from VDDA.
41 VSSA power_in Ground pin for the analog section.
42 P1.0 bidirectional GPIO port 1 bit 0 with ctb0_oa0+ opamp analog function, tcpwm.line[2]:1 and scb[0] UART, I2C, SPI alternate functions.
43 P1.1 bidirectional GPIO port 1 bit 1 with ctb0_oa0- opamp analog function, tcpwm.line_compl[2]:1 and scb[0] UART, I2C, SPI alternate functions.
44 P1.2 bidirectional GPIO port 1 bit 2 with ctb0_oa0_out opamp output, tcpwm.line[3]:1, tcpwm.tr_in[2] and scb[0]/scb[2] alternate functions.
45 P1.3 bidirectional GPIO port 1 bit 3 with ctb0_oa1_out opamp output, tcpwm.line_compl[3]:1, tcpwm.tr_in[3] and scb[0]/scb[2] alternate functions.
46 P1.4 bidirectional GPIO port 1 bit 4 with ctb0_oa1- opamp analog function, tcpwm.line[6]:1 and scb[3].i2c_scl:0 / scb[0].spi_select1:1 alternate functions.
47 P1.5 bidirectional GPIO port 1 bit 5 with ctb0_oa1+ opamp analog function, tcpwm.line_compl[6]:1 and scb[3].i2c_sda:0 / scb[0].spi_select2:1 alternate functions.
48 P1.6 bidirectional GPIO port 1 bit 6 with ctb0_oa0+ opamp analog function, tcpwm.line[7]:1 and scb[0].spi_select3:1 alternate functions.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TQFP-48(7x7)
Category Single Chip Microcomputer/Microcontroller
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 22
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 22
GPIO voltage VGPIO_ABS -0.5 V 22
Maximum current per GPIO IGPIO_ABS -25 25 mA 22
GPIO injection current, Max for VIH > VDDD, and Min for VIL < VSS IGPIO_injection -0.5 0.5 mA Current injected per pin 22
Electrostatic discharge human body model ESD_HBM 2200 V 22
Electrostatic discharge charged device model ESD_CDM 500 V 22
Pin current for latch-up LU -140 140 mA 22
Power supply input voltage (internally regulated supply) VDD 1.8 5.5 V Internally regulated supply 22
Power supply input voltage (VCCD = VDDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 22
Active mode supply current, execute from flash, CPU at 6 MHz IDD5 1.8 2.4 mA Active mode, VDD = 1.8 V to 5.5 V; execute from flash; CPU at 6 MHz 22
Active mode supply current, execute from flash, CPU at 24 MHz IDD8 3 4.6 mA Active mode, VDD = 1.8 V to 5.5 V; execute from flash; CPU at 24 MHz 22
Active mode supply current, execute from flash, CPU at 48 MHz IDD11 5.4 7.1 mA Active mode, VDD = 1.8 V to 5.5 V; execute from flash; CPU at 48 MHz 23
Sleep mode supply current, 6 MHz (regulator ON) IDD17 1.1 2.1 mA Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator ON); I2C wakeup WDT, and Comparators ON; 6 MHz 23
Sleep mode supply current, 12 MHz (regulator ON) IDD20 1.5 2.8 mA Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator ON); I2C wakeup, WDT, and Comparators ON; 12 MHz 23
Sleep mode supply current, 6 MHz (regulator bypassed) IDD23 1.1 2.1 mA Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed); I2C wakeup, WDT, and Comparators ON; 6 MHz 23
Sleep mode supply current, 12 MHz (regulator bypassed) IDD23A 1.5 2.8 mA Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed); I2C wakeup, WDT, and Comparators ON; 12 MHz 23
Deep Sleep supply current, VDD 1.8 V to 3.6 V (regulator ON), T -40 to 60 C IDD25 2.5 40 µA Deep Sleep mode, VDD = 1.8 V to 3.6 V (Regulator ON); I2C wakeup and WDT ON; T = -40°C to 60°C 23
Deep Sleep supply current, VDD 1.8 V to 3.6 V (regulator ON), max over temperature IDD26 2.5 125 µA Deep Sleep mode, VDD = 1.8 V to 3.6 V (Regulator ON); I2C wakeup and WDT ON; max is at 3.6 V and 85°C 23
Deep Sleep supply current, VDD 3.6 V to 5.5 V (regulator ON), T -40 to 60 C IDD28 2.5 40 µA Deep Sleep mode, VDD = 3.6 V to 5.5 V (Regulator ON); I2C wakeup and WDT ON; T = -40°C to 60°C 23
Deep Sleep supply current, VDD 3.6 V to 5.5 V (regulator ON), max over temperature IDD29 2.5 125 µA Deep Sleep mode, VDD = 3.6 V to 5.5 V (Regulator ON); I2C wakeup and WDT ON; max is at 5.5 V and 85°C 23
Deep Sleep supply current, VDD = VCCD 1.71 V to 1.89 V (regulator bypassed), T -40 to 60 C IDD31 2.5 60 µA Deep Sleep mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed); I2C wakeup and WDT ON; T = -40°C to 60°C 23
Deep Sleep supply current, VDD = VCCD 1.71 V to 1.89 V (regulator bypassed), max over temperature IDD32 2.5 180 µA Deep Sleep mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed); I2C wakeup and WDT ON; max is at 1.89 V and 85°C 23
Supply current while XRES asserted IDD_XR 2 5 mA 23
IMO operating current at 48 MHz IIMO1 250 µA 41
IMO operating current at 24 MHz IIMO2 180 µA 41
Frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % At -40°C to 85°C, for industrial temperature range and original extended industrial range parts 41
IMO startup time TSTARTIMO 7 µs 41
ILO operating current IILO1 0.3 1.05 µA 42
ILO startup time TSTARTILO1 2 ms 42
ILO duty cycle TILODUTY 40 50 60 % 42
ILO frequency range FILOTRIM1 20 40 80 kHz 42
Frequency tolerance (WCO) FTOL 50 250 ppm With 20-ppm crystal 42
Crystal load capacitance CL 6 12.5 pF 42
Drive level PD 1 µW 42
Startup time (WCO) TSTART 500 ms 42
Operating current (WCO, high power mode) IWCO1 8 µA 42
External clock input frequency ExtClkFreq 0 48 MHz 42
Duty cycle ExtClkDuty 45 55 % measured at VDD/2 42
ECO block current IECO1 1.5 mA 42
Crystal frequency range (ECO) FECO 4 33 MHz 42
PLL current, output 48 MHz IDD_PLL_48 530 610 µA In = 3 MHz, Out = 48 MHz 43
PLL current, output 24 MHz IDD_PLL_24 300 405 µA In = 3 MHz, Out = 24 MHz 43
PLL input frequency Fpllin 1 48 MHz 43
PLL intermediate frequency; prescaler out Fpllint 1 3 MHz 43
VCO output frequency before post-divide Fpllvco 22.5 104 MHz 43
VCO output post-divider range; PLL output frequency is Fpllvco/Divvco Divvco 1 8 43
Lock time at startup Plllocktime 250 µs 43
Period jitter for VCO ≥ 67 MHz Jperiod_1 150 ps Guaranteed by design 43
Period jitter for VCO ≤ 67 MHz Jperiod_2 200 ps Guaranteed by design 43
System clock source switching time TCLKSWITCH 3 4 Periods 43
Max delay added by Smart I/O in Bypass mode PRG_BYPASS 1.6 ns 43
Operating junction temperature TJ -40 125 °C 46
Package θJA, 48-pin TQFP (0.5-mm pitch) TJA 39.4 °C/Watt 46
Package θJC, 48-pin TQFP (0.5-mm pitch) TJC 9.3 °C/Watt 46

CAD (KiCad official)

  • Symbol: CY8C4148AZI-S453
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: cy8c4148azi-s453-etched.step / cy8c4148azi-s453-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4148azi-s453.step / cy8c4148azi-s453.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (56 pp, sha256 18bf0a9e56312bfa, retrieved 2026-10-31, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF