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CY8C4147LQS-S473

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY8C4147LQS-S473

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-40(6x6)

CY8C4147LQS-S473 from Cypress Semicon, in a QFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2.3 bidirectional GPIO port 2 bit 3 with SAR mux input sarmux[3], Smart I/O[0].io[3], TCPWM line_compl[5] and SCB1 SPI select0 alternate functions.
2 P2.4 bidirectional GPIO port 2 bit 4 with SAR mux input sarmux[4], Smart I/O[0].io[4], TCPWM line[0], SCB3 UART RX and SCB1 SPI select1 alternate functions.
3 P2.5 bidirectional GPIO port 2 bit 5 with SAR mux input sarmux[5], Smart I/O[0].io[5], TCPWM line_compl[0], SCB3 UART TX and SCB1 SPI select2 alternate functions.
4 P2.6 bidirectional GPIO port 2 bit 6 with SAR mux input sarmux[6], Smart I/O[0].io[6], TCPWM line[1], SCB3 UART CTS and SCB1 SPI select3 alternate functions.
5 P2.7 bidirectional GPIO port 2 bit 7 with SAR mux input sarmux[7], Smart I/O[0].io[7], TCPWM line_compl[1], SCB3 UART RTS, lpcomp.comp[0] and SCB2 SPI MOSI alternate functions.
6 P6.0 bidirectional GPIO port 6 bit 0 with TCPWM line[4], SCB3 UART RX, CAN tx_enb_n, SCB3 I2C SCL and SCB3 SPI MOSI alternate functions.
7 P6.1 bidirectional GPIO port 6 bit 1 with TCPWM line_compl[4], SCB3 UART TX, CAN RX, SCB3 I2C SDA and SCB3 SPI MISO alternate functions.
8 P6.2 bidirectional GPIO port 6 bit 2 with TCPWM line[5], SCB3 UART CTS, CAN TX and SCB3 SPI clock alternate functions.
9 VSSD power_in Ground pin for the digital section.
10 P3.0 bidirectional GPIO port 3 bit 0 with Smart I/O[1].io[0], TCPWM line[0], SCB1 UART RX, I2C SCL and SPI MOSI alternate functions.
11 P3.1 bidirectional GPIO port 3 bit 1 with Smart I/O[1].io[1], TCPWM line_compl[0], SCB1 UART TX, I2C SDA and SPI MISO alternate functions.
12 P3.2 bidirectional GPIO port 3 bit 2 with Smart I/O[1].io[2], TCPWM line[1], SCB1 UART CTS, SWD data (cpuss.swd_data) and SPI clock alternate functions.
13 P3.3 bidirectional GPIO port 3 bit 3 with Smart I/O[1].io[3], TCPWM line_compl[1], SCB1 UART RTS, SWD clock (cpuss.swd_clk) and SPI select0 alternate functions.
14 P3.4 bidirectional GPIO port 3 bit 4 with Smart I/O[1].io[4], TCPWM line[2], TCPWM trigger input tr_in[6] and SCB1 SPI select1 alternate functions.
15 P3.5 bidirectional GPIO port 3 bit 5 with Smart I/O[1].io[5], TCPWM line_compl[2] and SCB1 SPI select2 alternate functions.
16 P3.6 bidirectional GPIO port 3 bit 6 with Smart I/O[1].io[6], TCPWM line[3] and SCB1 SPI select3 alternate functions.
17 P3.7 bidirectional GPIO port 3 bit 7 with Smart I/O[1].io[7], TCPWM line_compl[3], lpcomp.comp[1] and SCB2 SPI MISO alternate functions.
18 P4.0 bidirectional GPIO port 4 bit 0 with CAPSENSE external Vref (csd.vref_ext), SCB0 UART RX, CAN RX, I2C SCL and SPI MOSI alternate functions.
19 P4.1 bidirectional GPIO port 4 bit 1 with CAPSENSE shield (csd.cshield), SCB0 UART TX, CAN TX, I2C SDA and SPI MISO alternate functions.
20 P4.2 bidirectional GPIO port 4 bit 2 with CAPSENSE Cmod/CintA capacitor connection, SCB0 UART CTS, CAN tx_enb_n, lpcomp.comp[0] and SPI clock alternate functions.
21 P4.3 bidirectional GPIO port 4 bit 3 with CAPSENSE shield tank/CintB capacitor connection, SCB0 UART RTS, lpcomp.comp[1] and SPI select0 alternate functions.
22 P0.0 bidirectional GPIO port 0 bit 0 with low-power comparator positive input lpcomp.in_p[0], TCPWM trigger in[0], SCB2 UART CTS, I2C SCL and SCB0 SPI select1 alternate functions.
23 P0.1 bidirectional GPIO port 0 bit 1 with low-power comparator negative input lpcomp.in_n[0], TCPWM trigger in[1], SCB2 UART RTS, I2C SDA and SCB0 SPI select2 alternate functions.
24 P0.2 bidirectional GPIO port 0 bit 2 with low-power comparator positive input lpcomp.in_p[1] and SCB0 SPI select3 alternate function.
25 P0.3 bidirectional GPIO port 0 bit 3 with low-power comparator negative input lpcomp.in_n[1] and SCB2 SPI select0 alternate function.
26 P0.4 bidirectional GPIO port 0 bit 4 with watch crystal oscillator input (wco.wco_in), SCB1/SCB2 UART RX, SCB1 I2C SCL and SPI MOSI alternate functions.
27 P0.5 bidirectional GPIO port 0 bit 5 with watch crystal oscillator output (wco.wco_out), SCB1/SCB2 UART TX, SCB1 I2C SDA and SPI MISO alternate functions.
28 P0.6 bidirectional GPIO port 0 bit 6 with external crystal oscillator input (exco.eco_in), external clock input (srss.ext_clk), SCB1 UART CTS and SPI clock alternate functions.
29 P0.7 bidirectional GPIO port 0 bit 7 with external crystal oscillator output (exco.eco_out), TCPWM line[0], SCB1 UART RTS and SPI select0 alternate functions.
30 XRES input External reset input.
31 VCCD power_out Regulated digital supply (1.8 V ± 5%); must be bypassed to ground with 0.1 µF (X5R ceramic or better) and not connected to anything else when the internal regulator is used.
32 VSSD power_in Ground pin for the digital section.
33 VDD power_in Single supply pin with VDDA and VDDD shorted inside the package; 1.8 V to 5.5 V in Mode 1, with 0.1 µF and 1 µF decoupling capacitors required.
34 VSSA power_in Ground pin for the analog section.
35 P1.0 bidirectional GPIO port 1 bit 0 with opamp 0 positive input (ctb0_oa0+), Smart I/O[2].io[0], TCPWM line[2], SCB0 UART RX, I2C SCL and SPI MOSI alternate functions.
36 P1.1 bidirectional GPIO port 1 bit 1 with opamp 0 negative input (ctb0_oa0-), Smart I/O[2].io[1], TCPWM line_compl[2], SCB0 UART TX, I2C SDA and SPI MISO alternate functions.
37 P1.2 bidirectional GPIO port 1 bit 2 with opamp 0 output (ctb0_oa0_out), Smart I/O[2].io[2], TCPWM line[3], SCB0 UART CTS, TCPWM trigger in[2] and SPI clock alternate functions.
38 P1.3 bidirectional GPIO port 1 bit 3 with opamp 1 output (ctb0_oa1_out), Smart I/O[2].io[3], TCPWM line_compl[3], SCB0 UART RTS, TCPWM trigger in[3] and SPI select0 alternate functions.
39 P1.4 bidirectional GPIO port 1 bit 4 with opamp 1 negative input (ctb0_oa1-), Smart I/O[2].io[4], TCPWM line[6], SCB3 I2C SCL and SCB0 SPI select1 alternate functions.
40 P1.7/VREF bidirectional GPIO port 1 bit 7 with opamp 1 positive input (ctb0_oa1+), SAR ADC external Vref (sar_ext_vref0/1), Smart I/O[2].io[7], TCPWM line_compl[7] and SCB2 SPI clock alternate functions.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-40(6x6)
Category Single Chip Microcomputer/Microcontroller
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 25
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 25
GPIO voltage VGPIO_ABS -0.5 V Max is VDD + 0.5 as printed 25
Maximum current per GPIO IGPIO_ABS -25 25 mA 25
GPIO injection current IGPIO_injection -0.5 0.5 mA Max for VIH > VDDD, and Min for VIL < VSS; current injected per pin 25
ESD human body model ESD_HBM 2200 V 25
ESD charged device model ESD_CDM 500 V 25
Pin current for latch-up LU -140 140 mA 25
Power supply input voltage VDD 1.8 5.5 V Internally regulated supply 26
Power supply input voltage (VCCD = VDDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 26
Output voltage (for core logic) VCCD 1.8 V 26
External regulator voltage bypass CEFC 0.1 µF X5R ceramic or better 26
Power supply bypass capacitor CEXC 1 µF X5R ceramic or better 26
Operating ambient temperature (S-grade) TA -40 25 105 °C For S-grade devices 60
Operating junction temperature (S-grade) TJ -40 115 °C For S-grade devices 60
Package thermal resistance θJA, 40-pin QFN θJA 25 °C/W 40-pin QFN 60
Package thermal resistance θJC, 40-pin QFN θJC 3 °C/W 40-pin QFN 60
Active mode current, CPU at 6 MHz IDD5 1.8 2.7 mA Execute from flash; CPU at 6 MHz; Max is at 125°C and 5.5 V 26
Active mode current, CPU at 24 MHz IDD8 3 5 mA Execute from flash; CPU at 24 MHz; Max is at 125°C and 5.5 V 26
Active mode current, CPU at 48 MHz IDD11 5.4 7.6 mA Execute from flash; CPU at 48 MHz; Max is at 125°C and 5.5 V 26
Sleep mode current, 6 MHz (regulator on) IDD17 1.1 2.2 mA I2C wakeup, WDT, and Comparators on; 6 MHz; Max is at 125°C and 5.5 V 26
Sleep mode current, 12 MHz (regulator on) IDD20 1.5 2.5 mA I2C wakeup, WDT, and Comparators on; 12 MHz; Max is at 125°C and 5.5 V 26
Sleep mode current, 6 MHz (regulator bypassed) IDD23 1.1 1.8 mA I2C wakeup, WDT, and Comparators on; 6 MHz; Max is at 125°C and 1.89 V 26
Sleep mode current, 12 MHz (regulator bypassed) IDD23A 1.5 2.1 mA I2C wakeup, WDT, and Comparators on; 12 MHz; Max is at 125°C and 1.89 V 26
Deep Sleep current, VDD 1.8 V to 3.6 V IDD25 2.5 40 µA I2C wakeup and WDT on; T = -40°C to 60°C 26
Deep Sleep current, VDD 1.8 V to 3.6 V, hot IDD26 2.5 350 µA I2C wakeup and WDT on; Max is at 3.6 V and 125°C 26
Deep Sleep current, VDD 3.6 V to 5.5 V IDD28 2.5 40 µA I2C wakeup and WDT on; T = -40°C to 60°C 26
Deep Sleep current, VDD 3.6 V to 5.5 V, hot IDD29 2.5 350 µA I2C wakeup and WDT on; Max is at 5.5 V and 125°C 26
Deep Sleep current, regulator bypassed IDD31 2.5 60 µA I2C wakeup and WDT on; T = -40°C to 60°C 26
Deep Sleep current, regulator bypassed, hot IDD32 2.5 400 µA I2C wakeup and WDT on; Max is at 125°C and 1.89 V 26
Supply current while XRES asserted IDD_XR 2 5 mA 26
IMO operating current at 48 MHz IIMO1 250 µA 46
IMO operating current at 24 MHz IIMO2 180 µA 46
IMO frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % -40°C ≤ TA ≤ 105°C 46
IMO variation in WCO-locked DPLL mode IMOWCO -0.25 0.25 % All IMO settings 46
IMO startup time TSTARTIMO 7 µs 46
IMO RMS jitter at 24 MHz TJITRMSIMO2 145 ps 46
ILO operating current IILO1 0.3 1.05 µA 47
ILO startup time TSTARTILO1 2 ms 47
ILO duty cycle TILODUTY 40 50 60 % 47
ILO frequency range FILOTRIM1 20 40 80 kHz 47
WCO crystal frequency FWCO 32.768 kHz 47
WCO frequency tolerance FTOL 50 250 ppm With 20-ppm crystal 47
WCO crystal ESR ESR 50 kΩ 47
WCO drive level PD 1 µW 47
WCO startup time TSTART 500 ms 47
WCO crystal load capacitance CL 6 12.5 pF 47
WCO crystal shunt capacitance C0 1.35 pF 47
WCO operating current (high power mode) IWCO1 8 µA 47
External clock input frequency ExtClkFreq 0 48 MHz -40°C ≤ TA ≤ 85°C 47
External clock duty cycle ExtClkDuty 45 55 % Measured at VDD/2; -40°C ≤ TA ≤ 85°C 47
ECO operating current (external clock input frequency) IECO1 1.5 mA 48
ECO crystal frequency range FECO 4 33 MHz 48
PLL current, In = 3 MHz, Out = 48 MHz IDD_PLL_48 530 610 µA In = 3 MHz, Out = 48 MHz 48
PLL current, In = 3 MHz, Out = 24 MHz IDD_PLL_24 300 405 µA In = 3 MHz, Out = 24 MHz 48
PLL input frequency Fpllin 1 48 MHz 48
PLL intermediate frequency; prescaler out Fpllint 1 3 MHz 48
PLL VCO output frequency before post-divide Fpllvco 22.5 104 MHz 48
PLL lock time at startup Plllocktime 250 µs 48
PLL period jitter for VCO ≥ 67 MHz Jperiod_1 150 ps Guaranteed by design; -40°C ≤ TA ≤ 85°C 48
PLL period jitter for VCO ≤ 67 MHz Jperiod_2 200 ps Guaranteed by design; -40°C ≤ TA ≤ 85°C 48
System clock source switching time TCLKSWITCH 3 4 Periods 49
Max delay added by Smart I/O in bypass mode PRG_BYPASS 1.6 ns 49
CAN block current consumption IDD_CAN 200 µA 49
CAN bit rate CAN_bits 1 Mbps Min 8-MHz clock 49

CAD (KiCad official)

  • Symbol: CY8C4147LQS-S473
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: QFN-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: cy8c4147lqs-s473-etched.step / cy8c4147lqs-s473-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4147lqs-s473.step / cy8c4147lqs-s473.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (71 pp, sha256 5c4dbf6d4a457466, retrieved 2026-10-26, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF