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CY8C4147AZI-S455

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Cypress Semicon CYPRESS, TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscy8c4147azi-s455factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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CY8C4147AZI-S455

Cypress Semicon · CYPRESS · TQFP-64(10x10)

CY8C4147AZI-S455 from Cypress Semicon, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7 bidirectional GPIO port 1 bit 7 with analog ctb0_oa1+, sar_ext_vref0/1, SmartIo[2].io[7], tcpwm.line_compl[7] and scb[2].spi_clk alternate functions.
2 P2.0 bidirectional GPIO port 2 bit 0 with sarmux[0], SmartIo[0].io[0], tcpwm.line[4], csd.comp and SCB1 I2C SCL/SPI MOSI alternate functions.
3 P2.1 bidirectional GPIO port 2 bit 1 with sarmux[1], SmartIo[0].io[1], tcpwm.line_compl[4] and SCB1 I2C SDA/SPI MISO alternate functions.
4 P2.2 bidirectional GPIO port 2 bit 2 with sarmux[2], SmartIo[0].io[2], tcpwm.line[5] and scb[1].spi_clk alternate functions.
5 P2.3 bidirectional GPIO port 2 bit 3 with sarmux[3], SmartIo[0].io[3], tcpwm.line_compl[5] and scb[1].spi_select0 alternate functions.
6 P2.4 bidirectional GPIO port 2 bit 4 with sarmux[4], SmartIo[0].io[4], tcpwm.line[0], scb[3].uart_rx and scb[1].spi_select1 alternate functions.
7 P2.5 bidirectional GPIO port 2 bit 5 with sarmux[5], SmartIo[0].io[5], tcpwm.line_compl[0], scb[3].uart_tx and scb[1].spi_select2 alternate functions.
8 P2.6 bidirectional GPIO port 2 bit 6 with sarmux[6], SmartIo[0].io[6], tcpwm.line[1], scb[3].uart_cts and scb[1].spi_select3 alternate functions.
9 P2.7 bidirectional GPIO port 2 bit 7 with sarmux[7], SmartIo[0].io[7], tcpwm.line_compl[1], scb[3].uart_rts, lpcomp.comp[0] and scb[2].spi_mosi alternate functions.
10 VSSD power_in Ground pin for the digital section.
11 NC unconnected No connect.
12 P6.0 bidirectional GPIO port 6 bit 0 with tcpwm.line[4], SCB3 UART RX/I2C SCL/SPI MOSI and can.can_tx_enb_n alternate functions.
13 P6.1 bidirectional GPIO port 6 bit 1 with tcpwm.line_compl[4], SCB3 UART TX/I2C SDA/SPI MISO and can.can_rx alternate functions.
14 P6.2 bidirectional GPIO port 6 bit 2 with tcpwm.line[5], scb[3].uart_cts, can.can_tx and scb[3].spi_clk alternate functions.
15 P6.4 bidirectional GPIO port 6 bit 4 with tcpwm.line[6], scb[4].i2c_scl and scb[3].spi_select1 alternate functions.
16 P6.5 bidirectional GPIO port 6 bit 5 with tcpwm.line_compl[6], scb[4].i2c_sda and scb[3].spi_select2 alternate functions.
17 VSSD power_in Ground pin for the digital section.
18 P3.0 bidirectional GPIO port 3 bit 0 with SmartIo[1].io[0], tcpwm.line[0] and SCB1 UART RX/I2C SCL/SPI MOSI alternate functions.
19 P3.1 bidirectional GPIO port 3 bit 1 with SmartIo[1].io[1], tcpwm.line_compl[0] and SCB1 UART TX/I2C SDA/SPI MISO alternate functions.
20 P3.2 bidirectional GPIO port 3 bit 2 with SmartIo[1].io[2], tcpwm.line[1], cpuss.swd_data and scb[1].spi_clk alternate functions.
21 P3.3 bidirectional GPIO port 3 bit 3 with SmartIo[1].io[3], tcpwm.line_compl[1], cpuss.swd_clk and scb[1].spi_select0 alternate functions.
22 P3.4 bidirectional GPIO port 3 bit 4 with SmartIo[1].io[4], tcpwm.line[2], tcpwm.tr_in[6] and scb[1].spi_select1 alternate functions.
23 P3.5 bidirectional GPIO port 3 bit 5 with SmartIo[1].io[5], tcpwm.line_compl[2] and scb[1].spi_select2 alternate functions.
24 P3.6 bidirectional GPIO port 3 bit 6 with SmartIo[1].io[6], tcpwm.line[3], scb[4].spi_select3 and scb[1].spi_select3 alternate functions.
25 P3.7 bidirectional GPIO port 3 bit 7 with SmartIo[1].io[7], tcpwm.line_compl[3], lpcomp.comp[1] and scb[2].spi_miso alternate functions.
26 VDDD power_in Power supply for the digital section.
27 P4.0 bidirectional GPIO port 4 bit 0 with csd.vref_ext, SCB0 UART RX/I2C SCL/SPI MOSI and can.can_rx alternate functions.
28 P4.1 bidirectional GPIO port 4 bit 1 with csd.cshield, SCB0 UART TX/I2C SDA/SPI MISO and can.can_tx alternate functions.
29 P4.2 bidirectional GPIO port 4 bit 2 with csd.cmod, scb[0].uart_cts, can.can_tx_enb_n, lpcomp.comp[0] and scb[0].spi_clk alternate functions.
30 P4.3 bidirectional GPIO port 4 bit 3 with csd.csh_tank, scb[0].uart_rts, lpcomp.comp[1] and scb[0].spi_select0 alternate functions.
31 P4.4 bidirectional GPIO port 4 bit 4 with scb[4].uart_rx, scb[4].spi_mosi and scb[0].spi_select1 alternate functions.
32 P4.5 bidirectional GPIO port 4 bit 5 with scb[4].uart_tx, scb[4].spi_miso and scb[0].spi_select2 alternate functions.
33 P4.6 bidirectional GPIO port 4 bit 6 with scb[4].uart_cts, scb[4].spi_clk and scb[0].spi_select3 alternate functions.
34 P4.7 bidirectional GPIO port 4 bit 7 with scb[4].uart_rts and scb[4].spi_select0 alternate functions.
35 P5.6 bidirectional GPIO port 5 bit 6 with tcpwm.line[7], scb[4].spi_select1 and scb[2].spi_select3 alternate functions.
36 P5.7 bidirectional GPIO port 5 bit 7 with tcpwm.line_compl[7] and scb[4].spi_select2 alternate functions.
37 P7.0 bidirectional GPIO port 7 bit 0 with tcpwm.line[0] and SCB3 UART RX/I2C SCL/SPI MOSI alternate functions.
38 P7.1 bidirectional GPIO port 7 bit 1 with tcpwm.line_compl[0] and SCB3 UART TX/I2C SDA/SPI MISO alternate functions.
39 P0.0 bidirectional GPIO port 0 bit 0 with lpcomp.in_p[0], tcpwm.tr_in[0] and SCB2 UART CTS/I2C SCL alternate functions.
40 P0.1 bidirectional GPIO port 0 bit 1 with lpcomp.in_n[0], tcpwm.tr_in[1] and SCB2 UART RTS/I2C SDA alternate functions.
41 P0.2 bidirectional GPIO port 0 bit 2 with lpcomp.in_p[1] and scb[0].spi_select3 alternate functions.
42 P0.3 bidirectional GPIO port 0 bit 3 with lpcomp.in_n[1] and scb[2].spi_select0 alternate functions.
43 P0.4 bidirectional GPIO port 0 bit 4 with wco.wco_in (32-kHz watch crystal) and SCB1/SCB2 UART RX, SCB1 I2C SCL/SPI MOSI alternate functions.
44 P0.5 bidirectional GPIO port 0 bit 5 with wco.wco_out (32-kHz watch crystal) and SCB1/SCB2 UART TX, SCB1 I2C SDA/SPI MISO alternate functions.
45 P0.6 bidirectional GPIO port 0 bit 6 with exco.eco_in (external crystal), srss.ext_clk and scb[1].uart_cts alternate functions.
46 P0.7 bidirectional GPIO port 0 bit 7 with exco.eco_out (external crystal), tcpwm.line[0] and scb[1].uart_rts alternate functions.
47 XRES input External reset input pin.
48 VCCD power_out Regulated digital supply (1.8 V ±5%).
49 VSSD power_in Ground pin for the digital section.
50 VDDD power_in Power supply for the digital section.
51 P5.0 bidirectional GPIO port 5 bit 0 with tcpwm.line[4] and SCB2 UART RX/I2C SCL/SPI MOSI alternate functions.
52 P5.1 bidirectional GPIO port 5 bit 1 with tcpwm.line_compl[4] and SCB2 UART TX/I2C SDA/SPI MISO alternate functions.
53 P5.2 bidirectional GPIO port 5 bit 2 with tcpwm.line[5], scb[2].uart_cts, lpcomp.comp[0] and scb[2].spi_clk alternate functions.
54 P5.3 bidirectional GPIO port 5 bit 3 with tcpwm.line_compl[5], scb[2].uart_rts, lpcomp.comp[1] and scb[2].spi_select0 alternate functions.
55 P5.5 bidirectional GPIO port 5 bit 5 with tcpwm.line_compl[6] and scb[2].spi_select2 alternate functions.
56 VDDA power_in Power supply for the analog section.
57 VSSA power_in Ground pin for the analog section.
58 P1.0 bidirectional GPIO port 1 bit 0 with opamp ctb0_oa0+, SmartIo[2].io[0], tcpwm.line[2] and SCB0 UART RX/I2C SCL/SPI MOSI alternate functions.
59 P1.1 bidirectional GPIO port 1 bit 1 with opamp ctb0_oa0-, SmartIo[2].io[1], tcpwm.line_compl[2] and SCB0 UART TX/I2C SDA/SPI MISO alternate functions.
60 P1.2 bidirectional GPIO port 1 bit 2 with opamp output ctb0_oa0_out, SmartIo[2].io[2], tcpwm.line[3] and scb[0].uart_cts alternate functions.
61 P1.3 bidirectional GPIO port 1 bit 3 with opamp output ctb0_oa1_out, SmartIo[2].io[3], tcpwm.line_compl[3] and scb[0].uart_rts alternate functions.
62 P1.4 bidirectional GPIO port 1 bit 4 with opamp ctb0_oa1-, SmartIo[2].io[4], tcpwm.line[6] and scb[3].i2c_scl alternate functions.
63 P1.5 bidirectional GPIO port 1 bit 5 with opamp ctb0_oa1+, SmartIo[2].io[5], tcpwm.line_compl[6] and scb[3].i2c_sda alternate functions.
64 P1.6 bidirectional GPIO port 1 bit 6 with opamp ctb0_oa0+, SmartIo[2].io[6], tcpwm.line[7] and scb[0].spi_select3 alternate functions.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package TQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 15
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 15
GPIO voltage VGPIO_ABS -0.5 V Max is VDD+0.5 15
Maximum current per GPIO IGPIO_ABS -25 25 mA 15
GPIO injection current IGPIO_injection -0.5 0.5 mA Max for VIH > VDDD, Min for VIL < VSS; current injected per pin 15
ESD human body model ESD_HBM 2200 V 15
ESD charged device model ESD_CDM 500 V 15
Pin current for latch-up LU -140 140 mA 15
Power supply input voltage VDD 1.8 5.5 V Internally regulated supply 15
Power supply input voltage (VCCD = VDDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 15
Active mode current, CPU at 6 MHz IDD5 1.8 2.4 mA Execute from flash; CPU at 6 MHz; VDD = 1.8 V to 5.5 V 15
Active mode current, CPU at 24 MHz IDD8 3 4.6 mA Execute from flash; CPU at 24 MHz; VDD = 1.8 V to 5.5 V 15
Active mode current, CPU at 48 MHz IDD11 5.4 7.1 mA Execute from flash; CPU at 48 MHz; VDD = 1.8 V to 5.5 V 15
Sleep current, 6 MHz IDD17 1.1 1.8 mA I2C wakeup, WDT, and Comparators on; 6 MHz; VDDD = 1.8 V to 5.5 V 15
Sleep current, 12 MHz IDD20 1.5 2.1 mA I2C wakeup, WDT, and Comparators on; 12 MHz; VDDD = 1.8 V to 5.5 V 15
Sleep current, 6 MHz (regulator bypassed) IDD23 1.1 1.8 mA I2C wakeup, WDT, and Comparators on; 6 MHz; VDDD = 1.71 V to 1.89 V 16
Sleep current, 12 MHz (regulator bypassed) IDD23A 1.5 2.1 mA I2C wakeup, WDT, and Comparators on; 12 MHz; VDDD = 1.71 V to 1.89 V 16
Deep Sleep current, -40 to 60 °C IDD25 2.5 40 µA VDD = 1.8 V to 3.6 V; I2C wakeup and WDT on; T = -40 °C to 60 °C 16
Deep Sleep current IDD26 2.5 125 µA VDD = 1.8 V to 3.6 V; I2C wakeup and WDT on; Max is at 3.6 V and 85 °C 16
Deep Sleep current, -40 to 60 °C (regulator bypassed) IDD31 2.5 60 µA VDD = VCCD = 1.71 V to 1.89 V; I2C wakeup and WDT on; T = -40 °C to 60 °C 16
Deep Sleep current (regulator bypassed) IDD32 2.5 180 µA VDD = VCCD = 1.71 V to 1.89 V; I2C wakeup and WDT on; Max is at 1.89 V and 85 °C 16
Supply current while XRES asserted IDD_XR 2 5 mA 16
CPU frequency FCPU 0 48 MHz 1.71 ≤ VDD ≤ 5.5 16
SWD clock frequency F_SWDCLK1 14 MHz 3.3 V ≤ VDD ≤ 5.5 V; SWDCLK ≤ 1/3 CPU clock frequency 30
SWD clock frequency F_SWDCLK2 7 MHz 1.71 V ≤ VDD ≤ 3.3 V; SWDCLK ≤ 1/3 CPU clock frequency 30
IMO frequency variation FIMOTOL1 -2 2 % Frequency variation at 24, 32, and 48 MHz (trimmed) 30
IMO startup time TSTARTIMO 7 µs 30
ILO duty cycle TILODUTY 40 50 60 % 30
ILO frequency range FILOTRIM1 20 40 80 kHz 30
Operating ambient temperature TA -40 25 105 °C 36
Operating junction temperature TJ -40 125 °C 36
Package thermal resistance θJA TJA 46 °C/Watt 64-pin TQFP (0.5-mm pitch) 36
Package thermal resistance θJC TJC 10 °C/Watt 64-pin TQFP (0.5-mm pitch) 36

CAD (KiCad official)

  • Symbol: CY8C4147AZI-S455
  • Footprint: Package_QFP:TQFP-64_10x10mm_P0.5mm
  • 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: cy8c4147azi-s455-etched.step / cy8c4147azi-s455-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4147azi-s455.step / cy8c4147azi-s455.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (44 pp, sha256 dbd64085f5f9728a, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF