component

CY8C4146LQI-S423

Public Made by Adom

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy8c4146lqi-s423factory-2.0.0extractor-text

Verified CY8C4146LQI-S423

by Ray · last 12 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

12 Nov 2026RayPublished by the parts factory: tier mfr, 41 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY8C4146LQI-S423 · QFN-40-EP(6x6) · 41 pins
  • ✓copper: 41 copper pads, none touching another net
  • ✓datasheet: all 41 pin names found in the 66-page datasheet
  • ✓distributor: lcsc C2948687, digikey CY8C4146LQI-S423-ND, mouser 727-CY8C4146LQI-S423
  • ✓family: QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-5urwjnhc/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height within the datasheet's package drawing (datasheet p.49)
  • ✓pads: 41 pins = 41 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 41 pins agree
  • ✓symbol_text: no pin names collide
  • ✓viewers: viewers/footprint.html 52 kB, viewers/symbol.html 28 kB
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy8c4146lqi-s423.kicad_sym✓ cy8c4146lqi-s423.kicad_mod✓ cy8c4146lqi-s423.step
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CY8C4146LQI-S423

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-40-EP(6x6)

CY8C4146LQI-S423 from Cypress Semicon, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model). Symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2.0 bidirectional GPIO port 2.0 (any GPIO can be CAPSENSE, analog or digital); alternate functions include sarmux[0], tcpwm.line[4]:0, csd.comp and scb[1].i2c_scl:1 per Table 2.
2 P2.1 bidirectional GPIO port 2.1 (any GPIO can be CAPSENSE, analog or digital); alternate functions include sarmux[1], tcpwm.line_compl[4]:0, tcpwm.tr_in[5] and scb[1].i2c_sda:1 per Table 2.
3 P2.2 bidirectional GPIO port 2.2 (any GPIO can be CAPSENSE, analog or digital); alternate functions include sarmux[2], SmartIo[0].io[2] and scb[1].spi_clk:2 per Table 2.
4 P2.3 bidirectional GPIO port 2.3 (any GPIO can be CAPSENSE, analog or digital); alternate functions include sarmux[3], SmartIo[0].io[3] and scb[1].spi_select0:2 per Table 2.
5 P2.4 bidirectional GPIO port 2.4 (any GPIO can be CAPSENSE, analog or digital); alternate functions include sarmux[4], SmartIo[0].io[4], tcpwm.line[0]:1 and scb[1].spi_select1:1 per Table 2.
6 P2.5 bidirectional GPIO port 2.5 (any GPIO can be CAPSENSE, analog or digital); alternate functions include sarmux[5], SmartIo[0].io[5], tcpwm.line_compl[0]:1 and scb[1].spi_select2:1 per Table 2.
7 P2.6 bidirectional GPIO port 2.6 (any GPIO can be CAPSENSE, analog or digital); alternate functions include sarmux[6], SmartIo[0].io[6], tcpwm.line[1]:1 and scb[1].spi_select3:1 per Table 2.
8 P2.7 bidirectional GPIO port 2.7 (any GPIO can be CAPSENSE, analog or digital); alternate functions include sarmux[7], SmartIo[0].io[7], tcpwm.line_compl[1]:1, lpcomp.comp[0]:1 and scb[2].spi_mosi per Table 2.
9 VSSD power_in Ground pin for the digital section.
10 P3.0 bidirectional GPIO port 3.0 (any GPIO can be CAPSENSE, analog or digital); alternate functions include SmartIo[1].io[0], tcpwm.line[0]:0, scb[1].uart_rx:1 and scb[1].spi_mosi:0 per Table 2.
11 P3.1 bidirectional GPIO port 3.1 (any GPIO can be CAPSENSE, analog or digital); alternate functions include SmartIo[1].io[1], tcpwm.line_compl[0]:0, scb[1].uart_tx:1 and scb[1].spi_miso:0 per Table 2.
12 P3.2 bidirectional GPIO port 3.2 (any GPIO can be CAPSENSE, analog or digital); alternate functions include SmartIo[1].io[2], tcpwm.line[1]:0, cpuss.swd_data and scb[1].spi_clk:0 per Table 2.
13 P3.3 bidirectional GPIO port 3.3 (any GPIO can be CAPSENSE, analog or digital); alternate functions include SmartIo[1].io[3], tcpwm.line_compl[1]:0, cpuss.swd_clk and scb[1].spi_select0:0 per Table 2.
14 P3.4 bidirectional GPIO port 3.4 (any GPIO can be CAPSENSE, analog or digital); alternate functions include SmartIo[1].io[4], tcpwm.line[2]:0, tcpwm.tr_in[6] and scb[1].spi_select1:0 per Table 2.
15 P3.5 bidirectional GPIO port 3.5 (any GPIO can be CAPSENSE, analog or digital); alternate functions include SmartIo[1].io[5], tcpwm.line_compl[2]:0 and scb[1].spi_select2:0 per Table 2.
16 P3.6 bidirectional GPIO port 3.6 (any GPIO can be CAPSENSE, analog or digital); alternate functions include SmartIo[1].io[6], tcpwm.line[3]:0 and scb[1].spi_select3:0 per Table 2.
17 P3.7 bidirectional GPIO port 3.7 (any GPIO can be CAPSENSE, analog or digital); alternate functions include SmartIo[1].io[7], tcpwm.line_compl[3]:0, lpcomp.comp[1]:1 and scb[2].spi_miso per Table 2.
18 P4.0 bidirectional GPIO port 4.0 (any GPIO can be CAPSENSE, analog or digital); alternate functions include csd.vref_ext, scb[0].uart_rx:0, scb[0].i2c_scl:1 and scb[0].spi_mosi:0 per Table 2.
19 P4.1 bidirectional GPIO port 4.1 (any GPIO can be CAPSENSE, analog or digital); alternate functions include csd.cshieldpads, scb[0].uart_tx:0, scb[0].i2c_sda:1 and scb[0].spi_miso:0 per Table 2.
20 P4.2 bidirectional GPIO port 4.2 (any GPIO can be CAPSENSE, analog or digital); alternate functions include csd.cmodpad, scb[0].uart_cts:0, lpcomp.comp[0]:0 and scb[0].spi_clk:0 per Table 2.
21 P4.3 bidirectional GPIO port 4.3 (any GPIO can be CAPSENSE, analog or digital); alternate functions include csd.csh_tank, scb[0].uart_rts:0, lpcomp.comp[1]:0 and scb[0].spi_select0:0 per Table 2.
22 P0.0 bidirectional GPIO port 0.0 (any GPIO can be CAPSENSE, analog or digital); alternate functions include lpcomp.in_p[0], tcpwm.tr_in[0], scb[2].i2c_scl:0 and scb[0].spi_select1:0 per Table 2.
23 P0.1 bidirectional GPIO port 0.1 (any GPIO can be CAPSENSE, analog or digital); alternate functions include lpcomp.in_n[0], tcpwm.tr_in[1], scb[2].i2c_sda:0 and scb[0].spi_select2:0 per Table 2.
24 P0.2 bidirectional GPIO port 0.2 (any GPIO can be CAPSENSE, analog or digital); alternate functions include lpcomp.in_p[1] and scb[0].spi_select3:0 per Table 2.
25 P0.3 bidirectional GPIO port 0.3 (any GPIO can be CAPSENSE, analog or digital); alternate functions include lpcomp.in_n[1] and scb[2].spi_select0 per Table 2.
26 P0.4 bidirectional GPIO port 0.4 (any GPIO can be CAPSENSE, analog or digital); alternate functions include wco.wco_in, scb[1].uart_rx:0, scb[2].uart_rx:0, scb[1].i2c_scl:0 and scb[1].spi_mosi:1 per Table 2.
27 P0.5 bidirectional GPIO port 0.5 (any GPIO can be CAPSENSE, analog or digital); alternate functions include wco.wco_out, scb[1].uart_tx:0, scb[2].uart_tx:0, scb[1].i2c_sda:0 and scb[1].spi_miso:1 per Table 2.
28 P0.6 bidirectional GPIO port 0.6 (any GPIO can be CAPSENSE, analog or digital); alternate functions include srss.ext_clk, scb[1].uart_cts:0, scb[2].uart_tx:1 and scb[1].spi_clk:1 per Table 2.
29 P0.7 bidirectional GPIO port 0.7 (any GPIO can be CAPSENSE, analog or digital); alternate functions include tcpwm.line[0]:2, scb[1].uart_rts:0 and scb[1].spi_select0:1 per Table 2.
30 XRES input External reset input (XRES); its electrical limits are given in section 5.2.2, which is not part of the supplied text.
31 VCCD power_out Regulated digital supply output of 1.8 V ± 5% that must be bypassed to ground with a 0.1 µF X5R (or better) capacitor and must not be connected to anything else in Mode 1.
32 VDDD power_in Power supply for the digital section.
33 VDDA power_in Power supply for the analog section, which runs directly from VDD with no analog regulator.
34 VSSA power_in Ground pin for the analog section.
35 P1.0 bidirectional GPIO port 1.0 (any GPIO can be CAPSENSE, analog or digital); alternate functions include ctb0_oa0+, tcpwm.line[2]:1, scb[0].uart_rx:1, scb[0].i2c_scl:0 and scb[0].spi_mosi:1 per Table 2.
36 P1.1 bidirectional GPIO port 1.1 (any GPIO can be CAPSENSE, analog or digital); alternate functions include ctb0_oa0-, tcpwm.line_compl[2]:1, scb[0].uart_tx:1, scb[0].i2c_sda:0 and scb[0].spi_miso:1 per Table 2.
37 P1.2 bidirectional GPIO port 1.2 (any GPIO can be CAPSENSE, analog or digital); alternate functions include ctb0_oa0_out, tcpwm.line[3]:1, scb[0].uart_cts:1, tcpwm.tr_in[2], scb[2].i2c_scl:1 and scb[0].spi_clk:1 per Table 2.
38 P1.3 bidirectional GPIO port 1.3 (any GPIO can be CAPSENSE, analog or digital); alternate functions include ctb0_oa1_out, tcpwm.line_compl[3]:1, scb[0].uart_rts:1, tcpwm.tr_in[3], scb[2].i2c_sda:1 and scb[0].spi_select0:1 per Table 2.
39 P1.4 bidirectional GPIO port 1.4 (any GPIO can be CAPSENSE, analog or digital); alternate functions include ctb0_oa1- and scb[0].spi_select1:1 per Table 2.
40 P1.7/VREF bidirectional GPIO port 1.7 (any GPIO can be CAPSENSE, analog or digital); alternate functions include ctb0_oa1+, sar_ext_vref0, sar_ext_vref1 and scb[2].spi_clk per Table 2.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-40-EP(6x6)
Category Single Chip Microcomputer/Microcontroller
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 22
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 22
GPIO voltage VGPIO_ABS -0.5 V 22
Maximum current per GPIO IGPIO_ABS -25 25 mA 22
GPIO injection current IGPIO_injection -0.5 0.5 Current injected per pin 22
Electrostatic discharge human body model ESD_HBM 2200 V 22
Electrostatic discharge charged device model ESD_CDM 500 22
Pin current for latch-up LU -140 140 mA 22
Maximum storage temperature 150 °C In compliance with JEDEC JESD22-A103 22
Power supply input voltage VDD 1.8 5.5 V Internally regulated supply 22
Power supply input voltage (VCCD = VDDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 22
Active mode current, execute from flash at 6 MHz IDD5 1.8 2.7 mA Execute from flash; CPU at 6 MHz. Max is at 85°C and 5.5 V 23
Active mode current, execute from flash at 24 MHz IDD8 3 4.75 mA Execute from flash; CPU at 24 MHz 23
Active mode current, execute from flash at 48 MHz IDD11 5.4 6.85 mA Execute from flash; CPU at 48 MHz 23
Sleep mode current (regulator on), 6 MHz IDD17 1.7 2.2 mA I2C wakeup WDT, and comparators on; 6 MHz. Max is at 85°C and 5.5 V. 23
Sleep mode current (regulator on), 12 MHz IDD20 2.2 2.5 mA I2C wakeup, WDT, and comparators on; 12 MHz. Max is at 85°C and 5.5 V 23
Sleep mode current (regulator bypassed), 6 MHz IDD23 0.7 0.9 mA I2C wakeup, WDT, and comparators on; 6 MHz. Max is at 85°C and 5.5 V. 23
Sleep mode current (regulator bypassed), 12 MHz IDD23A 1 1.2 mA I2C wakeup, WDT, and comparators on; 12 MHz. Max is at 85°C and 5.5 V 23
Deep Sleep mode current (VDD 1.8 V to 3.6 V, regulator on) IDD26 2.5 60 µA I2C wakeup and WDT on; Max is at 3.6 V and 85°C. 23
Deep Sleep mode current (VDD 3.6 V to 5.5 V, regulator on) IDD29 2.5 60 µA I2C wakeup and WDT on; Max is at 5.5 V and 85°C. 23
Deep Sleep mode current (VDD = VCCD 1.71 V to 1.89 V, regulator bypassed) IDD32 2.5 65 µA I2C wakeup and WDT on; Max is at 1.89 V and 85°C. 23
XRES supply current while asserted IDD_XR 2 5 mA 23
CPU frequency FCPU 48 MHz 1.71 ≤ VDD ≤ 5.5 23
Frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % At -40°C to 85°C, for industrial temperature range and original extended industrial range parts 41
IMO operating current at 48 MHz IIMO1 250 µA 41
IMO operating current at 24 MHz IIMO2 180 41
IMO startup time TSTARTIMO 7 µs 41
ILO operating current IILO1 0.3 1.05 µA 42
ILO startup time TSTARTILO1 2 ms 42
ILO duty cycle TILODUTY 40 50 60 % 42
ILO frequency range FILOTRIM1 20 40 80 kHz 42
Frequency tolerance (WCO) FTOL 50 250 ppm With 20-ppm crystal 42
WCO drive level PD 1 µW 42
WCO startup time TSTART 500 ms 43
WCO crystal load capacitance CL 6 12.5 pF 43
WCO operating current (high power mode) IWCO1 8 mA 43
WCO operating current (low power mode) IWCO2 1 43
External clock input frequency ExtClkFreq 0 48 MHz 43
External clock duty cycle ExtClkDuty 45 55 % Measured at VDD/2 43
System clock source switching time TCLKSWITCH 3 4 Periods 43
Smart I/O pass-through delay in Bypass mode PRG_BYPASS 1.6 ns 43
SWD clock frequency, 3.3 V ≤ VDD ≤ 5.5 V F_SWDCLK1 14 MHz 3.3 V ≤ VDD ≤ 5.5 V; SWDCLK ≤ 1/3 CPU clock frequency 41
SWD clock frequency, 1.71 V ≤ VDD ≤ 3.3 V F_SWDCLK2 7 1.71 V ≤ VDD ≤ 3.3 V; SWDCLK ≤ 1/3 CPU clock frequency 41
SWD output hold time T_SWDO_HOLD 1 T = 1/f SWDCLK 41
Operating ambient temperature TA -40 25 105 °C 49
Operating junction temperature TJ -40 125 °C 49
Maximum peak solder reflow temperature 260 °C Maximum time at peak temperature 30 seconds 49
External regulator voltage bypass capacitor CEFC 0.1 µF X5R ceramic or better 22
Power supply bypass capacitor CEXC 1 22
Crystal frequency (external 32.768 kHz watch crystal) FWCO 32.768 kHz 42
Equivalent series resistance (external crystal) ESR 50 kΩ 42
Crystal shunt capacitance C0 1.35 43
Package θJA, 40L QFN TJA 17.8 °C/W 49
Package θJC, 40L QFN TJC 2.8 °C/W 49

CAD (KiCad official)

  • Symbol: CY8C4146LQI-S423
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: QFN-40-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.6 mm tall, datasheet A, nominal). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions come from the datasheet drawing where it was read and are defaults otherwise (see provenance.model_3d_generated), not the manufacturer's CAD (STEP)
  • 3D model files: cy8c4146lqi-s423-etched.step / cy8c4146lqi-s423-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4146lqi-s423.step / cy8c4146lqi-s423.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (66 pp, sha256 077139eb014776df, retrieved 2026-11-12, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF