component
CY8C4146AZI-S445
Public Made by Adomby adom
Infineon Cypress Semicon Microcontrollers (MCU/MPU/SOC), TQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCY8C4146AZI-S445
Infineon Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · TQFP-64(10x10)
CY8C4146AZI-S445 from Infineon Cypress Semicon, in a TQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.7 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog functions ctb0_oa1+, sar_ext_vref0 and sar_ext_vref1, digital alternates include SmartIo[2].io[7], tcpwm.line_compl[7]:1 and scb[2].spi_clk:1. |
| 2 | P2.0 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function sarmux[0], digital alternates include SmartIo[0].io[0], tcpwm.line[4]:0, csd.comp, tcpwm.tr_in[4], scb[1].i2c_scl:1 and scb[1].spi_mosi:2. |
| 3 | P2.1 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function sarmux[1], digital alternates include SmartIo[0].io[1], tcpwm.line_compl[4]:0, tcpwm.tr_in[5], scb[1].i2c_sda:1 and scb[1].spi_miso:2. |
| 4 | P2.2 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function sarmux[2], digital alternates include SmartIo[0].io[2], tcpwm.line[5]:1 and scb[1].spi_clk:2. |
| 5 | P2.3 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function sarmux[3], digital alternates include SmartIo[0].io[3], tcpwm.line_compl[5]:1 and scb[1].spi_select0:2. |
| 6 | P2.4 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function sarmux[4], digital alternates include SmartIo[0].io[4], tcpwm.line[0]:1, scb[3].uart_rx:1 and scb[1].spi_select1:1. |
| 7 | P2.5 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function sarmux[5], digital alternates include SmartIo[0].io[5], tcpwm.line_compl[0]:1, scb[3].uart_tx:1 and scb[1].spi_select2:1. |
| 8 | P2.6 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function sarmux[6], digital alternates include SmartIo[0].io[6], tcpwm.line[1]:1, scb[3].uart_cts:1 and scb[1].spi_select3:1. |
| 9 | P2.7 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function sarmux[7], digital alternates include SmartIo[0].io[7], tcpwm.line_compl[1]:1, scb[3].uart_rts:1, lpcomp.comp[0]:0 and scb[2].spi_mosi:1. |
| 10 | VSSD | power_in | Ground pin for the digital section. |
| 11 | NC | unconnected | No connection. |
| 12 | P6.0 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line[4]:1, scb[3].uart_rx:0, can.can_tx_enb_n:0, scb[3].i2c_scl:1 and scb[3].spi_mosi:0. |
| 13 | P6.1 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line_compl[4]:1, scb[3].uart_tx:0, can.can_rx:0, scb[3].i2c_sda:1 and scb[3].spi_miso:0. |
| 14 | P6.2 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line[5]:0, scb[3].uart_cts:0, can.can_tx:0 and scb[3].spi_clk:0. |
| 15 | P6.4 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line[6]:0, scb[4].i2c_scl and scb[3].spi_select1:0. |
| 16 | P6.5 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line_compl[6]:0, scb[4].i2c_sda and scb[3].spi_select2:0. |
| 17 | VSSD | power_in | Ground pin for the digital section. |
| 18 | P3.0 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include SmartIo[1].io[0], tcpwm.line[0]:0, scb[1].uart_rx:1, scb[1].i2c_scl:2 and scb[1].spi_mosi:0. |
| 19 | P3.1 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include SmartIo[1].io[1], tcpwm.line_compl[0]:0, scb[1].uart_tx:1, scb[1].i2c_sda:2 and scb[1].spi_miso:0. |
| 20 | P3.2 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include SmartIo[1].io[2], tcpwm.line[1]:0, scb[1].uart_cts:1, cpuss.swd_data and scb[1].spi_clk:0. |
| 21 | P3.3 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include SmartIo[1].io[3], tcpwm.line_compl[1]:0, scb[1].uart_rts:1, cpuss.swd_clk and scb[1].spi_select0:0. |
| 22 | P3.4 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include SmartIo[1].io[4], tcpwm.line[2]:0, tcpwm.tr_in[6] and scb[1].spi_select1:0. |
| 23 | P3.5 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include SmartIo[1].io[5], tcpwm.line_compl[2]:0 and scb[1].spi_select2:0. |
| 24 | P3.6 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include SmartIo[1].io[6], tcpwm.line[3]:0, scb[4].spi_select3 and scb[1].spi_select3:0. |
| 25 | P3.7 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include SmartIo[1].io[7], tcpwm.line_compl[3]:0, lpcomp.comp[1]:1 and scb[2].spi_miso:1. |
| 26 | VDDD | power_in | Power supply for the digital section. |
| 27 | P4.0 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function csd.vref_ext, digital alternates include scb[0].uart_rx:0, can.can_rx:1, scb[0].i2c_scl:1 and scb[0].spi_mosi:0. |
| 28 | P4.1 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function csd.cshield, digital alternates include scb[0].uart_tx:0, can.can_tx:1, scb[0].i2c_sda:1 and scb[0].spi_miso:0. |
| 29 | P4.2 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function csd.cmod, digital alternates include scb[0].uart_cts:0, can.can_tx_enb_n:1, lpcomp.comp[0]:1 and scb[0].spi_clk:0. |
| 30 | P4.3 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function csd.csh_tank, digital alternates include scb[0].uart_rts:0, lpcomp.comp[1]:2 and scb[0].spi_select0:0. |
| 31 | P4.4 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include scb[4].uart_rx, scb[4].spi_mosi and scb[0].spi_select1:2. |
| 32 | P4.5 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include scb[4].uart_tx, scb[4].spi_miso and scb[0].spi_select2:2. |
| 33 | P4.6 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include scb[4].uart_cts, scb[4].spi_clk and scb[0].spi_select3:2. |
| 34 | P4.7 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include scb[4].uart_rts and scb[4].spi_select0. |
| 35 | P5.6 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line[7]:0, scb[4].spi_select1 and scb[2].spi_select3:0. |
| 36 | P5.7 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line_compl[7]:0 and scb[4].spi_select2. |
| 37 | P7.0 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line[0]:2, scb[3].uart_rx:2, scb[3].i2c_scl:2 and scb[3].spi_mosi:1. |
| 38 | P7.1 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line_compl[0]:2, scb[3].uart_tx:2, scb[3].i2c_sda:2 and scb[3].spi_miso:1. |
| 39 | P0.0 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function lpcomp.in_p[0], digital alternates include tcpwm.tr_in[0], scb[2].uart_cts:0, scb[2].i2c_scl:0 and scb[0].spi_select1:0. |
| 40 | P0.1 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function lpcomp.in_n[0], digital alternates include tcpwm.tr_in[1], scb[2].uart_rts:0, scb[2].i2c_sda:0 and scb[0].spi_select2:0. |
| 41 | P0.2 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function lpcomp.in_p[1], digital alternate scb[0].spi_select3:0. |
| 42 | P0.3 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function lpcomp.in_n[1], digital alternate scb[2].spi_select0:1. |
| 43 | P0.4 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function wco.wco_in, digital alternates include scb[1].uart_rx:0, scb[2].uart_rx:0, scb[1].i2c_scl:0 and scb[1].spi_mosi:1. |
| 44 | P0.5 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function wco.wco_out, digital alternates include scb[1].uart_tx:0, scb[2].uart_tx:0, scb[1].i2c_sda:0 and scb[1].spi_miso:1. |
| 45 | P0.6 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function exco.eco_in, digital alternates include srss.ext_clk:0, scb[1].uart_cts:0, scb[2].uart_tx:1, and scb[1].spi_clk:1. |
| 46 | P0.7 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function exco.eco_out, digital alternates include tcpwm.line[0]:3, scb[1].uart_rts:0 and scb[1].spi_select0:1. |
| 47 | XRES | input | External reset pin; this excerpt gives no electrical limits for it. |
| 48 | VCCD | power_out | Regulated digital supply, 1.8 V ±5%. |
| 49 | VSSD | power_in | Ground pin for the digital section. |
| 50 | VDDD | power_in | Power supply for the digital section. |
| 51 | P5.0 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line[4]:2, scb[2].uart_rx:1, scb[2].i2c_scl:1 and scb[2].spi_mosi:0. |
| 52 | P5.1 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line_compl[4]:2, scb[2].uart_tx:2, scb[2].i2c_sda:1 and scb[2].spi_miso:0. |
| 53 | P5.2 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line[5]:2, scb[2].uart_cts:1, lpcomp.comp[0]:2 and scb[2].spi_clk:0. |
| 54 | P5.3 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line_compl[5]:2, scb[2].uart_rts:1, lpcomp.comp[1]:0 and scb[2].spi_select0:0. |
| 55 | P5.5 | bidirectional | GPIO that can be configured as CapSense, analog or digital; digital alternates include tcpwm.line_compl[6]:2 and scb[2].spi_select2:0. |
| 56 | VDDA | power_in | Power supply for the analog section. |
| 57 | VSSA | power_in | Ground pin for the analog section. |
| 58 | P1.0 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function ctb0_oa0+, digital alternates include SmartIo[2].io[0], tcpwm.line[2]:1, scb[0].uart_rx:1, scb[0].i2c_scl:0 and scb[0].spi_mosi:1. |
| 59 | P1.1 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function ctb0_oa0-, digital alternates include SmartIo[2].io[1], tcpwm.line_compl[2]:1, scb[0].uart_tx:1, scb[0].i2c_sda:0 and scb[0].spi_miso:1. |
| 60 | P1.2 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function ctb0_oa0_out, digital alternates include SmartIo[2].io[2], tcpwm.line[3]:1, scb[0].uart_cts:1, tcpwm.tr_in[2], scb[2].i2c_scl:2 and scb[0].spi_clk:1. |
| 61 | P1.3 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function ctb0_oa1_out, digital alternates include SmartIo[2].io[3], tcpwm.line_compl[3]:1, scb[0].uart_rts:1, tcpwm.tr_in[3], scb[2].i2c_sda:2 and scb[0].spi_select0:1. |
| 62 | P1.4 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function ctb0_oa1-, digital alternates include SmartIo[2].io[4], tcpwm.line[6]:1, scb[3].i2c_scl:0 and scb[0].spi_select1:1. |
| 63 | P1.5 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function ctb0_oa1+, digital alternates include SmartIo[2].io[5], tcpwm.line_compl[6]:1, scb[3].i2c_sda:0 and scb[0].spi_select2:1. |
| 64 | P1.6 | bidirectional | GPIO that can be configured as CapSense, analog or digital; analog function ctb0_oa0+ as printed in the alternate function table, digital alternates include SmartIo[2].io[6], tcpwm.line[7]:1 and scb[0].spi_select3:1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Cypress Semicon |
| Package | TQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Digital supply relative to VSS (absolute maximum) | VDDD_ABS | -0.5 | 6 | V | 15 | ||
| Direct digital core voltage input relative to VSS (absolute maximum) | VCCD_ABS | -0.5 | 1.95 | V | 15 | ||
| GPIO voltage (absolute maximum) | VGPIO_ABS | -0.5 | V | 15 | |||
| Maximum current per GPIO (absolute maximum) | IGPIO_ABS | -25 | 25 | mA | 15 | ||
| GPIO injection current, max for VIH > VDDD, min for VIL < VSS (absolute maximum) | IGPIO_injection | -0.5 | 0.5 | mA | Current injected per pin | 15 | |
| Electrostatic discharge human body model (ESD_HBM) | ESD_HBM | 2200 | V | 15 | |||
| Electrostatic discharge charged device model (ESD_CDM) | ESD_CDM | 500 | V | 15 | |||
| Pin current for latch-up (LU) | LU | -140 | 140 | mA | 15 | ||
| Power supply input voltage, internally regulated supply | VDD | 1.8 | 5.5 | V | Internally regulated supply | 15 | |
| Power supply input voltage (VCCD = VDDD = VDDA), internally unregulated supply | VDD | 1.71 | 1.89 | V | Internally unregulated supply | 15 | |
| Execute from flash; CPU at 6 MHz (IDD5) | IDD5 | 1.8 | 2.4 | mA | Active mode, VDD = 1.8 V to 5.5 V; typ at VDD 3.3 V and 25 °C | 15 | |
| Execute from flash; CPU at 24 MHz (IDD8) | IDD8 | 3 | 4.6 | mA | Active mode, VDD = 1.8 V to 5.5 V; typ at VDD 3.3 V and 25 °C | 15 | |
| Execute from flash; CPU at 48 MHz (IDD11) | IDD11 | 5.4 | 7.1 | mA | Active mode, VDD = 1.8 V to 5.5 V; typ at VDD 3.3 V and 25 °C | 15 | |
| I2C wakeup, WDT, and Comparators on, 6 MHz (IDD17) | IDD17 | 1.1 | 1.8 | mA | Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on) | 15 | |
| I2C wakeup, WDT, and Comparators on, 12 MHz (IDD20) | IDD20 | 1.5 | 2.1 | mA | Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on) | 15 | |
| I2C wakeup, WDT, and Comparators on, 6 MHz (IDD23) | IDD23 | 1.1 | 1.8 | mA | Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed) | 16 | |
| I2C wakeup, WDT, and Comparators on, 12 MHz (IDD23A) | IDD23A | 1.5 | 2.1 | mA | Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed) | 16 | |
| I2C wakeup and WDT on; T = -40 °C to 60 °C (IDD25) | IDD25 | 2.5 | 40 | µA | Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on); T = -40 °C to 60 °C | 16 | |
| I2C wakeup and WDT on (IDD26) | IDD26 | 2.5 | 125 | µA | Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on); max is at 3.6 V and 85 °C | 16 | |
| I2C wakeup and WDT on; T = -40 °C to 60 °C (IDD28) | IDD28 | 2.5 | 40 | µA | Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on); T = -40 °C to 60 °C | 16 | |
| I2C wakeup and WDT on (IDD29) | IDD29 | 2.5 | 125 | µA | Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on); max is at 5.5 V and 85 °C | 16 | |
| I2C wakeup and WDT on; T = -40 °C to 60 °C (IDD31) | IDD31 | 2.5 | 60 | µA | Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed); T = -40 °C to 60 °C | 16 | |
| I2C wakeup and WDT on (IDD32) | IDD32 | 2.5 | 180 | µA | Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed); max is at 1.89 V and 85 °C | 16 | |
| Supply current while XRES asserted (IDD_XR) | IDD_XR | 2 | 5 | mA | 16 | ||
| CPU frequency (FCPU) | FCPU | 48 | MHz | 1.71 V ≤ VDD ≤ 5.5 V; minimum printed as DC | 16 | ||
| SWDCLK frequency (F_SWDCLK1) | F_SWDCLK1 | 14 | MHz | 3.3 V ≤ VDD ≤ 5.5 V; SWDCLK ≤ 1/3 CPU clock frequency | 30 | ||
| SWDCLK frequency (F_SWDCLK2) | F_SWDCLK2 | 7 | MHz | 1.71 V ≤ VDD ≤ 3.3 V; SWDCLK ≤ 1/3 CPU clock frequency | 30 | ||
| SWDO hold time (T_SWDO_HOLD) | T_SWDO_HOLD | 1 | ns | T = 1/f SWDCLK | 30 | ||
| IMO operating current at 48 MHz (IIMO1) | IIMO1 | 250 | µA | 30 | |||
| IMO operating current at 24 MHz (IIMO2) | IIMO2 | 180 | µA | 30 | |||
| Frequency variation at 24, 32, and 48 MHz (trimmed) (FIMOTOL1) | FIMOTOL1 | -2 | 2 | % | Trimmed | 30 | |
| IMO startup time (TSTARTIMO) | TSTARTIMO | 7 | µs | 30 | |||
| ILO operating current (IILO1) | IILO1 | 0.3 | 1.05 | µA | Guaranteed by design | 30 | |
| ILO startup time (TSTARTILO1) | TSTARTILO1 | 2 | ms | 30 | |||
| ILO duty cycle (TILODUTY) | TILODUTY | 40 | 50 | 60 | % | 30 | |
| ILO frequency range (FILOTRIM1) | FILOTRIM1 | 20 | 40 | 80 | kHz | 30 | |
| Frequency tolerance (FTOL, WCO) | FTOL | 50 | 250 | ppm | With 20-ppm crystal | 31 | |
| Drive level (PD, WCO) | PD | 1 | µW | 31 | |||
| Startup time (TSTART, WCO) | TSTART | 500 | ms | 31 | |||
| Crystal load capacitance (CL, WCO) | CL | 6 | 12.5 | pF | 31 | ||
| Operating current, high power mode (IWCO1) | IWCO1 | 8 | uA | 31 | |||
| External clock input frequency (ExtClkFreq) | ExtClkFreq | 0 | 48 | MHz | 31 | ||
| Duty cycle (ExtClkDuty) | ExtClkDuty | 45 | 55 | % | Measured at VDD/2 | 31 | |
| Row labelled 'External clock input frequency' in ECO table (IECO1) | IECO1 | 1.5 | mA | 31 | |||
| Crystal frequency range (FECO) | FECO | 4 | 33 | MHz | 31 | ||
| PLL operating current, In = 3 MHz, Out = 48 MHz (IDD_PLL_48) | IDD_PLL_48 | 530 | 610 | uA | In = 3 MHz, Out = 48 MHz | 31 | |
| PLL input frequency (Fpllin) | Fpllin | 1 | 48 | MHz | 31 | ||
| PLL intermediate frequency; prescaler out (Fpllint) | Fpllint | 1 | 3 | MHz | 31 | ||
| VCO output frequency before post-divide (Fpllvco) | Fpllvco | 22.5 | 104 | MHz | 31 | ||
| VCO output post-divider range (Divvco) | Divvco | 1 | 8 | PLL output frequency is Fpplvco/Divvco | 31 | ||
| Lock time at startup (Plllocktime) | Plllocktime | 250 | µs | 31 | |||
| Period jitter for VCO ≥ 67 MHz (Jperiod_1) | Jperiod_1 | 150 | ps | Guaranteed by design | 31 | ||
| Period jitter for VCO ≤ 67 MHz (Jperiod_2) | Jperiod_2 | 200 | ps | Guaranteed by design | 31 | ||
| System clock source switching time (TCLKSWITCH) | TCLKSWITCH | 3 | 4 | Periods | 31 | ||
| Max delay added by Smart I/O in bypass mode (PRG_BYPASS) | PRG_BYPASS | 1.6 | ns | 32 | |||
| Block current consumption (IDD_CAN) | IDD_CAN | 200 | µA | 32 | |||
| Operating ambient temperature (TA), industrial grade | TA | -40 | 85 | °C | Industrial (I) suffix per ordering table; family Table 41 lists 105 °C | 33 | |
| Operating junction temperature (TJ) | TJ | -40 | 125 | °C | 36 | ||
| Package θJA, 64-pin TQFP (0.5-mm pitch) | TJA | 46 | °C/Watt | 64-pin TQFP (0.5-mm pitch) | 36 | ||
| Package θJC, 64-pin TQFP (0.5-mm pitch) | TJC | 10 | °C/Watt | 64-pin TQFP (0.5-mm pitch) | 36 |
CAD (KiCad official)
- Symbol:
CY8C4146AZI-S445 - Footprint:
Package_QFP:TQFP-64_10x10mm_P0.5mm - 3D model: TQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
cy8c4146azi-s445-etched.step/cy8c4146azi-s445-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy8c4146azi-s445.step/cy8c4146azi-s445.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Cypress Semicon datasheet (44 pp, sha256
dbd64085f5f9728a, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).