component

CY8C4146AZI-S423

Public Made by Adom

by adom

Infineon Cypress Semicon Microcontrollers (MCU/MPU/SOC), TQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscy8c4146azi-s423factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

3D Model

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

Datasheet

Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

CY8C4146AZI-S423

Infineon Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · TQFP-48(7x7)

CY8C4146AZI-S423 from Infineon Cypress Semicon, in a TQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7/VREF bidirectional GPIO port 1 bit 7 (all port pins support GPIO), also usable as SAR external reference via sar_ext_vref0/sar_ext_vref1 and alternate functions ctb0_oa1+ and scb[2].spi_clk per Table 2.
2 P2.0 bidirectional GPIO port 2 bit 0, also SAR mux input sarmux[0], SmartIO[0].io[0], csd.comp, and scb[1] I2C/SPI alternate functions per Table 2.
3 P2.1 bidirectional GPIO port 2 bit 1, also SAR mux input sarmux[1], SmartIO[0].io[1], tcpwm.tr_in[5], and scb[1] I2C/SPI alternate functions per Table 2.
4 P2.2 bidirectional GPIO port 2 bit 2, also SAR mux input sarmux[2], SmartIO[0].io[2], and scb[1].spi_clk:2 per Table 2.
5 P2.3 bidirectional GPIO port 2 bit 3, also SAR mux input sarmux[3], SmartIO[0].io[3], and scb[1].spi_select0:2 per Table 2.
6 P2.4 bidirectional GPIO port 2 bit 4, also SAR mux input sarmux[4], SmartIO[0].io[4], tcpwm.line[0]:1, and scb[1].spi_select1:1 per Table 2.
7 P2.5 bidirectional GPIO port 2 bit 5, also SAR mux input sarmux[5], SmartIO[0].io[5], tcpwm.line_compl[0]:1, and scb[1].spi_select2:1 per Table 2.
8 P2.6 bidirectional GPIO port 2 bit 6, also SAR mux input sarmux[6], SmartIO[0].io[6], tcpwm.line[1]:1, and scb[1].spi_select3:1 per Table 2.
9 P2.7 bidirectional GPIO port 2 bit 7, also SAR mux input sarmux[7], SmartIO[0].io[7], lpcomp.comp[0]:1, and scb[2].spi_mosi per Table 2.
10 VSSD power_in Ground pin for the digital section.
11 NC unconnected No connect on the 48-pin TQFP package.
12 P3.0 bidirectional GPIO port 3 bit 0, also SmartIO[1].io[0], tcpwm.line[0]:0, and scb[1] UART/I2C/SPI alternate functions per Table 2.
13 P3.1 bidirectional GPIO port 3 bit 1, also SmartIO[1].io[1], tcpwm.line_compl[0]:0, and scb[1] UART/I2C/SPI alternate functions per Table 2.
14 P3.2 bidirectional GPIO port 3 bit 2, also SmartIO[1].io[2], tcpwm.line[1]:0, cpuss.swd_data, and scb[1] UART/SPI alternate functions per Table 2.
15 NC unconnected No connect on the 48-pin TQFP package.
16 P3.3 bidirectional GPIO port 3 bit 3, also SmartIO[1].io[3], tcpwm.line_compl[1]:0, cpuss.swd_clk, and scb[1] UART/SPI alternate functions per Table 2.
17 P3.4 bidirectional GPIO port 3 bit 4, also SmartIO[1].io[4], tcpwm.line[2]:0, tcpwm.tr_in[6], and scb[1].spi_select1:0 per Table 2.
18 P3.5 bidirectional GPIO port 3 bit 5, also SmartIO[1].io[5], tcpwm.line_compl[2]:0, and scb[1].spi_select2:0 per Table 2.
19 P3.6 bidirectional GPIO port 3 bit 6, also SmartIO[1].io[6], tcpwm.line[3]:0, and scb[1].spi_select3:0 per Table 2.
20 P3.7 bidirectional GPIO port 3 bit 7, also SmartIO[1].io[7], tcpwm.line_compl[3]:0, lpcomp.comp[1]:1, and scb[2].spi_miso per Table 2.
21 VDDD power_in Power supply for the digital section.
22 P4.0 bidirectional GPIO port 4 bit 0, also csd.vref_ext, scb[0].uart_rx:0, scb[0].i2c_scl:1, and scb[0].spi_mosi:0 per Table 2.
23 P4.1 bidirectional GPIO port 4 bit 1, also csd.cshieldpads, scb[0].uart_tx:0, scb[0].i2c_sda:1, and scb[0].spi_miso:0 per Table 2.
24 P4.2 bidirectional GPIO port 4 bit 2, also csd.cmodpad, scb[0].uart_cts:0, lpcomp.comp[0]:0, and scb[0].spi_clk:0 per Table 2.
25 P4.3 bidirectional GPIO port 4 bit 3, also csd.csh_tank, scb[0].uart_rts:0, lpcomp.comp[1]:0, and scb[0].spi_select0:0 per Table 2.
26 NC unconnected No connect on the 48-pin TQFP package.
27 NC unconnected No connect on the 48-pin TQFP package.
28 P0.0 bidirectional GPIO port 0 bit 0, also lpcomp.in_p[0], tcpwm.tr_in[0], scb[2].i2c_scl:0, and scb[0].spi_select1:0 per Table 2.
29 P0.1 bidirectional GPIO port 0 bit 1, also lpcomp.in_n[0], tcpwm.tr_in[1], scb[2].i2c_sda:0, and scb[0].spi_select2:0 per Table 2.
30 P0.2 bidirectional GPIO port 0 bit 2, also lpcomp.in_p[1] and scb[0].spi_select3:0 per Table 2.
31 P0.3 bidirectional GPIO port 0 bit 3, also lpcomp.in_n[1] and scb[2].spi_select0 per Table 2.
32 P0.4 bidirectional GPIO port 0 bit 4, also wco.wco_in, scb[1].uart_rx:0, scb[2].uart_rx:0, scb[1].i2c_scl:0, and scb[1].spi_mosi:1 per Table 2.
33 P0.5 bidirectional GPIO port 0 bit 5, also wco.wco_out, scb[1].uart_tx:0, scb[2].uart_tx:0, scb[1].i2c_sda:0, and scb[1].spi_miso:1 per Table 2.
34 P0.6 bidirectional GPIO port 0 bit 6, also srss.ext_clk, scb[1].uart_cts:0, scb[2].uart_tx:1, and scb[1].spi_clk:1 per Table 2.
35 P0.7 bidirectional GPIO port 0 bit 7, also tcpwm.line[0]:2, scb[1].uart_rts:0, and scb[1].spi_select0:1 per Table 2.
36 XRES input External reset pin for the device; the provided text gives only its name and pin location in Table 1, with no electrical limits stated.
37 VCCD power_out Regulated digital supply output of the internal 1.8 V regulator (1.8 V ±5%), which must be bypassed to ground with 0.1 µF X5R or better and must not be connected to anything else in Mode 1.
38 VSSD power_in Ground pin for the digital section.
39 VDDD power_in Power supply for the digital section, supplied in the 1.8 V to 5.5 V range (Mode 1) or 1.71 V to 1.89 V (Mode 2).
40 VDDA power_in Power supply for the analog section, which runs directly from the VDD input since there is no analog regulator.
41 VSSA power_in Ground pin for the analog section.
42 P1.0 bidirectional GPIO port 1 bit 0, also ctb0_oa0+, tcpwm.line[2]:1, scb[0].uart_rx:1, scb[0].i2c_scl:0, and scb[0].spi_mosi:1 per Table 2.
43 P1.1 bidirectional GPIO port 1 bit 1, also ctb0_oa0-, tcpwm.line_compl[2]:1, scb[0].uart_tx:1, scb[0].i2c_sda:0, and scb[0].spi_miso:1 per Table 2.
44 P1.2 bidirectional GPIO port 1 bit 2, also ctb0_oa0_out, tcpwm.line[3]:1, scb[0].uart_cts:1, tcpwm.tr_in[2], scb[2].i2c_scl:1, and scb[0].spi_clk:1 per Table 2.
45 P1.3 bidirectional GPIO port 1 bit 3, also ctb0_oa1_out, tcpwm.line_compl[3]:1, scb[0].uart_rts:1, tcpwm.tr_in[3], scb[2].i2c_sda:1, and scb[0].spi_select0:1 per Table 2.
46 P1.4 bidirectional GPIO port 1 bit 4, also ctb0_oa1- and scb[0].spi_select1:1 per Table 2.
47 P1.5 bidirectional GPIO port 1 bit 5, also ctb0_oa1+ and scb[0].spi_select2:1 per Table 2.
48 P1.6 bidirectional GPIO port 1 bit 6, also ctb0_oa0+ and scb[0].spi_select3:1 per Table 2.

Key specifications

Parameter Value
Manufacturer Infineon Cypress Semicon
Package TQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 16
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 16
GPIO voltage VGPIO_ABS -0.5 V 16
Maximum current per GPIO IGPIO_ABS -25 25 mA 16
GPIO injection current IGPIO_injection -0.5 0.5 mA Current injected per pin 16
Electrostatic discharge human body model ESD_HBM 2200 V 16
Electrostatic discharge charged device model ESD_CDM 500 V 16
Pin current for latch-up LU -140 140 mA 16
Power supply input voltage (internally regulated supply) VDD 1.8 5.5 V Internally regulated supply 16
Power supply input voltage (VCCD = VDDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 16
Execute from flash; CPU at 6 MHz IDD5 1.8 2.7 mA Active Mode, VDD = 1.8 V to 5.5 V; max at 85 °C and 5.5 V 16
Execute from flash; CPU at 24 MHz IDD8 3 4.75 mA Active Mode, VDD = 1.8 V to 5.5 V; max at 85 °C and 5.5 V 16
Execute from flash; CPU at 48 MHz IDD11 5.4 6.85 mA Active Mode, VDD = 1.8 V to 5.5 V; max at 85 °C and 5.5 V 16
I2C wakeup, WDT, and Comparators on, 6 MHz IDD17 1.7 2.2 mA Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on); max at 85 °C and 5.5 V 16
I2C wakeup, WDT, and Comparators on, 12 MHz IDD20 2.2 2.5 mA Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on); max at 85 °C and 5.5 V 16
I2C wakeup, WDT, and Comparators on, 6 MHz IDD23 0.7 0.9 mA Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed); max at 85 °C and 5.5 V 17
I2C wakeup, WDT, and Comparators on, 12 MHz IDD23A 1 1.2 mA Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed); max at 85 °C and 5.5 V 17
I2C wakeup and WDT on IDD26 2.5 60 µA Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on); max at 3.6 V and 85 °C 17
I2C wakeup and WDT on IDD32 2.5 65 µA Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed); max at 1.89 V and 85 °C 17
Supply current while XRES asserted IDD_XR 2 5 mA XRES Current 17
CPU frequency FCPU 48 MHz 1.71 ≤ VDD ≤ 5.5 17
SWD clock frequency F_SWDCLK1 14 MHz 3.3 V ≤ VDD ≤ 5.5 V; SWDCLK ≤ 1/3 CPU clock frequency 30
SWD clock frequency F_SWDCLK2 7 MHz 1.71 V ≤ VDD ≤ 3.3 V; SWDCLK ≤ 1/3 CPU clock frequency 30
SWDIO output hold time from SWDCLK T_SWDO_HOLD 1 ns T = 1/f SWDCLK 30
BOD trip voltage in active and sleep modes VFALLPPOR 1.48 1.62 V 30
BOD trip voltage in Deep Sleep VFALLDPSLP 1.11 1.5 V 30
IMO operating current at 48 MHz IIMO1 250 µA Guaranteed by design 30
IMO operating current at 24 MHz IIMO2 180 µA Guaranteed by design 30
Frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % Trimmed 30
IMO startup time TSTARTIMO 7 µs 30
ILO operating current IILO1 0.3 1.05 µA Guaranteed by design 30
ILO startup time TSTARTILO1 2 ms Guaranteed by characterization 31
ILO duty cycle TILODUTY 40 50 60 % Guaranteed by characterization 31
ILO frequency range FILOTRIM1 20 40 80 kHz 31
Frequency tolerance FTOL 50 250 ppm With 20-ppm crystal 31
Drive level PD 1 µW 31
Startup time TSTART 500 ms 31
Crystal load capacitance CL 6 12.5 pF 31
Operating current (high power mode) IWCO1 8 µA 31
Operating current (low power mode) IWCO2 1 µA 31
External clock input frequency ExtClkFreq 0 48 MHz 31
Duty cycle ExtClkDuty 45 55 % Measured at VDD/2 31
System clock source switching time TCLKSWITCH 3 4 Periods 31
Max delay added by Smart I/O in bypass mode PRG_BYPASS 1.6 ns 31
Operating ambient temperature TA -40 25 105 °C General device-level range as printed in Table 40; this MPN's ordering range is -40 to 85 °C 35
Operating junction temperature TJ -40 125 °C 35
Package θJA, 48-pin TQFP TJA 74.8 °C/Watt 35
Package θJC, 48-pin TQFP TJC 35.7 °C/Watt 35
Maximum peak solder reflow temperature 260 °C All packages 35
Maximum time at peak solder reflow temperature 30 s All packages 35

CAD (KiCad official)

  • Symbol: CY8C4146AZI-S423
  • Footprint: Package_QFP:TQFP-48_7x7mm_P0.5mm
  • 3D model: TQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: cy8c4146azi-s423-etched.step / cy8c4146azi-s423-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4146azi-s423.step / cy8c4146azi-s423.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon Cypress Semicon datasheet (44 pp, sha256 ffa6972966622b0d, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF