component

CY8C4146AXI-S443

Public Made by Adom

by adom

Cypress Semicon Pre-ordered Products, LQFP-44. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentelectronic tools-instruments-consumablescy8c4146axi-s443factory-2.0.0extractor-text

Verified CY8C4146AXI-S443

by Ray · last 9 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

9 Nov 2026RayPublished by the parts factory: tier lcsc, 44 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: CY8C4146AXI-S443 · LQFP-44 · 44 pins
  • ✓copper: 44 copper pads, none touching another net
  • ✓datasheet: all 44 pin names found in the 44-page datasheet
  • ✓distributor: lcsc C2948702, digikey 448-CY8C4146AXI-S443-ND, mouser 727-CY8C4146AXI-S443
  • ✓family: LQFP-44_10x10mm_P0.8mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-fwbs3ytg/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 44 pins = 44 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 44 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ cy8c4146axi-s443.kicad_sym✓ cy8c4146axi-s443.kicad_mod✓ cy8c4146axi-s443.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray
viewers cy8c4146axi-s443: viewers · Ray
cy8c4146axi-s443-etched.glb Publish 0.1.0 · Ray
cy8c4146axi-s443-etched.step cy8c4146axi-s443: factory component page (tier=lcsc) · Ray
cy8c4146axi-s443-hero.glb cy8c4146axi-s443: hero GLB from the etched model (keeps the MPN mark) · Ray
cy8c4146axi-s443-hero.overlay.json Publish 0.1.0 · Ray
cy8c4146axi-s443.glb Publish 0.1.0 · Ray
cy8c4146axi-s443.kicad_mod Publish 0.1.0 · Ray
cy8c4146axi-s443.kicad_sym Publish 0.1.0 · Ray
cy8c4146axi-s443.lbr Publish 0.1.0 · Ray
cy8c4146axi-s443.step Publish 0.1.0 · Ray
package.json Publish 0.1.0 · Ray
page.json Set visibility: public · Ray
README.md Publish 0.1.0 · Ray
verification.json Verified: Published by the parts factory: tier lcsc, 44 pins · Ray

CY8C4146AXI-S443

Cypress Semicon · Pre-ordered Products · LQFP-44

CY8C4146AXI-S443 from Cypress Semicon, in a LQFP-44. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VSSD power_in Ground pin for the digital section.
2 P2.0 bidirectional GPIO port 2 bit 0 with analog sarmux[0], SmartIo[0].io[0], csd.comp, TCPWM line[4], and SCB1 I2C SCL/SPI MOSI functions.
3 P2.1 bidirectional GPIO port 2 bit 1 with analog sarmux[1], SmartIo[0].io[1], TCPWM line_compl[4], and SCB1 I2C SDA/SPI MISO functions.
4 P2.2 bidirectional GPIO port 2 bit 2 with analog sarmux[2], SmartIo[0].io[2], TCPWM line[5], and SCB1 SPI clock functions.
5 P2.3 bidirectional GPIO port 2 bit 3 with analog sarmux[3], SmartIo[0].io[3], TCPWM line_compl[5], and SCB1 SPI select0 functions.
6 P2.4 bidirectional GPIO port 2 bit 4 with analog sarmux[4], SmartIo[0].io[4], TCPWM line[0], and SCB3 UART RX / SCB1 SPI select1 functions.
7 P2.5 bidirectional GPIO port 2 bit 5 with analog sarmux[5], SmartIo[0].io[5], TCPWM line_compl[0], and SCB3 UART TX / SCB1 SPI select2 functions.
8 P2.6 bidirectional GPIO port 2 bit 6 with analog sarmux[6], SmartIo[0].io[6], TCPWM line[1], and SCB3 UART CTS / SCB1 SPI select3 functions.
9 P2.7 bidirectional GPIO port 2 bit 7 with analog sarmux[7], SmartIo[0].io[7], TCPWM line_compl[1], lpcomp.comp[0], and SCB3 UART RTS / SCB2 SPI MOSI functions.
10 P6.0 bidirectional GPIO port 6 bit 0 with TCPWM line[4], SCB3 UART RX/I2C SCL/SPI MOSI, and CAN tx_enb_n functions.
11 P3.0 bidirectional GPIO port 3 bit 0 with SmartIo[1].io[0], TCPWM line[0], and SCB1 UART RX/I2C SCL/SPI MOSI functions.
12 P3.1 bidirectional GPIO port 3 bit 1 with SmartIo[1].io[1], TCPWM line_compl[0], and SCB1 UART TX/I2C SDA/SPI MISO functions.
13 P3.2 bidirectional GPIO port 3 bit 2 with SmartIo[1].io[2], TCPWM line[1], SCB1 UART CTS/SPI clock, and cpuss.swd_data (SWD data) functions.
14 P3.3 bidirectional GPIO port 3 bit 3 with SmartIo[1].io[3], TCPWM line_compl[1], SCB1 UART RTS/SPI select0, and cpuss.swd_clk (SWD clock) functions.
15 P3.4 bidirectional GPIO port 3 bit 4 with SmartIo[1].io[4], TCPWM line[2], tr_in[6], and SCB1 SPI select1 functions.
16 P3.5 bidirectional GPIO port 3 bit 5 with SmartIo[1].io[5], TCPWM line_compl[2], and SCB1 SPI select2 functions.
17 P3.6 bidirectional GPIO port 3 bit 6 with SmartIo[1].io[6], TCPWM line[3], and SCB1 SPI select3 functions.
18 P3.7 bidirectional GPIO port 3 bit 7 with SmartIo[1].io[7], TCPWM line_compl[3], lpcomp.comp[1], and SCB2 SPI MISO functions.
19 VDDD power_in Power supply for the digital section.
20 P4.0 bidirectional GPIO port 4 bit 0 with csd.vref_ext, SCB0 UART RX/I2C SCL/SPI MOSI, and CAN rx functions.
21 P4.1 bidirectional GPIO port 4 bit 1 with csd.cshield, SCB0 UART TX/I2C SDA/SPI MISO, and CAN tx functions.
22 P4.2 bidirectional GPIO port 4 bit 2 with csd.cmod, SCB0 UART CTS/SPI clock, CAN tx_enb_n, and lpcomp.comp[0] functions.
23 P4.3 bidirectional GPIO port 4 bit 3 with csd.csh_tank, SCB0 UART RTS/SPI select0, and lpcomp.comp[1] functions.
24 P0.0 bidirectional GPIO port 0 bit 0 with low-power comparator input lpcomp.in_p[0], TCPWM trigger, and SCB2 UART CTS/I2C SCL functions.
25 P0.1 bidirectional GPIO port 0 bit 1 with low-power comparator input lpcomp.in_n[0], TCPWM trigger, and SCB2 UART RTS/I2C SDA functions.
26 P0.2 bidirectional GPIO port 0 bit 2 with low-power comparator input lpcomp.in_p[1] and SCB0 SPI select3 function.
27 P0.3 bidirectional GPIO port 0 bit 3 with low-power comparator input lpcomp.in_n[1] and SCB2 SPI select0 function.
28 P0.4 bidirectional GPIO port 0 bit 4 with watch crystal input wco.wco_in and SCB1/SCB2 UART RX/I2C SCL functions.
29 P0.5 bidirectional GPIO port 0 bit 5 with watch crystal output wco.wco_out and SCB1/SCB2 UART TX/I2C SDA functions.
30 P0.6 bidirectional GPIO port 0 bit 6 with external crystal input exco.eco_in, srss.ext_clk, and SCB1 UART CTS/SPI clock functions.
31 P0.7 bidirectional GPIO port 0 bit 7 with external crystal output exco.eco_out, TCPWM line[0], and SCB1 UART RTS/SPI select0 functions.
32 XRES input External reset input pin.
33 VCCD power_out Regulated digital supply (1.8 V ±5%).
34 VDDD power_in Power supply for the digital section.
35 VDDA power_in Power supply for the analog section.
36 VSSA power_in Ground pin for the analog section.
37 P1.0 bidirectional GPIO port 1 bit 0 with opamp ctb0_oa0+, SmartIo[2].io[0], TCPWM line[2], and SCB0 UART RX/I2C SCL/SPI MOSI functions.
38 P1.1 bidirectional GPIO port 1 bit 1 with opamp ctb0_oa0-, SmartIo[2].io[1], TCPWM line_compl[2], and SCB0 UART TX/I2C SDA/SPI MISO functions.
39 P1.2 bidirectional GPIO port 1 bit 2 with opamp output ctb0_oa0_out, SmartIo[2].io[2], TCPWM line[3], and SCB0 UART CTS/SPI clock functions.
40 P1.3 bidirectional GPIO port 1 bit 3 with opamp output ctb0_oa1_out, SmartIo[2].io[3], TCPWM line_compl[3], and SCB0 UART RTS/SPI select0 functions.
41 P1.4 bidirectional GPIO port 1 bit 4 with opamp ctb0_oa1-, SmartIo[2].io[4], TCPWM line[6], and SCB3 I2C SCL functions.
42 P1.5 bidirectional GPIO port 1 bit 5 with opamp ctb0_oa1+, SmartIo[2].io[5], TCPWM line_compl[6], and SCB3 I2C SDA functions.
43 P1.6 bidirectional GPIO port 1 bit 6 with opamp ctb0_oa0+, SmartIo[2].io[6], TCPWM line[7], and SCB0 SPI select3 functions.
44 P1.7 bidirectional GPIO port 1 bit 7 with opamp ctb0_oa1+, sar_ext_vref0/1, SmartIo[2].io[7], TCPWM line_compl[7], and SCB2 SPI clock functions.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package LQFP-44
Category Electronic Tools/Instruments/Consumables
Pins 44

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 15
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 15
GPIO voltage VGPIO_ABS -0.5 V max printed as VDD+0.5 15
Maximum current per GPIO IGPIO_ABS -25 25 mA 15
GPIO injection current IGPIO_injection -0.5 0.5 mA Current injected per pin 15
Electrostatic discharge human body model ESD_HBM 2200 V 15
Electrostatic discharge charged device model ESD_CDM 500 V 15
Pin current for latch-up LU -140 140 mA 15
Power supply input voltage VDD 1.8 5.5 V Internally regulated supply 15
Power supply input voltage (VCCD = VDDD = VDDA) VDD 1.71 1.89 V Internally unregulated supply 15
Active mode supply current, execute from flash, CPU at 6 MHz IDD5 1.8 2.4 mA Execute from flash; CPU at 6 MHz 15
Active mode supply current, execute from flash, CPU at 24 MHz IDD8 3 4.6 mA Execute from flash; CPU at 24 MHz 15
Active mode supply current, execute from flash, CPU at 48 MHz IDD11 5.4 7.1 mA Execute from flash; CPU at 48 MHz 15
Sleep mode supply current, regulator on IDD17 1.1 1.8 mA Sleep, VDDD = 1.8 V to 5.5 V; I2C wakeup, WDT and comparators on; 6 MHz 15
Sleep mode supply current, regulator on IDD20 1.5 2.1 mA Sleep, VDDD = 1.8 V to 5.5 V; I2C wakeup, WDT and comparators on; 12 MHz 15
Sleep mode supply current, regulator bypassed IDD23 1.1 1.8 mA Sleep, VDDD = 1.71 V to 1.89 V; I2C wakeup, WDT and comparators on; 6 MHz 16
Sleep mode supply current, regulator bypassed IDD23A 1.5 2.1 mA Sleep, VDDD = 1.71 V to 1.89 V; I2C wakeup, WDT and comparators on; 12 MHz 16
Deep Sleep supply current, VDD 1.8 V to 3.6 V IDD25 2.5 40 µA Deep Sleep, VDD = 1.8 V to 3.6 V, regulator on; I2C wakeup and WDT on; T = -40 °C to 60 °C 16
Deep Sleep supply current, VDD 1.8 V to 3.6 V IDD26 2.5 125 µA Deep Sleep, VDD = 1.8 V to 3.6 V, regulator on; I2C wakeup and WDT on; max at 3.6 V and 85 °C 16
Deep Sleep supply current, VDD 3.6 V to 5.5 V IDD28 2.5 40 µA Deep Sleep, VDD = 3.6 V to 5.5 V, regulator on; I2C wakeup and WDT on; T = -40 °C to 60 °C 16
Deep Sleep supply current, VDD 3.6 V to 5.5 V IDD29 2.5 125 µA Deep Sleep, VDD 3.6 V to 5.5 V, regulator on; I2C wakeup and WDT on; max at 5.5 V and 85 °C 16
Deep Sleep supply current, regulator bypassed IDD31 2.5 60 µA Deep Sleep, VDD = VCCD = 1.71 V to 1.89 V, regulator bypassed; I2C wakeup and WDT on; T = -40 °C to 60 °C 16
Deep Sleep supply current, regulator bypassed IDD32 2.5 180 µA Deep Sleep, VDD = VCCD = 1.71 V to 1.89 V, regulator bypassed; I2C wakeup and WDT on; max at 1.89 V and 85 °C 16
Supply current while XRES asserted IDD_XR 2 5 mA 16
CPU frequency FCPU 48 MHz DC to max; 1.71 V ≤ VDD ≤ 5.5 V 15
Wakeup from Sleep mode TSLEEP 0 µs 15
Wakeup from Deep Sleep mode TDEEPSLEEP 35 µs 15
SWD clock frequency F_SWDCLK1 14 MHz 3.3 V ≤ VDD ≤ 5.5 V; SWDCLK ≤ 1/3 CPU clock frequency 30
SWD clock frequency F_SWDCLK2 7 MHz 1.71 V ≤ VDD ≤ 3.3 V; SWDCLK ≤ 1/3 CPU clock frequency 30
IMO operating current at 48 MHz IIMO1 250 µA 30
IMO operating current at 24 MHz IIMO2 180 µA 30
Frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % Trimmed 30
IMO startup time TSTARTIMO 7 µs 30
ILO startup time TSTARTILO1 2 ms 30
ILO duty cycle TILODUTY 40 50 60 % 30
ILO frequency range FILOTRIM1 20 40 80 kHz 30
Crystal frequency FWCO 32.768 kHz 31
Frequency tolerance FTOL 50 250 ppm With 20-ppm crystal 31
Crystal load capacitance CL 6 12.5 pF 31
Drive level PD 1 µW 31
Startup time TSTART 500 ms 31
Operating current (high power mode) IWCO1 8 µA 31
External clock input frequency ExtClkFreq 0 48 MHz 31
Duty cycle ExtClkDuty 45 55 % Measured at VDD/2 31
External clock input frequency IECO1 1.5 mA Printed row label; see review_required 31
Crystal frequency range FECO 4 33 MHz 31
PLL current at 48 MHz output IDD_PLL_48 530 610 µA In = 3 MHz, Out = 48 MHz 31
PLL current at 24 MHz output IDD_PLL_24 300 405 µA In = 3 MHz, Out = 24 MHz 31
PLL input frequency Fpllin 1 48 MHz 31
PLL intermediate frequency; prescaler out Fpllint 1 3 MHz 31
VCO output frequency before post-divide Fpllvco 22.5 104 MHz 31
VCO output post-divider range Divvco 1 8 PLL output frequency is Fpllvco/Divvco 31
Lock time at startup Plllocktime 250 µs 31
Period jitter for VCO ≥ 67 MHz Jperiod_1 150 ps Guaranteed by design 31
Period jitter for VCO ≤ 67 MHz Jperiod_2 200 ps Guaranteed by design 31
System clock source switching time TCLKSWITCH 3 4 Periods 31
Max delay added by Smart I/O in bypass mode PRG_BYPASS 1.6 ns 32
CAN block current consumption IDD_CAN 200 µA 32
CAN bit rate CAN_bits 1 Mbps Min 8-MHz clock 32
Digital core output voltage (for core logic) VCCD 1.8 V 15
External regulator voltage bypass CEFC 0.1 µF X5R ceramic or better 15
Power supply bypass capacitor CEXC 1 µF X5R ceramic or better 15
Operating ambient temperature TA -40 25 105 °C Package thermal characteristics table; XI grade is -40 to 85 °C per ordering table 36
Operating junction temperature TJ -40 125 °C 36
Package θJA, 44-pin TQFP TJA 55.6 °C/Watt 44-pin TQFP 36
Package θJC, 44-pin TQFP TJC 14.4 °C/Watt 44-pin TQFP 36

CAD (KiCad official)

  • Symbol: CY8C4146AXI-S443
  • Footprint: Package_QFP:LQFP-44_10x10mm_P0.8mm
  • 3D model: LQFP-44 (KiCad packages3D, STEP)
  • 3D model files: cy8c4146axi-s443-etched.step / cy8c4146axi-s443-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4146axi-s443.step / cy8c4146axi-s443.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (44 pp, sha256 dbd64085f5f9728a, retrieved 2026-11-09, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF