component
CY8C4125PVI-482T
Public Made by Adomby adom
Cypress Semicon CYPRESS, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.1.0
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{
"slug": "cy8c4125pvi-482t",
"version": "0.1.0",
"type": "component",
"description": "Cypress Semicon CYPRESS, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"embedded processors & controllers",
"cy8c4125pvi-482t",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"cy8c4125pvi-482t.kicad_sym",
"cy8c4125pvi-482t.kicad_mod",
"cy8c4125pvi-482t.glb",
"cy8c4125pvi-482t.step",
"cy8c4125pvi-482t.lbr",
"docs/hero.png",
"docs/cy8c4125pvi-482t-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"cy8c4125pvi-482t-hero.glb",
"cy8c4125pvi-482t-hero.overlay.json",
"cy8c4125pvi-482t-etched.glb"
],
"component": {
"mpn": "CY8C4125PVI-482T",
"manufacturer": "Cypress Semicon",
"package": "SSOP-28-208mil",
"pin_count": 28,
"category": "Embedded Processors & Controllers",
"subcategory": "CYPRESS",
"datasheet": "https://www.infineon.com/dgdl/Infineon-PSoC_4_PSoC_4100_Family-DataSheet-v12_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ec86cc240d7&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files",
"parts": {
"symbol": "cy8c4125pvi-482t.kicad_sym",
"footprint": "cy8c4125pvi-482t.kicad_mod",
"model_3d": "cy8c4125pvi-482t-hero.glb",
"model_3d_plain": "cy8c4125pvi-482t-etched.glb",
"model_3d_step": "cy8c4125pvi-482t-etched.step",
"model_3d_step_plain": "cy8c4125pvi-482t.step",
"lbr": "cy8c4125pvi-482t.lbr"
},
"distributor_links": {
"lcsc": "C2840301",
"digikey": "448-CY8C4125PVI-482TTR-ND",
"mouser": "727-CY8C4125PVI-482T"
},
"distributor_check": {
"checked_at": "2026-10-31T18:33:21Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "448-CY8C4125PVI-482TTR-ND",
"status": "found"
},
"mouser": {
"pn": "727-CY8C4125PVI-482T",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "P1.0",
"type": "bidirectional",
"description": "Port 1 Pin 0: GPIO, LCD, CSD, CTB (ctb.oa0.inp) and PWM (tcpwm2_p[1])."
},
{
"number": "2",
"name": "P1.1",
"type": "bidirectional",
"description": "Port 1 Pin 1: GPIO, LCD, CSD, CTB (ctb.oa0.inm) and PWM (tcpwm2_n[1])."
},
{
"number": "3",
"name": "P1.2",
"type": "bidirectional",
"description": "Port 1 Pin 2: GPIO, LCD, CSD, CTB (ctb.oa0.out) and PWM (tcpwm3_p[1])."
},
{
"number": "4",
"name": "P1.7/VREF",
"type": "bidirectional",
"description": "Port 1 Pin 7: GPIO, LCD, CSD, CTB (ctb.oa1.inp_alt) and optional external SAR reference input/bypass (ext_vref)."
},
{
"number": "5",
"name": "P2.2",
"type": "bidirectional",
"description": "Port 2 Pin 2: GPIO, LCD, CSD, SARMUX input (sarmux.2)."
},
{
"number": "6",
"name": "P2.3",
"type": "bidirectional",
"description": "Port 2 Pin 3: GPIO, LCD, CSD, SARMUX input (sarmux.3)."
},
{
"number": "7",
"name": "P2.4",
"type": "bidirectional",
"description": "Port 2 Pin 4: GPIO, LCD, CSD, SARMUX input (sarmux.4) and PWM (tcpwm0_p[1])."
},
{
"number": "8",
"name": "P2.5",
"type": "bidirectional",
"description": "Port 2 Pin 5: GPIO, LCD, CSD, SARMUX input (sarmux.5) and PWM (tcpwm0_n[1])."
},
{
"number": "9",
"name": "P2.6",
"type": "bidirectional",
"description": "Port 2 Pin 6: GPIO, LCD, CSD, SARMUX input (sarmux.6) and PWM (tcpwm1_p[1])."
},
{
"number": "10",
"name": "P2.7",
"type": "bidirectional",
"description": "Port 2 Pin 7: GPIO, LCD, CSD, SARMUX input (sarmux.7) and PWM (tcpwm1_n[1])."
},
{
"number": "11",
"name": "P3.0",
"type": "bidirectional",
"description": "Port 3 Pin 0: GPIO, LCD, CSD, PWM (tcpwm0_p[0]) and SCB1 UART RX / I2C SCL / SPI MOSI."
},
{
"number": "12",
"name": "P3.1",
"type": "bidirectional",
"description": "Port 3 Pin 1: GPIO, LCD, CSD, PWM (tcpwm0_n[0]) and SCB1 UART TX / I2C SDA / SPI MISO."
},
{
"number": "13",
"name": "P3.2",
"type": "bidirectional",
"description": "Port 3 Pin 2: GPIO, LCD, CSD, PWM (tcpwm1_p[0]), SCB1 SPI clock and SWD I/O (swd_io[0]), which is an SWD pin after boot (reset)."
},
{
"number": "14",
"name": "P3.3",
"type": "bidirectional",
"description": "Port 3 Pin 3: GPIO, LCD, CSD, PWM (tcpwm1_n[0]), SCB1 SPI SSEL0 and SWD clock (swd_clk[0]), which is an SWD pin after boot (reset)."
},
{
"number": "15",
"name": "P4.0",
"type": "bidirectional",
"description": "Port 4 Pin 0: GPIO, LCD, CSD and SCB0 UART RX / I2C SCL / SPI MOSI."
},
{
"number": "16",
"name": "P4.1",
"type": "bidirectional",
"description": "Port 4 Pin 1: GPIO, LCD, CSD and SCB0 UART TX / I2C SDA / SPI MISO."
},
{
"number": "17",
"name": "P4.2",
"type": "bidirectional",
"description": "Port 4 Pin 2: GPIO, LCD, CSD (csd_c_mod) and SCB0 SPI clock."
},
{
"number": "18",
"name": "P4.3",
"type": "bidirectional",
"description": "Port 4 Pin 3: GPIO, LCD, CSD (csd_c_sh_tank) and SCB0 SPI SSEL0."
},
{
"number": "19",
"name": "P0.0",
"type": "bidirectional",
"description": "Port 0 Pin 0: GPIO, LCD, CSD, comparator 1 positive input (comp1_inp) and SCB0 SPI SSEL1."
},
{
"number": "20",
"name": "P0.1",
"type": "bidirectional",
"description": "Port 0 Pin 1: GPIO, LCD, CSD, comparator 1 negative input (comp1_inn) and SCB0 SPI SSEL2."
},
{
"number": "21",
"name": "P0.2",
"type": "bidirectional",
"description": "Port 0 Pin 2: GPIO, LCD, CSD, comparator 2 positive input (comp2_inp) and SCB0 SPI SSEL3."
},
{
"number": "22",
"name": "P0.3",
"type": "bidirectional",
"description": "Port 0 Pin 3: GPIO, LCD, CSD and comparator 2 negative input (comp2_inn)."
},
{
"number": "23",
"name": "P0.6",
"type": "bidirectional",
"description": "Port 0 Pin 6: GPIO, LCD, CSD, external clock input (ext_clk) and SCB1 SPI clock."
},
{
"number": "24",
"name": "P0.7",
"type": "bidirectional",
"description": "Port 0 Pin 7: GPIO, LCD, CSD, wakeup and SCB1 SPI SSEL0."
},
{
"number": "25",
"name": "XRES",
"type": "input",
"description": "Chip reset, active low; has an internal pull-up resistor that is always enabled."
},
{
"number": "26",
"name": "VCCD",
"type": "power_out",
"description": "Regulated digital supply (1.8 V ±5%); connect to a 1 µF capacitor (1 µF to 1.6 µF, X5R or better) or to 1.8 V."
},
{
"number": "27",
"name": "VDD",
"type": "power_in",
"description": "Supply pin shared as VDDD and VDDA on this package, 1.8 - 5.5 V."
},
{
"number": "28",
"name": "VSS",
"type": "power_in",
"description": "Ground pin, shared as VSSA on this package."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-sonnet-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: The datasheet lists only the base part CY8C4125PVI-482 (28-SSOP) in the ordering table. The 'T' suff; The package outline is titled 28-pin (210-mil) SSOP, while the hint says 208 mil. This is probably t; The extracted SSOP pinout figure text shows '1 VSS', which conflicts with the pin table. The table g"
],
"pages_sent": 24,
"cost_usd": 0.3179,
"at": "2026-10-31T18:33:01"
},
"datasheet": {
"url": "https://www.infineon.com/dgdl/Infineon-PSoC_4_PSoC_4100_Family-DataSheet-v12_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ec86cc240d7&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-files",
"pages": 44,
"sha256": "96f5358c3c46932a",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 28,
"described": 28,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "cy8c4125pvi-482t.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
7.8,
10.2,
2.1
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "7aa76979ae41da44bded1ed74115012868f2f3f5a757faf32bb9df4f92c1e313",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cy8c4125pvi-482t-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
7.8,
10.2,
2.1
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "0d154baca604579ee39d63aa44c15321f13e80be54d7f31e46e94930ff07eecf",
"checked": "2026-10-31",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}