component

CY8C4125LTI-M445

Public Made by Adom

by adom

Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-68(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentsingle chip microcomputer-microcontrollercy8c4125lti-m445factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers cy8c4125lti-m445: viewers · Ray 5d ago
cy8c4125lti-m445-etched.glb Publish 0.1.0 · Ray 5d ago
cy8c4125lti-m445-etched.step cy8c4125lti-m445: factory component page (tier=lcsc) · Ray 5d ago
cy8c4125lti-m445-hero.glb cy8c4125lti-m445: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
cy8c4125lti-m445-hero.overlay.json Publish 0.1.0 · Ray 5d ago
cy8c4125lti-m445.glb Publish 0.1.0 · Ray 5d ago
cy8c4125lti-m445.kicad_mod Publish 0.1.0 · Ray 5d ago
cy8c4125lti-m445.kicad_sym Publish 0.1.0 · Ray 5d ago
cy8c4125lti-m445.lbr Publish 0.1.0 · Ray 5d ago
cy8c4125lti-m445.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago

CY8C4125LTI-M445

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-68(8x8)

CY8C4125LTI-M445 from Cypress Semicon, in a QFN-68(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P1.7/VREF bidirectional GPIO port 1 bit 7 (output driver powered from VDDA) with VREF function, ctb0.oa1.inp_alt and tcpwm.line_compl[7] alternate functions.
2 P2.0 bidirectional GPIO port 2 bit 0 (VDDA domain) with sarmux.0, tcpwm.line[4], scb[1].i2c_scl:1 and scb[1].spi_mosi:2 functions.
3 P2.1 bidirectional GPIO port 2 bit 1 (VDDA domain) with sarmux.1, tcpwm.line_compl[4], scb[1].i2c_sda:1 and scb[1].spi_miso:2 functions.
4 P2.2 bidirectional GPIO port 2 bit 2 (VDDA domain) with sarmux.2, tcpwm.line[5] and scb[1].spi_clk:2 functions.
5 P2.3 bidirectional GPIO port 2 bit 3 (VDDA domain) with sarmux.3, tcpwm.line_compl[5] and scb[1].spi_select0:2 functions.
6 P2.4 bidirectional GPIO port 2 bit 4 (VDDA domain) with sarmux.4, tcpwm.line[0] and scb[1].spi_select1:1 functions.
7 P2.5 bidirectional GPIO port 2 bit 5 (VDDA domain) with sarmux.5, tcpwm.line_compl[0] and scb[1].spi_select2:1 functions.
8 P2.6 bidirectional GPIO port 2 bit 6 (VDDA domain) with sarmux.6, tcpwm.line[1] and scb[1].spi_select3:1 functions.
9 P2.7 bidirectional GPIO port 2 bit 7 (VDDA domain) with sarmux.7, tcpwm.line_compl[1] and scb[3].spi_select0:1 functions.
10 VSSA power_in Analog ground pin; must be tied together with all other VSS pins.
11 VDDA power_in Analog VDD supply pin (1.71 to 5.5 V supply range), bypassed with 0.1 µF ceramic at the pin plus 1 to 10 µF bulk capacitor to VSSA.
12 P6.0 bidirectional Overvoltage-tolerant GPIO port 6 bit 0 (VDDIO domain) with tcpwm.line[4], scb[3].uart_rx:0, scb[3].i2c_scl:0 and scb[3].spi_mosi:0 functions.
13 P6.1 bidirectional Overvoltage-tolerant GPIO port 6 bit 1 (VDDIO domain) with tcpwm.line_compl[4], scb[3].uart_tx:0, scb[3].i2c_sda:0 and scb[3].spi_miso:0 functions.
14 P6.2 bidirectional Overvoltage-tolerant GPIO port 6 bit 2 (VDDIO domain) with tcpwm.line[5], scb[3].uart_cts:0 and scb[3].spi_clk:0 functions.
15 P6.3 bidirectional Overvoltage-tolerant GPIO port 6 bit 3 (VDDIO domain) with tcpwm.line_compl[5], scb[3].uart_rts:0 and scb[3].spi_select0:0 functions.
16 P6.4 bidirectional Overvoltage-tolerant GPIO port 6 bit 4 (VDDIO domain) with tcpwm.line[6] and scb[3].spi_select1:0 functions.
17 P6.5 bidirectional Overvoltage-tolerant GPIO port 6 bit 5 (VDDIO domain) with tcpwm.line_compl[6] and scb[3].spi_select2:0 functions.
18 VSSIO power_in Ground pin for the I/O domain; all VSS pins must be tied together.
19 P3.0 bidirectional GPIO port 3 bit 0 (VDDIO domain) with tcpwm.line[0], scb[1].uart_rx:1, scb[1].i2c_scl:2 and scb[1].spi_mosi:0 functions.
20 P3.1 bidirectional GPIO port 3 bit 1 (VDDIO domain) with tcpwm.line_compl[0], scb[1].uart_tx:1, scb[1].i2c_sda:2 and scb[1].spi_miso:0 functions.
21 P3.2 bidirectional GPIO port 3 bit 2 (VDDIO domain) with tcpwm.line[1], scb[1].uart_cts:1, swd_data and scb[1].spi_clk:0 functions.
22 P3.3 bidirectional GPIO port 3 bit 3 (VDDIO domain) with tcpwm.line_compl[1], scb[1].uart_rts:1, swd_clk and scb[1].spi_select0:0 functions.
23 P3.4 bidirectional GPIO port 3 bit 4 (VDDIO domain) with tcpwm.line[2] and scb[1].spi_select1:0 functions.
24 P3.5 bidirectional GPIO port 3 bit 5 (VDDIO domain) with tcpwm.line_compl[2] and scb[1].spi_select2:0 functions.
25 P3.6 bidirectional GPIO port 3 bit 6 (VDDIO domain) with tcpwm.line[3] and scb[1].spi_select3:0 functions.
26 P3.7 bidirectional GPIO port 3 bit 7 (VDDIO domain) with tcpwm.line_compl[3] function.
27 VDDIO power_in I/O pin power domain supply for ports 3, 4 and 6, bypassed with 0.1 µF ceramic at the pin plus 1 to 10 µF bulk capacitor.
28 P4.0 bidirectional GPIO port 4 bit 0 (VDDIO domain) with scb[0].uart_rx:0, scb[0].i2c_scl:1 and scb[0].spi_mosi:0 functions.
29 P4.1 bidirectional GPIO port 4 bit 1 (VDDIO domain) with scb[0].uart_tx:0, scb[0].i2c_sda:1 and scb[0].spi_miso:0 functions.
30 P4.2 bidirectional GPIO port 4 bit 2 (VDDIO domain) with csd[0].c_mod, scb[0].uart_cts:0, lpcomp.comp[0]:0 and scb[0].spi_clk:0 functions.
31 P4.3 bidirectional GPIO port 4 bit 3 (VDDIO domain) with csd[0].c_sh_tank, scb[0].uart_rts:0, lpcomp.comp[1]:0 and scb[0].spi_select0:0 functions.
32 P4.4 bidirectional GPIO port 4 bit 4 (VDDIO domain) with scb[0].spi_select1:2 function.
33 P4.5 bidirectional GPIO port 4 bit 5 (VDDIO domain) with scb[0].spi_select2:2 function.
34 P4.6 bidirectional GPIO port 4 bit 6 (VDDIO domain) with scb[0].spi_select3:2 function.
35 P4.7 bidirectional GPIO port 4 bit 7 (VDDIO domain) with no alternate function listed.
36 NC unconnected No-connect pin on the 68-pin QFN.
37 NC unconnected No-connect pin on the 68-pin QFN.
38 NC unconnected No-connect pin on the 68-pin QFN.
39 P7.0 bidirectional GPIO port 7 bit 0 (VDDD domain) with tcpwm.line[0], scb[3].uart_rx:1, scb[3].i2c_scl:1 and scb[3].spi_mosi:1 functions.
40 P7.1 bidirectional GPIO port 7 bit 1 (VDDD domain) with tcpwm.line_compl[0], scb[3].uart_tx:1, scb[3].i2c_sda:1 and scb[3].spi_miso:1 functions.
41 P7.2 bidirectional GPIO port 7 bit 2 (VDDD domain) with tcpwm.line[1], scb[3].uart_cts:1 and scb[3].spi_clk:1 functions.
42 P0.0 bidirectional GPIO port 0 bit 0 (VDDD domain) with lpcomp.in_p[0] analog input and scb[0].spi_select1:0 functions.
43 P0.1 bidirectional GPIO port 0 bit 1 (VDDD domain) with lpcomp.in_n[0] analog input and scb[0].spi_select2:0 functions.
44 P0.2 bidirectional GPIO port 0 bit 2 (VDDD domain) with lpcomp.in_p[1] analog input and scb[0].spi_select3:0 functions.
45 P0.3 bidirectional GPIO port 0 bit 3 (VDDD domain) with lpcomp.in_n[1] analog input function.
46 P0.4 bidirectional GPIO port 0 bit 4 (VDDD domain) with wco_in, scb[1].uart_rx:0, scb[1].i2c_scl:0 and scb[1].spi_mosi:1 functions.
47 P0.5 bidirectional GPIO port 0 bit 5 (VDDD domain) with wco_out, scb[1].uart_tx:0, scb[1].i2c_sda:0 and scb[1].spi_miso:1 functions.
48 P0.6 bidirectional GPIO port 0 bit 6 (VDDD domain) with ext_clk:0, scb[1].uart_cts:0 and scb[1].spi_clk:1 functions.
49 P0.7 bidirectional GPIO port 0 bit 7 (VDDD domain) with scb[1].uart_rts:0, wakeup and scb[1].spi_select0:1 functions.
50 XRES input External reset pin reserved to avoid complications with configuration and multiple pin functions during power-on or reconfiguration.
51 VCCD power_out Regulated digital supply (1.8 V ±5%) bypassed to ground with a 1 µF ceramic capacitor (1 to 1.6 µF, X5R or better).
52 VSSD power_in Digital ground pin; all VSS pins must be tied together.
53 VDDD power_in Digital supply for port 0 and 7 drivers and core regulator input (1.71 to 5.5 V), bypassed with 0.1 µF ceramic at the pin plus 1 to 10 µF bulk capacitor.
54 P5.0 bidirectional GPIO port 5 bit 0 (VDDA domain) with ctb1.oa0.inp, tcpwm.line[4], scb[2].uart_rx:0, scb[2].i2c_scl:0 and scb[2].spi_mosi:0 functions.
55 P5.1 bidirectional GPIO port 5 bit 1 (VDDA domain) with ctb1.oa0.inm, tcpwm.line_compl[4], scb[2].uart_tx:0, scb[2].i2c_sda:0 and scb[2].spi_miso:0 functions.
56 P5.2 bidirectional GPIO port 5 bit 2 (VDDA domain) with ctb1.oa0.out, tcpwm.line[5], scb[2].uart_cts:0, lpcomp.comp[0]:1 and scb[2].spi_clk:0 functions.
57 P5.3 bidirectional GPIO port 5 bit 3 (VDDA domain) with ctb1.oa1.out, tcpwm.line_compl[5], scb[2].uart_rts:0, lpcomp.comp[1]:1 and scb[2].spi_select0:0 functions.
58 P5.4 bidirectional GPIO port 5 bit 4 (VDDA domain) with ctb1.oa1.inm, tcpwm.line[6] and scb[2].spi_select1:0 functions.
59 P5.5 bidirectional GPIO port 5 bit 5 (VDDA domain) with ctb1.oa1.inp, tcpwm.line_compl[6] and scb[2].spi_select2:0 functions.
60 VDDA power_in Analog VDD supply pin (1.71 to 5.5 V supply range), bypassed with 0.1 µF ceramic at the pin plus 1 to 10 µF bulk capacitor to VSSA.
61 VSSA power_in Analog ground pin; must be tied together with all other VSS pins.
62 P1.0 bidirectional GPIO port 1 bit 0 (VDDA domain) with ctb0.oa0.inp, tcpwm.line[2], scb[0].uart_rx:1, scb[0].i2c_scl:0 and scb[0].spi_mosi:1 functions.
63 P1.1 bidirectional GPIO port 1 bit 1 (VDDA domain) with ctb0.oa0.inm, tcpwm.line_compl[2], scb[0].uart_tx:1, scb[0].i2c_sda:0 and scb[0].spi_miso:1 functions.
64 P1.2 bidirectional GPIO port 1 bit 2 (VDDA domain) with ctb0.oa0.out, tcpwm.line[3], scb[0].uart_cts:1 and scb[0].spi_clk:1 functions.
65 P1.3 bidirectional GPIO port 1 bit 3 (VDDA domain) with ctb0.oa1.out, tcpwm.line_compl[3], scb[0].uart_rts:1 and scb[0].spi_select0:1 functions.
66 P1.4 bidirectional GPIO port 1 bit 4 (VDDA domain) with ctb0.oa1.inm, tcpwm.line[6] and scb[0].spi_select1:1 functions.
67 P1.5 bidirectional GPIO port 1 bit 5 (VDDA domain) with ctb0.oa1.inp, tcpwm.line_compl[6] and scb[0].spi_select2:1 functions.
68 P1.6 bidirectional GPIO port 1 bit 6 (VDDA domain) with ctb0.oa0.inp_alt, tcpwm.line[7] and scb[0].spi_select3:1 functions.
69 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-68(8x8)
Category Single Chip Microcomputer/Microcontroller
Pins 69

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Analog or digital supply relative to VSS VDD_ABS -0.5 6 V Absolute maximum 24
Direct digital core voltage input relative to VSSD VCCD_ABS -0.5 1.95 V Absolute maximum 24
GPIO voltage; VDDD or VDDA VGPIO_ABS -0.5 5.5 V Absolute maximum; printed as VDD+0.5 24
Current per GPIO IGPIO_ABS -25 25 mA Absolute maximum 24
GPIO injection current per pin IGPIO_injection -0.5 0.5 mA Absolute maximum 24
ESD human body model ESD_HBM 2200 V 24
ESD charged device model ESD_CDM 500 V 24
Pin current for latch-up LU -140 140 mA 24
Power supply input voltage (VDDA = VDDD = VDD) VDD 1.8 5.5 V With regulator enabled 24
Power supply input voltage unregulated VDDD 1.71 1.8 1.89 V Internally unregulated supply 24
Output voltage (for core logic) VCCD 1.8 V 24
External regulator voltage bypass CEFC 1 1.3 1.6 µF X5R ceramic or better 25
Power supply decoupling capacitor CEXC 1 µF X5R ceramic or better 25
Active current, execute from flash, CPU at 6 MHz IDD1 2.2 2.8 mA VDD = 1.71 V to 5.5 V, -40°C to +105°C 25
Active current, execute from flash, CPU at 12 MHz IDD2 3.7 4.2 mA VDD = 1.71 V to 5.5 V, -40°C to +105°C 25
Active current, execute from flash, CPU at 24 MHz IDD3 6.7 7.2 mA VDD = 1.71 V to 5.5 V, -40°C to +105°C 25
Sleep current, I2C wakeup, WDT, comparators on, regulator off IDD16 1.75 2.1 mA VDD = 1.71 to 1.89, 6 MHz 25
Sleep current, I2C wakeup, WDT, comparators on IDD17 1.7 2.1 mA VDD = 1.8 to 5.5, 6 MHz 25
Sleep current, I2C wakeup, WDT, comparators on, regulator off IDD18 2.35 2.8 mA VDD = 1.71 to 1.89, 12 MHz 25
Sleep current, I2C wakeup, WDT, comparators on IDD19 2.25 2.8 mA VDD = 1.8 to 5.5, 12 MHz 25
Deep Sleep current, I2C wakeup and WDT on, regulator off IDD25 1.55 20 µA VDD = 1.71 to 1.89, -40°C to +60°C 25
Deep Sleep current, I2C wakeup and WDT on IDD26 1.35 15 µA VDD = 1.8 to 3.6, -40°C to +60°C 25
Deep Sleep current, I2C wakeup and WDT on IDD27 1.5 15 µA VDD = 3.6 to 5.5, -40°C to +60°C 25
Deep Sleep current, regulator off, +85°C IDD28 60 µA VDD = 1.71 to 1.89, +85°C 25
Deep Sleep current, +85°C IDD29 45 µA VDD = 1.8 to 3.6, +85°C 25
Deep Sleep current, +85°C IDD30 30 µA VDD = 3.6 to 5.5, +85°C 25
Deep Sleep current, regulator off, +105°C IDD28Q 135 µA VDD = 1.71 to 1.89, +105°C 25
Deep Sleep current, +105°C IDD29Q 180 µA VDD = 1.8 to 3.6, +105°C 25
Deep Sleep current, +105°C IDD30Q 140 µA VDD = 3.6 to 5.5, +105°C 25
Hibernate current, regulator off IDD34 150 3000 nA VDD = 1.71 to 1.89, -40°C to +60°C 25
Hibernate current IDD35 150 1000 nA VDD = 1.8 to 3.6, -40°C to +60°C 25
SWD clock frequency F_SWDCLK1 14 MHz 3.3 V ≤ VDD ≤ 5.5 V; SWDCLK ≤ 1/3 CPU clock frequency 44
SWD clock frequency F_SWDCLK2 7 MHz 1.71 V ≤ VDD ≤ 3.3 V; SWDCLK ≤ 1/3 CPU clock frequency 44
SWD output hold time T_SWDO_HOLD 1 ns T = 1/f SWDCLK 44
IMO operating current at 48 MHz IIMO1 1000 µA 44
IMO operating current at 24 MHz IIMO2 325 µA 44
IMO operating current at 12 MHz IIMO3 225 µA 44
IMO operating current at 6 MHz IIMO4 180 µA 44
IMO operating current at 3 MHz IIMO5 150 µA 44
IMO frequency variation from 3 to 48 MHz FIMOTOL1 -2 2 % ±3% if TA > 85 °C and IMO frequency < 24 MHz 44
IMO startup time TSTARTIMO 12 µs 44
ILO operating current at 32 kHz IILO1 0.3 1.05 µA 45
ILO leakage current IILOLEAK 2 15 nA 45
ILO startup time TSTARTILO1 2 ms 45
ILO duty cycle TILODUTY 40 50 60 % 45
ILO 32 kHz trimmed frequency FILOTRIM1 15 32 50 kHz Max ILO frequency is 70 kHz if TA > 85 °C 45
External clock input frequency ExtClkFreq 0 48 MHz 45
External clock duty cycle ExtClkDuty 45 55 % Measured at VDD/2 45
WCO crystal frequency FWCO 32.768 kHz 46
WCO frequency tolerance FTOL 50 250 ppm With 20-ppm crystal 46
WCO operating current (high power mode) IWCO1 8 uA 46
Trimmed internal reference to SAR VREFSAR -1 1 % Percentage of Vbg (1.024 V) 46
Package θJA (68-pin QFN) TJA 16.8 °C/Watt 49
Package θJC (68-pin QFN) TJC 2.9 °C/Watt 49
Operating ambient temperature TA -40 25 85 °C 49
Operating junction temperature TJ -40 100 °C 49

CAD (KiCad official)

  • Symbol: CY8C4125LTI-M445
  • Footprint: Package_DFN_QFN:QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm
  • 3D model: QFN-68(8x8) (KiCad packages3D, STEP)
  • 3D model files: cy8c4125lti-m445-etched.step / cy8c4125lti-m445-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4125lti-m445.step / cy8c4125lti-m445.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (61 pp, sha256 dee6e99bd0083d49, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF