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CY8C4125LQS-S433

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Infineon/Cypress Semicon Microcontrollers (MCU/MPU/SOC), QFN-40(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllerscy8c4125lqs-s433factory-2.0.0extractor-text
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3D Model

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Symbol & Footprint

Schematic Symbol

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Datasheet

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Contents

README

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CY8C4125LQS-S433

Infineon/Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · QFN-40(6x6)

CY8C4125LQS-S433 from Infineon/Cypress Semicon, in a QFN-40(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2.0 bidirectional GPIO port 2 bit 0 with SAR mux pad 0, smart I/O prgio[0].io[0], TCPWM line[4], csd.comp, LCD com[16]/seg[16] and SCB1 I2C SCL/SPI MOSI options.
2 P2.1 bidirectional GPIO port 2 bit 1 with SAR mux pad 1, smart I/O prgio[0].io[1], TCPWM line_compl[4], LCD com[17]/seg[17] and SCB1 I2C SDA/SPI MISO options.
3 P2.2 bidirectional GPIO port 2 bit 2 with SAR mux pad 2, smart I/O prgio[0].io[2], LCD com[18]/seg[18] and SCB1 SPI clock option.
4 P2.3 bidirectional GPIO port 2 bit 3 with SAR mux pad 3, smart I/O prgio[0].io[3], LCD com[19]/seg[19] and SCB1 SPI select0 option.
5 P2.4 bidirectional GPIO port 2 bit 4 with SAR mux pad 4, smart I/O prgio[0].io[4], TCPWM line[0], LCD com[20]/seg[20] and SCB1 SPI select1 option.
6 P2.5 bidirectional GPIO port 2 bit 5 with SAR mux pad 5, smart I/O prgio[0].io[5], TCPWM line_compl[0], LCD com[21]/seg[21] and SCB1 SPI select2 option.
7 P2.6 bidirectional GPIO port 2 bit 6 with SAR mux pad 6, smart I/O prgio[0].io[6], TCPWM line[1], LCD com[22]/seg[22] and SCB1 SPI select3 option.
8 P2.7 bidirectional GPIO port 2 bit 7 with SAR mux pad 7, smart I/O prgio[0].io[7], TCPWM line_compl[1], LCD com[23]/seg[23], lpcomp.comp[0] and SCB2 SPI MOSI options.
9 VSSD power_in Digital ground pin.
10 P3.0 bidirectional GPIO port 3 bit 0 with smart I/O prgio[1].io[0], TCPWM line[0], SCB1 UART RX, LCD com[24]/seg[24] and SCB1 I2C SCL/SPI MOSI options.
11 P3.1 bidirectional GPIO port 3 bit 1 with smart I/O prgio[1].io[1], TCPWM line_compl[0], SCB1 UART TX, LCD com[25]/seg[25] and SCB1 I2C SDA/SPI MISO options.
12 P3.2 bidirectional GPIO port 3 bit 2 with smart I/O prgio[1].io[2], TCPWM line[1], SCB1 UART CTS, LCD com[26]/seg[26], SWD data (cpuss.swd_data) and SCB1 SPI clock options.
13 P3.3 bidirectional GPIO port 3 bit 3 with smart I/O prgio[1].io[3], TCPWM line_compl[1], SCB1 UART RTS, LCD com[27]/seg[27], SWD clock (cpuss.swd_clk) and SCB1 SPI select0 options.
14 P3.4 bidirectional GPIO port 3 bit 4 with smart I/O prgio[1].io[4], TCPWM line[2], tcpwm.tr_in[6], LCD com[28]/seg[28] and SCB1 SPI select1 option.
15 P3.5 bidirectional GPIO port 3 bit 5 with smart I/O prgio[1].io[5], TCPWM line_compl[2], LCD com[29]/seg[29] and SCB1 SPI select2 option.
16 P3.6 bidirectional GPIO port 3 bit 6 with smart I/O prgio[1].io[6], TCPWM line[3], LCD com[30]/seg[30] and SCB1 SPI select3 option.
17 P3.7 bidirectional GPIO port 3 bit 7 with smart I/O prgio[1].io[7], TCPWM line_compl[3], LCD com[31]/seg[31], lpcomp.comp[1] and SCB2 SPI MISO options.
18 P4.0 bidirectional GPIO port 4 bit 0 with CAPSENSE external Vref (csd.vref_ext), SCB0 UART RX, LCD com[32]/seg[32] and SCB0 I2C SCL/SPI MOSI options.
19 P4.1 bidirectional GPIO port 4 bit 1 with CAPSENSE shield/Cmod (csd.cshield/csd.cmod), SCB0 UART TX, LCD com[33]/seg[33] and SCB0 I2C SDA/SPI MISO options.
20 P4.2 bidirectional GPIO port 4 bit 2 with CAPSENSE Cmod and CintA (csd.cmod/csd.CintA), SCB0 UART CTS, LCD com[34]/seg[34], lpcomp.comp[0] and SCB0 SPI clock options.
21 P4.3 bidirectional GPIO port 4 bit 3 with CAPSENSE shield tank and CintB (csd.csh_tank/csd.csh_CintB), SCB0 UART RTS, LCD com[35]/seg[35], lpcomp.comp[1] and SCB0 SPI select0 options.
22 P0.0 bidirectional GPIO port 0 bit 0 with low-power comparator input lpcomp.in_p[0], SCB2 UART CTS, tcpwm.tr_in[0], LCD com[0]/seg[0] and SCB2 I2C SCL/SCB0 SPI select1 options.
23 P0.1 bidirectional GPIO port 0 bit 1 with low-power comparator input lpcomp.in_n[0], SCB2 UART RTS, tcpwm.tr_in[1], LCD com[1]/seg[1] and SCB2 I2C SDA/SCB0 SPI select2 options.
24 P0.2 bidirectional GPIO port 0 bit 2 with low-power comparator input lpcomp.in_p[1], LCD com[2]/seg[2] and SCB0 SPI select3 option.
25 P0.3 bidirectional GPIO port 0 bit 3 with low-power comparator input lpcomp.in_n[1], LCD com[3]/seg[3] and SCB2 SPI select0 option.
26 P0.4 bidirectional GPIO port 0 bit 4 with watch crystal oscillator input (wco_in), SCB1/SCB2 UART RX, LCD com[4]/seg[4] and SCB1 I2C SCL/SPI MOSI options.
27 P0.5 bidirectional GPIO port 0 bit 5 with watch crystal oscillator output (wco_out), SCB1/SCB2 UART TX, LCD com[5]/seg[5] and SCB1 I2C SDA/SPI MISO options.
28 P0.6 bidirectional GPIO port 0 bit 6 with external clock input (srss.ext_clk), SCB1 UART CTS, SCB2 UART TX, LCD com[6]/seg[6] and SCB1 SPI clock options.
29 P0.7 bidirectional GPIO port 0 bit 7 with TCPWM line[0], SCB1 UART RTS, LCD com[7]/seg[7] and SCB1 SPI select0 options.
30 XRES input External reset input pin.
31 VCCD power_out Regulated digital supply (1.8 V ± 5%); bypass to ground with a 0.1 µF X5R ceramic capacitor and connect nothing else in the 1.8 V to 5.5 V supply mode.
32 VSSD power_in Digital ground pin.
33 VDD power_in Combined VDDA/VDDD supply, shorted internally; 1.8 V to 5.5 V with 0.1 µF and 1 µF decoupling (1.71 V to 1.89 V in externally regulated mode).
34 VSSA power_in Analog ground pin.
35 P1.0 bidirectional GPIO port 1 bit 0 with opamp pad pass.ctb0_pads[0], TCPWM line[2], SCB0 UART RX, LCD com[8]/seg[8] and SCB0 I2C SCL/SPI MOSI options.
36 P1.1 bidirectional GPIO port 1 bit 1 with opamp pad pass.ctb0_pads[1], TCPWM line_compl[2], SCB0 UART TX, LCD com[9]/seg[9] and SCB0 I2C SDA/SPI MISO options.
37 P1.2 bidirectional GPIO port 1 bit 2 with opamp pad pass.ctb0_pads[2], opamp0 10x output (ctb0_oa0_out_10x), TCPWM line[3], SCB0 UART CTS, LCD com[10]/seg[10] and SCB2 I2C SCL/SCB0 SPI clock options.
38 P1.3 bidirectional GPIO port 1 bit 3 with opamp pad pass.ctb0_pads[3], opamp1 10x output (ctb0_oa1_out_10x), TCPWM line_compl[3], SCB0 UART RTS, LCD com[11]/seg[11] and SCB2 I2C SDA/SCB0 SPI select0 options.
39 P1.4 bidirectional GPIO port 1 bit 4 with opamp pad pass.ctb0_pads[4], LCD com[12]/seg[12] and SCB0 SPI select1 option.
40 P1.7/VREF bidirectional GPIO port 1 bit 7 with opamp pad pass.ctb0_pads[7], SAR ADC external Vref (pass.sar_ext_vref0/1), LCD com[15]/seg[15] and SCB2 SPI clock option.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Infineon/Cypress Semicon
Package QFN-40(6x6)
Category Embedded Processors & Controllers
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDDD_ABS -0.5 6 V 27
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 27
Maximum current per GPIO IGPIO_ABS -25 25 mA 27
GPIO injection current IGPIO_injection -0.5 0.5 mA Current injected per pin; Max for VIH > VDDD, Min for VIL < VSS 27
ESD human body model ESD_HBM 2200 V 27
ESD charged device model ESD_CDM 500 V 27
Pin current for latch-up LU -140 140 mA 27
Power supply input voltage (internally regulated) VDD 1.8 5.5 V Internally regulated supply 27
Power supply input voltage (unregulated) VDD 1.71 1.89 V Internally unregulated supply, VCCD = VDDD = VDDA 27
Output voltage for core logic VCCD 1.8 V 27
External regulator voltage bypass CEFC 0.1 µF X5R ceramic or better 28
Power supply bypass capacitor CEXC 1 µF X5R ceramic or better 28
Active mode current, CPU at 6 MHz IDD5 1.8 2.7 mA Execute from flash; CPU at 6 MHz; Max is at 125°C and 5.5 V 28
Active mode current, CPU at 24 MHz IDD8 3 4.75 mA Execute from flash; CPU at 24 MHz; Max is at 125°C and 5.5 V 28
Active mode current, CPU at 48 MHz IDD11 5.4 6.85 mA Execute from flash; CPU at 48 MHz; Max is at 125°C and 5.5 V 28
Sleep current 6 MHz (regulator on) IDD17 1.7 2.2 mA I2C wakeup, WDT, and Comparators on; 6 MHz; Max is at 125°C and 5.5 V 28
Sleep current 12 MHz (regulator on) IDD20 2.2 2.5 mA I2C wakeup, WDT, and Comparators on; 12 MHz; Max is at 125°C and 5.5 V 28
Sleep current 6 MHz (regulator bypassed) IDD23 0.7 0.9 mA I2C wakeup, WDT, and Comparators on; 6 MHz; Max is at 125°C and 5.5 V 28
Sleep current 12 MHz (regulator bypassed) IDD23A 1 1.2 mA I2C wakeup, WDT, and Comparators on; 12 MHz; Max is at 125°C and 5.5 V 28
Deep Sleep current, VDD 1.8 V to 3.6 V IDD26 2.5 150 µA I2C wakeup and WDT on; Max is at 3.6 V and 125°C 28
Deep Sleep current, VDD 3.6 V to 5.5 V IDD29 2.5 150 µA I2C wakeup and WDT on; Max is at 5.5 V and 125°C 28
Deep Sleep current, regulator bypassed IDD32 2.5 160 µA I2C wakeup and WDT on; Max is at 1.89 V and 125°C 28
Supply current while XRES asserted IDD_XR 2 5 mA 28
CPU frequency FCPU 48 MHz 1.71 V ≤ VDD ≤ 5.5 V 28
BOD trip voltage in Active and Sleep modes VFALLPPOR 1.48 1.62 V 48
BOD trip voltage in Deep Sleep mode VFALLDPSLP 1.11 1.5 V 48
SWDCLK frequency FSWDCLK1 14 MHz 3.3 V ≤ VDD ≤ 5.5 V; SWDCLK ≤ 1/3 CPU clock frequency 48
SWDCLK frequency FSWDCLK2 7 MHz 1.71 V ≤ VDD ≤ 3.3 V; SWDCLK ≤ 1/3 CPU clock frequency 48
SWDI setup time TSWDI_SETUP 0.25 ns T = 1/fSWDCLK; min is 0.25 × T 48
SWDI hold time TSWDI_HOLD 0.25 ns T = 1/fSWDCLK; min is 0.25 × T 48
SWDO valid time TSWDO_VALID 0.5 ns T = 1/fSWDCLK; max is 0.5 × T 48
SWDO hold time TSWDO_HOLD 1 ns T = 1/fSWDCLK 48
IMO operating current at 48 MHz IIMO1 250 µA 48
IMO operating current at 24 MHz IIMO2 180 µA 48
IMO frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -2 2 % −40°C ≤ TA ≤ 125°C 48
IMO frequency variation at 24, 32, and 48 MHz (trimmed) FIMOTOL1 -4 4 % 125°C ≤ TA ≤ 150°C 48
IMO startup time TSTARTIMO 7 µs 48
IMO RMS jitter at 24 MHz TJITRMSIMO2 145 ps 48
ILO operating current IILO1 0.3 1.05 µA 49
ILO startup time TSTARTILO1 2 ms 49
ILO duty cycle TILODUTY 40 50 60 % 49
ILO frequency range FILOTRIM1 20 40 80 kHz 49
WCO crystal frequency FWCO 32.768 kHz 49
WCO frequency tolerance FTOL 50 250 ppm With 20-ppm crystal 49
WCO equivalent series resistance ESR 50 kΩ 49
WCO drive level PD 1 µW 49
WCO startup time TSTART 500 ms 49
WCO crystal load capacitance CL 6 12.5 pF 49
WCO crystal shunt capacitance C0 1.35 pF 49
WCO operating current (high power mode) IWCO1 8 µA 49
WCO operating current (low power mode) IWCO2 1 µA 49
External clock input frequency ExtClkFreq 0 48 MHz 49
External clock duty cycle ExtClkDuty 45 55 % Measured at VDD/2 50
System clock source switching time TCLKSWITCH 3 4 Periods 50
Max delay added by PRGIO in bypass mode PRG_BYPASS 1.6 ns 50
Operating ambient temperature (S-grade) TA -40 25 105 °C For S-grade devices 56
Operating junction temperature (S-grade) TJ -40 120 °C For S-grade devices 56
Package thermal resistance junction-to-ambient, 40-pin QFN TJA 25 °C/W 40-pin QFN 56
Package thermal resistance junction-to-case, 40-pin QFN TJC 3 °C/W 40-pin QFN 56

CAD (KiCad official)

  • Symbol: CY8C4125LQS-S433
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: QFN-40(6x6) (KiCad packages3D, STEP)
  • 3D model files: cy8c4125lqs-s433-etched.step / cy8c4125lqs-s433-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4125lqs-s433.step / cy8c4125lqs-s433.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Infineon/Cypress Semicon datasheet (68 pp, sha256 4c3cc0528eecb677, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF