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CY8C4124LQI-443T

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Cypress Semicon Microcontroller Units (MCUs/MPUs/SOCs), QFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY8C4124LQI-443T

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · QFN-40-EP(6x6)

CY8C4124LQI-443T from Cypress Semicon, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2.0 bidirectional Port 2 Pin 0: GPIO with lcd, csd and sarmux.0 analog function.
2 P2.1 bidirectional Port 2 Pin 1: GPIO with lcd, csd and sarmux.1 analog function.
3 P2.2 bidirectional Port 2 Pin 2: GPIO with lcd, csd and sarmux.2 analog function.
4 P2.3 bidirectional Port 2 Pin 3: GPIO with lcd, csd and sarmux.3 analog function.
5 P2.4 bidirectional Port 2 Pin 4: GPIO with lcd, csd, sarmux.4 and tcpwm0_p[1] PWM function.
6 P2.5 bidirectional Port 2 Pin 5: GPIO with lcd, csd, sarmux.5 and tcpwm0_n[1] PWM function.
7 P2.6 bidirectional Port 2 Pin 6: GPIO with lcd, csd, sarmux.6 and tcpwm1_p[1] PWM function.
8 P2.7 bidirectional Port 2 Pin 7: GPIO with lcd, csd, sarmux.7 and tcpwm1_n[1] PWM function.
9 VSS power_in Ground.
10 P3.0 bidirectional Port 3 Pin 0: GPIO with lcd, csd, tcpwm0_p[0] PWM and SCB1 (UART rx, I2C scl, SPI mosi) functions.
11 P3.1 bidirectional Port 3 Pin 1: GPIO with lcd, csd, tcpwm0_n[0] PWM and SCB1 (UART tx, I2C sda, SPI miso) functions.
12 P3.2 bidirectional Port 3 Pin 2: GPIO with lcd, csd, tcpwm1_p[0] PWM, SCB1 SPI clk and swd_io; it is an SWD pin after boot (reset).
13 P3.3 bidirectional Port 3 Pin 3: GPIO with lcd, csd, tcpwm1_n[0] PWM, SCB1 SPI ssel_0 and swd_clk; it is an SWD pin after boot (reset).
14 P3.4 bidirectional Port 3 Pin 4: GPIO with lcd, csd, tcpwm2_p[0] PWM and SCB1 SPI ssel_1 functions.
15 P3.5 bidirectional Port 3 Pin 5: GPIO with lcd, csd, tcpwm2_n[0] PWM and SCB1 SPI ssel_2 functions.
16 P3.6 bidirectional Port 3 Pin 6: GPIO with lcd, csd, tcpwm3_p[0] PWM and SCB1 SPI ssel_3 functions.
17 P3.7 bidirectional Port 3 Pin 7: GPIO with lcd, csd and tcpwm3_n[0] PWM function.
18 P4.0 bidirectional Port 4 Pin 0: GPIO with lcd, csd and SCB0 (UART rx, I2C scl, SPI mosi) functions.
19 P4.1 bidirectional Port 4 Pin 1: GPIO with lcd, csd and SCB0 (UART tx, I2C sda, SPI miso) functions.
20 P4.2 bidirectional Port 4 Pin 2: GPIO with lcd, csd, csd_c_mod analog function and SCB0 SPI clk.
21 P4.3 bidirectional Port 4 Pin 3: GPIO with lcd, csd, csd_c_sh_tank analog function and SCB0 SPI ssel_0.
22 P0.0 bidirectional Port 0 Pin 0: GPIO with lcd, csd, comp1_inp analog input and SCB0 SPI ssel_1.
23 P0.1 bidirectional Port 0 Pin 1: GPIO with lcd, csd, comp1_inn analog input and SCB0 SPI ssel_2.
24 P0.2 bidirectional Port 0 Pin 2: GPIO with lcd, csd, comp2_inp analog input and SCB0 SPI ssel_3.
25 P0.3 bidirectional Port 0 Pin 3: GPIO with lcd, csd and comp2_inn analog input.
26 P0.4 bidirectional Port 0 Pin 4: GPIO with lcd, csd and SCB1 (UART rx, I2C scl, SPI mosi) functions.
27 P0.5 bidirectional Port 0 Pin 5: GPIO with lcd, csd and SCB1 (UART tx, I2C sda, SPI miso) functions.
28 P0.6 bidirectional Port 0 Pin 6: GPIO with lcd, csd, ext_clk and SCB1 SPI clk functions.
29 P0.7 bidirectional Port 0 Pin 7: GPIO with lcd, csd, wakeup and SCB1 SPI ssel_0 functions.
30 XRES input Chip reset, active low, with an internal pull-up resistor that is always enabled.
31 VCCD power_out Regulated digital supply (1.8 V ±5%); connect to a 1 µF capacitor or 1.8 V.
32 VDDD power_in Digital supply, 1.8 - 5.5 V.
33 VDDA power_in Analog supply, 1.8 - 5.5 V, equal to VDDD.
34 VSSA power_in Analog ground.
35 P1.0 bidirectional Port 1 Pin 0: GPIO with lcd, csd, ctb.oa0.inp analog input and tcpwm2_p[1] PWM.
36 P1.1 bidirectional Port 1 Pin 1: GPIO with lcd, csd, ctb.oa0.inm analog input and tcpwm2_n[1] PWM.
37 P1.2 bidirectional Port 1 Pin 2: GPIO with lcd, csd, ctb.oa0.out analog output and tcpwm3_p[1] PWM.
38 P1.3 bidirectional Port 1 Pin 3: GPIO with lcd, csd, ctb.oa1.out analog output and tcpwm3_n[1] PWM.
39 P1.4 bidirectional Port 1 Pin 4: GPIO with lcd, csd and ctb.oa1.inm analog input.
40 P1.7/VREF bidirectional Port 1 Pin 7: GPIO with lcd, csd, ctb.oa1.inp_alt and ext_vref (optional external input and bypass for the SAR reference).
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package QFN-40-EP(6x6)
Category Single Chip Microcomputer/Microcontroller
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSSD VDDD_ABS -0.5 6 V Absolute max 19
Direct digital core voltage input relative to Vssd VCCD_ABS -0.5 1.95 V Absolute max 19
GPIO voltage VGPIO_ABS -0.5 5.5 V Absolute max; printed max is VDD+0.5 19
Maximum current per GPIO IGPIO_ABS -25 25 mA Absolute max 19
GPIO injection current IGPIO_injection -0.5 0.5 mA Absolute max, current injected per pin 19
ESD human body model ESD_HBM 2200 V 19
ESD charged device model ESD_CDM 500 V 19
Pin current for latch-up LU -200 200 mA 19
Power supply input voltage VDD 1.8 5.5 V With regulator enabled 19
Power supply input voltage unregulated VDDD 1.71 1.8 1.89 V Internally unregulated Supply 19
Output voltage (core logic) VCCD 1.8 V 19
External regulator voltage (VCCD) bypass CEFC 1 1.3 1.6 µF X5R ceramic or better 19
Power supply decoupling capacitor CEXC 1 µF X5R ceramic or better 19
Active current, 6 MHz IDD4 2.8 mA Execute from Flash; CPU at 6 MHz 19
Active current, 6 MHz IDD5 2.2 mA Execute from Flash; CPU at 6 MHz; T = 25 °C 19
Active current, 12 MHz IDD7 4.2 mA Execute from Flash; CPU at 12 MHz 19
Active current, 12 MHz IDD8 3.7 mA Execute from Flash; CPU at 12 MHz; T = 25 °C 19
Active current, 24 MHz IDD11 6.7 mA Execute from Flash; CPU at 24 MHz; T = 25 °C 19
Active current, 24 MHz IDD12 7.2 mA Execute from Flash; CPU at 24 MHz 19
Sleep current, 6 MHz IDD20 1.3 1.8 mA I2C wakeup, WDT, and Comparators on. 6 MHz; VDD = 1.71 to 5.5 V 19
Sleep current, 12 MHz IDD20A 1.7 2.2 mA I2C wakeup, WDT, and Comparators on. 12 MHz; VDD = 1.71 to 5.5 V 19
Deep Sleep current 1.8-3.6 V IDD26 1.3 µA I2C wakeup and WDT on; T = 25 °C 19
Deep Sleep current 1.8-3.6 V IDD27 45 µA I2C wakeup and WDT on; T = 85 °C 20
Deep Sleep current 3.6-5.5 V IDD29 1.5 15 µA I2C wakeup and WDT on; Typ at 25 °C, Max at 85 °C 20
Deep Sleep current 1.71-1.89 V IDD32 1.7 µA I2C wakeup and WDT on; T = 25 °C 20
Deep Sleep current 1.71-1.89 V IDD33 60 µA I2C wakeup and WDT on; T = 85 °C 20
Hibernate current 1.8-3.6 V IDD35 150 nA GPIO and Reset active; T = 25 °C 20
Hibernate current 1.8-3.6 V IDD36 1000 nA GPIO and Reset active; T = 85 °C 20
Hibernate current 3.6-5.5 V IDD38 150 nA GPIO and Reset active; T = 25 °C 20
Hibernate current 1.71-1.89 V IDD41 150 nA GPIO and Reset active; T = 25 °C 20
Hibernate current 1.71-1.89 V IDD42 1000 nA GPIO and Reset active; T = 85 °C 20
Stop mode current IDD43A 20 80 nA VDD = 3.3 V; Typ at 25 °C, Max at 85 °C 20
Supply current while XRES asserted IDD_XR 2 5 mA 20
CPU frequency FCPU 24 MHz 1.71 ≤ VDD ≤ 5.5 20
Wakeup from Deep Sleep mode TDEEPSLEEP 25 µs 24-MHz IMO. Guaranteed by characterization 20
Wakeup from Hibernate and Stop modes THIBERNATE 2 ms Guaranteed by characterization 20
External reset pulse width TRESETWIDTH 1 µs Guaranteed by characterization 20
Trimmed internal reference to SAR VREFSAR -1 1 % Percentage of Vbg (1.024 V). Guaranteed by characterization 33
Clock switching from clk1 to clk2 in clk1 periods TCLKSWITCH 3 4 Periods Guaranteed by design 33
Operating ambient temperature TA -40 25 105 °C 36
Operating junction temperature TJ -40 125 °C 36
Deep Sleep current +105 °C, regulator off IDD28Q 135 µA I2C wakeup and WDT on. Regulator Off; VDD = 1.71 to 1.89 20
Number of wait states at 24 MHz TWS24 0 CPU execution from Flash. Guaranteed by characterization 33
Package thermal resistance junction-to-ambient (40-pin QFN) TJA 15.34 °C/Watt 36
Package thermal resistance junction-to-case (40-pin QFN) TJC 2.5 °C/Watt 36

CAD (KiCad official)

  • Symbol: CY8C4124LQI-443T
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: cy8c4124lqi-443t-etched.step / cy8c4124lqi-443t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4124lqi-443t.step / cy8c4124lqi-443t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (44 pp, sha256 96f5358c3c46932a, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF