component
CY8C4046LQI-T452
Public Made by Adomby adom
Infineon/Cypress Semicon , QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
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{
"slug": "cy8c4046lqi-t452",
"version": "0.1.0",
"type": "component",
"description": "Infineon/Cypress Semicon , QFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"ic",
"cy8c4046lqi-t452",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"cy8c4046lqi-t452.kicad_sym",
"cy8c4046lqi-t452.kicad_mod",
"cy8c4046lqi-t452.glb",
"cy8c4046lqi-t452.step",
"cy8c4046lqi-t452.lbr",
"docs/hero.png",
"docs/cy8c4046lqi-t452-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"cy8c4046lqi-t452-hero.glb",
"cy8c4046lqi-t452-hero.overlay.json",
"cy8c4046lqi-t452-etched.glb"
],
"component": {
"mpn": "CY8C4046LQI-T452",
"manufacturer": "Infineon/Cypress Semicon",
"package": "QFN-24(4x4)",
"pin_count": 25,
"category": "IC",
"subcategory": "IC",
"datasheet": "https://www.infineon.com/dgdl/Infineon-PSoC_4000T_MCU_datasheet-DataSheet-v09_00-EN.pdf?fileId=8ac78c8c8a44f57b018a799f5fb53b5d",
"parts": {
"symbol": "cy8c4046lqi-t452.kicad_sym",
"footprint": "cy8c4046lqi-t452.kicad_mod",
"model_3d": "cy8c4046lqi-t452-hero.glb",
"model_3d_plain": "cy8c4046lqi-t452-etched.glb",
"model_3d_step": "cy8c4046lqi-t452-etched.step",
"model_3d_step_plain": "cy8c4046lqi-t452.step",
"lbr": "cy8c4046lqi-t452.lbr"
},
"distributor_links": {
"lcsc": "C22408361"
},
"distributor_check": {
"checked_at": "2026-10-23T18:21:23Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": null,
"status": "deferred",
"error": "shared DigiKey quota guard: 884 calls left today"
},
"mouser": {
"pn": null,
"status": "quota"
}
},
"pins": [
{
"number": "1",
"name": "P2.1",
"type": "bidirectional",
"description": "GPIO port 2 bit 1 with CAPSENSE sense/drive function csd.msc_gpio_ctrl_sns[8] and Deep Sleep csd.obs_data[2]."
},
{
"number": "2",
"name": "P2.2",
"type": "bidirectional",
"description": "GPIO port 2 bit 2 with CAPSENSE sense function, tcpwm.line[0]:1, uart_rx:3, spi_mosi:3 and scb[1].i2c_scl:1 alternates."
},
{
"number": "3",
"name": "P2.3",
"type": "bidirectional",
"description": "GPIO port 2 bit 3 with CAPSENSE sense function, tcpwm.line_compl[0]:1, uart_tx:3, spi_miso:3 and scb[1].i2c_sda:1 alternates."
},
{
"number": "4",
"name": "P2.4",
"type": "bidirectional",
"description": "GPIO port 2 bit 4 with CAPSENSE sense function, tcpwm.line[1]:1, uart_cts:3, spi_clk:3 and csd.ext_sync:1 alternates."
},
{
"number": "5",
"name": "P2.5",
"type": "bidirectional",
"description": "GPIO port 2 bit 5 with CAPSENSE sense function, tcpwm.line_compl[1]:1, uart_rts:3, spi_select0:3 and csd.ext_sync_clk:1 alternates."
},
{
"number": "6",
"name": "P3.0",
"type": "bidirectional",
"description": "GPIO port 3 bit 0 with CAPSENSE sense function, tcpwm.line[0]:0, uart_rx:1, i2c_scl:1 and spi_mosi:1 alternates."
},
{
"number": "7",
"name": "P3.2",
"type": "bidirectional",
"description": "GPIO port 3 bit 2 with CAPSENSE sense function, tcpwm.line[1]:0, uart_cts:1, spi_clk:1, scb[1].i2c_sda:0 and SWD data (cpuss.swd_data:0) alternates."
},
{
"number": "8",
"name": "P3.3",
"type": "bidirectional",
"description": "GPIO port 3 bit 3 with CAPSENSE sense function, tcpwm.line_compl[1]:0, uart_rts:1, spi_select0:1, scb[1].i2c_scl:0 and SWD clock (cpuss.swd_clk:0) alternates."
},
{
"number": "9",
"name": "P4.0",
"type": "bidirectional",
"description": "GPIO port 4 bit 0 with CAPSENSE sense function, uart_rx:0, i2c_scl:0, spi_mosi:2 and tcpwm.tr_in[6] alternates."
},
{
"number": "10",
"name": "P4.1",
"type": "bidirectional",
"description": "GPIO port 4 bit 1 with CAPSENSE sense function, uart_tx:0, i2c_sda:0 and spi_miso:2 alternates."
},
{
"number": "11",
"name": "P4.2",
"type": "bidirectional",
"description": "GPIO port 4 bit 2 with CAPSENSE Cmod1 function (csd.msc_gpio_ctrl_cmod1), uart_cts:0 and spi_clk:2 alternates."
},
{
"number": "12",
"name": "P4.3",
"type": "bidirectional",
"description": "GPIO port 4 bit 3 with CAPSENSE Cmod2 function (csd.msc_gpio_ctrl_cmod2), uart_rts:0 and spi_select0:2 alternates."
},
{
"number": "13",
"name": "P0.0",
"type": "bidirectional",
"description": "GPIO port 0 bit 0 with CAPSENSE sense function, tcpwm.tr_in[0], csd.ext_sync:0 and spi_select1:0 alternates."
},
{
"number": "14",
"name": "P0.1",
"type": "bidirectional",
"description": "GPIO port 0 bit 1 with CAPSENSE sense function, tcpwm.tr_in[1], csd.ext_sync_clk:0 and spi_select2:0 alternates."
},
{
"number": "15",
"name": "P0.2",
"type": "bidirectional",
"description": "GPIO port 0 bit 2 with CAPSENSE sense function, uart_rx:2, i2c_scl:2, spi_mosi:0 and SWD clock (cpuss.swd_clk:1) alternates."
},
{
"number": "16",
"name": "P0.3",
"type": "bidirectional",
"description": "GPIO port 0 bit 3 with CAPSENSE sense function, uart_tx:2, i2c_sda:2, spi_miso:0 and SWD data (cpuss.swd_data:1) alternates."
},
{
"number": "17",
"name": "P0.4",
"type": "bidirectional",
"description": "GPIO port 0 bit 4 with CAPSENSE sense function, srss.ext_clk, uart_cts:2, spi_clk:0 and csd.ext_frm_start:0 alternates."
},
{
"number": "18",
"name": "XRES",
"type": "input",
"description": "External reset input for the device."
},
{
"number": "19",
"name": "VCCD",
"type": "power_out",
"description": "Regulated digital supply (1.8 V ±5%); must be bypassed to ground with a 2.2 µF X5R ceramic or better capacitor and connected to nothing else in the 2.0 V to 5.5 V supply mode, or shorted to VDDD in the 1.8 V ±5% supply mode."
},
{
"number": "20",
"name": "VSSD",
"type": "power_in",
"description": "Ground pin for the digital section."
},
{
"number": "21",
"name": "VDDD",
"type": "power_in",
"description": "Power supply for the digital section, 2.0 V to 5.5 V (or 1.71 V to 1.89 V when externally regulated)."
},
{
"number": "22",
"name": "VSSA",
"type": "power_in",
"description": "Ground pin for the CAPSENSE section."
},
{
"number": "23",
"name": "P1.0",
"type": "bidirectional",
"description": "GPIO port 1 bit 0 with CAPSENSE sense function, tcpwm.line[1]:2, tcpwm.tr_in[2] and spi_select3:0 alternates."
},
{
"number": "24",
"name": "P2.0",
"type": "bidirectional",
"description": "GPIO port 2 bit 0 with CAPSENSE sense function, tcpwm.line_compl[1]:2, tcpwm.tr_in[3] and csd.obs_data[3] alternates."
},
{
"number": "25",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-sonnet-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: In Table 1 the row for P2.1 lacks explicit dashes for the 16-QFN column; pin 1 = P2.1 for 24-QFN is ; The text provided does not show the 24-QFN package drawing or pinout figure, so the exposed center p; The pin type for VCCD (power_out) is an interpretation of the described internal regulator output; t",
"2/25 pins cited to the wrong page (name found elsewhere): ['19:VCCD@p16', '21:VDDD@p16']"
],
"pages_sent": 19,
"cost_usd": 0.2065,
"at": "2026-10-23T18:21:03"
},
"datasheet": {
"url": "https://www.infineon.com/dgdl/Infineon-PSoC_4000T_MCU_datasheet-DataSheet-v09_00-EN.pdf?fileId=8ac78c8c8a44f57b018a799f5fb53b5d",
"pages": 46,
"sha256": "91700ca10102b80f",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 25,
"described": 25,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "cy8c4046lqi-t452.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
4.0,
4.0,
0.77
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "096fc110543e6d324c5120c2d38e3dca87a389da9b6fac234f1fe40856295ef4",
"checked": "2026-10-23",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cy8c4046lqi-t452-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
4.0,
4.0,
0.77
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "deca0221f9dba9c18011ba9b06e1b957c0694ebb287f08385b9493032abf02ab",
"checked": "2026-10-23",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
}
}