CY8C4025AXI-S412

Cypress Semicon · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-32(7x7)

CY8C4025AXI-S412 from Cypress Semicon, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P1.7	bidirectional	GPIO port pin P1.7; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
2	P2.0	bidirectional	GPIO port pin P2.0; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
3	P2.1	bidirectional	GPIO port pin P2.1; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
4	P2.2	bidirectional	GPIO port pin P2.2; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
5	P2.3	bidirectional	GPIO port pin P2.3; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
6	P2.5	bidirectional	GPIO port pin P2.5; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
7	P2.6	bidirectional	GPIO port pin P2.6; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
8	P2.7	bidirectional	GPIO port pin P2.7; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
9	P3.0	bidirectional	GPIO port pin P3.0; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
10	P3.1	bidirectional	GPIO port pin P3.1; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
11	P3.2	bidirectional	GPIO port pin P3.2; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
12	P3.3	bidirectional	GPIO port pin P3.3; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
13	P4.0	bidirectional	GPIO port pin P4.0; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
14	P4.1	bidirectional	GPIO port pin P4.1; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
15	P4.2	bidirectional	GPIO port pin P4.2; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
16	P4.3	bidirectional	GPIO port pin P4.3; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
17	P0.0	bidirectional	GPIO port pin P0.0; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
18	P0.1	bidirectional	GPIO port pin P0.1; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
19	P0.2	bidirectional	GPIO port pin P0.2; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
20	P0.3	bidirectional	GPIO port pin P0.3; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
21	P0.4	bidirectional	GPIO port pin P0.4; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
22	P0.5	bidirectional	GPIO port pin P0.5; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
23	P0.6	bidirectional	GPIO port pin P0.6; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
24	XRES	input	External reset pin listed in the pin table; the provided pages give no electrical limits for it.
25	VCCD	power_out	Regulated digital supply (1.8 V ± 5%) that must be bypassed to ground via an external 0.1 µF X5R ceramic or better capacitor and must not be connected to anything else.
26	VSSD	power_in	Ground pin for the digital section.
27	VDD	power_in	Power supply to all sections of the chip; 1.8 V to 5.5 V in Mode 1 and 1.71 V to 1.89 V in Mode 2 with the internal regulator bypassed.
28	VSSA	power_in	Ground pin for the analog section.
29	P1.0	bidirectional	GPIO port pin P1.0; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
30	P1.1	bidirectional	GPIO port pin P1.1; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
31	P1.2	bidirectional	GPIO port pin P1.2; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.
32	P1.3	bidirectional	GPIO port pin P1.3; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital.

Key specifications

Parameter	Value
Manufacturer	Cypress Semicon
Package	TQFP-32(7x7)
Category	Single Chip Microcomputer/Microcontroller
Pins	32

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Digital supply relative to VSS	VDDD_ABS	-0.5		6	V		21
Direct digital core voltage input relative to VSS	VCCD_ABS	-0.5		1.95	V		21
Maximum current per GPIO	IGPIO_ABS	-25		25	mA		21
GPIO injection current	IGPIO_injection	-0.5		0.5	mA	Current injected per pin	21
Electrostatic discharge human body model	ESD_HBM	2200			V		21
Electrostatic discharge charged device model	ESD_CDM	500			V		21
Pin current for latch-up	LU	-140		140	mA		21
Power supply input voltage	VDD	1.8		5.5	V	Internally regulated supply	22
Power supply input voltage (VCCD = VDD = VDDA)	VDD	1.71		1.89	V	Internally unregulated supply	22
Output voltage (for core logic)	VCCD		1.8		V		22
External regulator voltage bypass	CEFC		0.1		µF	X5R ceramic or better	22
Power supply bypass capacitor	CEXC		1		µF	X5R ceramic or better	22
Execute from flash; CPU at 6 MHz active supply current	IDD5		1.2	2	mA	Active mode, VDD = 1.8 V to 5.5 V	22
Execute from flash; CPU at 24 MHz active supply current	IDD8		2.4	4	mA	Active mode, VDD = 1.8 V to 5.5 V	22
Execute from flash; CPU at 48 MHz active supply current	IDD11		4.6	5.9	mA	Active mode, VDD = 1.8 V to 5.5 V	22
I2C wakeup WDT and comparators on, 6 MHz sleep current	IDD17		1.1	1.6	mA	Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator on), 6 MHz	22
I2C wakeup, WDT, and comparators on, 12 MHz sleep current	IDD20		1.4	1.9	mA	Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator on), 12 MHz	22
I2C wakeup, WDT, and Comparators on, 6 MHz sleep current	IDD23		0.7	0.9	mA	Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed), 6 MHz	22
I2C wakeup, WDT, and Comparators on, 12 MHz sleep current	IDD23A		0.9	1.1	mA	Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed), 12 MHz	22
I2C wakeup and WDT on Deep Sleep current	IDD26		2.5	60	µA	Deep Sleep mode, VDD = 1.8 V to 3.6 V (Regulator on)	22
Supply current while XRES asserted	IDD_XR		2	5	mA		22
IMO operating current at 48 MHz	IIMO1			250	µA		39
IMO operating current at 24 MHz	IIMO2			180	µA		39
Frequency variation at 24, 32, and 48 MHz (trimmed)	FIMOTOL1	-2		2	%	At -40°C to 85°C, for industrial temperature range and original extended industrial range parts	39
IMO startup time	TSTARTIMO			7	µs		39
ILO operating current	IILO1		0.3	1.05	µA		40
ILO startup time	TSTARTILO1			2	ms		40
ILO duty cycle	TILODUTY	40	50	60	%		40
ILO frequency range	FILOTRIM1	20	40	80	kHz		40
Crystal frequency	FWCO		32.768		kHz		40
Frequency tolerance	FTOL		50	250	ppm	With 20-ppm crystal	40
Equivalent series resistance	ESR		50		kΩ		40
Drive level	PD			1	µW		40
Startup time	TSTART			500	ms		40
Crystal load capacitance	CL	6		12.5	pF		40
Crystal shunt capacitance	C0		1.35		pF		40
Operating current (high power mode)	IWCO1			8	µA		40
Operating current (low power mode)	IWCO2			1	µA		40
External clock input frequency	ExtClkFreq	0		48	MHz		41
Duty cycle	ExtClkDuty	45		55	%	measured at VDD/2	41
System clock source switching time	TCLKSWITCH	3		4	Periods		41
Max delay added by Smart I/O in Bypass Mode	PRG_BYPASS			1.6	ns		41
Operating ambient temperature	TA	-40	25	105	°C		44
Operating junction temperature	TJ	-40		125	°C		44
Package θJA 32LD TQFP	TJA		29.4		°C/W		44
Package θJC 32LD TQFP	TJC		3.5		°C/W		44

CAD (KiCad official)

Symbol: CY8C4025AXI-S412
Footprint: Package_QFP:TQFP-32_7x7mm_P0.8mm
3D model: TQFP-32(7x7) (KiCad packages3D, STEP)
3D model files: cy8c4025axi-s412-etched.step / cy8c4025axi-s412-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4025axi-s412.step / cy8c4025axi-s412.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cypress Semicon datasheet (58 pp, sha256 493ab905a29a5d98, retrieved 2026-10-27, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# CY8C4025AXI-S412

**Cypress Semicon** · Microcontroller Units (MCUs/MPUs/SOCs) · TQFP-32(7x7)

CY8C4025AXI-S412 from Cypress Semicon, in a TQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P1.7 | bidirectional | GPIO port pin P1.7; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 2 | P2.0 | bidirectional | GPIO port pin P2.0; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 3 | P2.1 | bidirectional | GPIO port pin P2.1; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 4 | P2.2 | bidirectional | GPIO port pin P2.2; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 5 | P2.3 | bidirectional | GPIO port pin P2.3; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 6 | P2.5 | bidirectional | GPIO port pin P2.5; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 7 | P2.6 | bidirectional | GPIO port pin P2.6; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 8 | P2.7 | bidirectional | GPIO port pin P2.7; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 9 | P3.0 | bidirectional | GPIO port pin P3.0; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 10 | P3.1 | bidirectional | GPIO port pin P3.1; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 11 | P3.2 | bidirectional | GPIO port pin P3.2; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 12 | P3.3 | bidirectional | GPIO port pin P3.3; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 13 | P4.0 | bidirectional | GPIO port pin P4.0; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 14 | P4.1 | bidirectional | GPIO port pin P4.1; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 15 | P4.2 | bidirectional | GPIO port pin P4.2; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 16 | P4.3 | bidirectional | GPIO port pin P4.3; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 17 | P0.0 | bidirectional | GPIO port pin P0.0; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 18 | P0.1 | bidirectional | GPIO port pin P0.1; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 19 | P0.2 | bidirectional | GPIO port pin P0.2; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 20 | P0.3 | bidirectional | GPIO port pin P0.3; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 21 | P0.4 | bidirectional | GPIO port pin P0.4; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 22 | P0.5 | bidirectional | GPIO port pin P0.5; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 23 | P0.6 | bidirectional | GPIO port pin P0.6; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 24 | XRES | input | External reset pin listed in the pin table; the provided pages give no electrical limits for it. |
| 25 | VCCD | power_out | Regulated digital supply (1.8 V ± 5%) that must be bypassed to ground via an external 0.1 µF X5R ceramic or better capacitor and must not be connected to anything else. |
| 26 | VSSD | power_in | Ground pin for the digital section. |
| 27 | VDD | power_in | Power supply to all sections of the chip; 1.8 V to 5.5 V in Mode 1 and 1.71 V to 1.89 V in Mode 2 with the internal regulator bypassed. |
| 28 | VSSA | power_in | Ground pin for the analog section. |
| 29 | P1.0 | bidirectional | GPIO port pin P1.0; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 30 | P1.1 | bidirectional | GPIO port pin P1.1; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 31 | P1.2 | bidirectional | GPIO port pin P1.2; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |
| 32 | P1.3 | bidirectional | GPIO port pin P1.3; all port pins support GPIO and can be configured as CAPSENSE, analog, or digital. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | TQFP-32(7x7) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 32 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Digital supply relative to VSS | VDDD_ABS | -0.5 |  | 6 | V |  | 21 |
| Direct digital core voltage input relative to VSS | VCCD_ABS | -0.5 |  | 1.95 | V |  | 21 |
| Maximum current per GPIO | IGPIO_ABS | -25 |  | 25 | mA |  | 21 |
| GPIO injection current | IGPIO_injection | -0.5 |  | 0.5 | mA | Current injected per pin | 21 |
| Electrostatic discharge human body model | ESD_HBM | 2200 |  |  | V |  | 21 |
| Electrostatic discharge charged device model | ESD_CDM | 500 |  |  | V |  | 21 |
| Pin current for latch-up | LU | -140 |  | 140 | mA |  | 21 |
| Power supply input voltage | VDD | 1.8 |  | 5.5 | V | Internally regulated supply | 22 |
| Power supply input voltage (VCCD = VDD = VDDA) | VDD | 1.71 |  | 1.89 | V | Internally unregulated supply | 22 |
| Output voltage (for core logic) | VCCD |  | 1.8 |  | V |  | 22 |
| External regulator voltage bypass | CEFC |  | 0.1 |  | µF | X5R ceramic or better | 22 |
| Power supply bypass capacitor | CEXC |  | 1 |  | µF | X5R ceramic or better | 22 |
| Execute from flash; CPU at 6 MHz active supply current | IDD5 |  | 1.2 | 2 | mA | Active mode, VDD = 1.8 V to 5.5 V | 22 |
| Execute from flash; CPU at 24 MHz active supply current | IDD8 |  | 2.4 | 4 | mA | Active mode, VDD = 1.8 V to 5.5 V | 22 |
| Execute from flash; CPU at 48 MHz active supply current | IDD11 |  | 4.6 | 5.9 | mA | Active mode, VDD = 1.8 V to 5.5 V | 22 |
| I2C wakeup WDT and comparators on, 6 MHz sleep current | IDD17 |  | 1.1 | 1.6 | mA | Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator on), 6 MHz | 22 |
| I2C wakeup, WDT, and comparators on, 12 MHz sleep current | IDD20 |  | 1.4 | 1.9 | mA | Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator on), 12 MHz | 22 |
| I2C wakeup, WDT, and Comparators on, 6 MHz sleep current | IDD23 |  | 0.7 | 0.9 | mA | Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed), 6 MHz | 22 |
| I2C wakeup, WDT, and Comparators on, 12 MHz sleep current | IDD23A |  | 0.9 | 1.1 | mA | Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed), 12 MHz | 22 |
| I2C wakeup and WDT on Deep Sleep current | IDD26 |  | 2.5 | 60 | µA | Deep Sleep mode, VDD = 1.8 V to 3.6 V (Regulator on) | 22 |
| Supply current while XRES asserted | IDD_XR |  | 2 | 5 | mA |  | 22 |
| IMO operating current at 48 MHz | IIMO1 |  |  | 250 | µA |  | 39 |
| IMO operating current at 24 MHz | IIMO2 |  |  | 180 | µA |  | 39 |
| Frequency variation at 24, 32, and 48 MHz (trimmed) | FIMOTOL1 | -2 |  | 2 | % | At -40°C to 85°C, for industrial temperature range and original extended industrial range parts | 39 |
| IMO startup time | TSTARTIMO |  |  | 7 | µs |  | 39 |
| ILO operating current | IILO1 |  | 0.3 | 1.05 | µA |  | 40 |
| ILO startup time | TSTARTILO1 |  |  | 2 | ms |  | 40 |
| ILO duty cycle | TILODUTY | 40 | 50 | 60 | % |  | 40 |
| ILO frequency range | FILOTRIM1 | 20 | 40 | 80 | kHz |  | 40 |
| Crystal frequency | FWCO |  | 32.768 |  | kHz |  | 40 |
| Frequency tolerance | FTOL |  | 50 | 250 | ppm | With 20-ppm crystal | 40 |
| Equivalent series resistance | ESR |  | 50 |  | kΩ |  | 40 |
| Drive level | PD |  |  | 1 | µW |  | 40 |
| Startup time | TSTART |  |  | 500 | ms |  | 40 |
| Crystal load capacitance | CL | 6 |  | 12.5 | pF |  | 40 |
| Crystal shunt capacitance | C0 |  | 1.35 |  | pF |  | 40 |
| Operating current (high power mode) | IWCO1 |  |  | 8 | µA |  | 40 |
| Operating current (low power mode) | IWCO2 |  |  | 1 | µA |  | 40 |
| External clock input frequency | ExtClkFreq | 0 |  | 48 | MHz |  | 41 |
| Duty cycle | ExtClkDuty | 45 |  | 55 | % | measured at VDD/2 | 41 |
| System clock source switching time | TCLKSWITCH | 3 |  | 4 | Periods |  | 41 |
| Max delay added by Smart I/O in Bypass Mode | PRG_BYPASS |  |  | 1.6 | ns |  | 41 |
| Operating ambient temperature | TA | -40 | 25 | 105 | °C |  | 44 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 44 |
| Package θJA 32LD TQFP | TJA |  | 29.4 |  | °C/W |  | 44 |
| Package θJC 32LD TQFP | TJC |  | 3.5 |  | °C/W |  | 44 |

## CAD (KiCad official)

- Symbol: `CY8C4025AXI-S412`
- Footprint: `Package_QFP:TQFP-32_7x7mm_P0.8mm`
- 3D model: TQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files: `cy8c4025axi-s412-etched.step` / `cy8c4025axi-s412-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cy8c4025axi-s412.step` / `cy8c4025axi-s412.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Cypress Semicon datasheet](https://www.infineon.com/dgdl/Infineon-PSoC_4_PSoC_4000S_Datasheet_Programmable_System-on-Chip_(PSoC_)-DataSheet-v16_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0eda97715cf1) (58 pp, sha256 `493ab905a29a5d98`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/cy8c4025axi-s412-datasheet.pdf)