component
CY8C4024LQI-S402
Public Made by Adomby adom
Infineon/Cypress Semicon Microcontrollers (MCU/MPU/SOC), QFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
Ray
Publish 0.1.0
2033ce9
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{
"slug": "cy8c4024lqi-s402",
"version": "0.1.0",
"type": "component",
"description": "Infineon/Cypress Semicon Microcontrollers (MCU/MPU/SOC), QFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",
"tags": [
"component",
"embedded processors & controllers",
"cy8c4024lqi-s402",
"factory-2.0.0",
"extractor-text"
],
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"cy8c4024lqi-s402.kicad_sym",
"cy8c4024lqi-s402.kicad_mod",
"cy8c4024lqi-s402.glb",
"cy8c4024lqi-s402.step",
"cy8c4024lqi-s402.lbr",
"docs/hero.png",
"docs/cy8c4024lqi-s402-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html",
"cy8c4024lqi-s402-hero.glb",
"cy8c4024lqi-s402-hero.overlay.json"
],
"component": {
"mpn": "CY8C4024LQI-S402",
"manufacturer": "Infineon/Cypress Semicon",
"package": "QFN-32(5x5)",
"pin_count": 33,
"category": "Embedded Processors & Controllers",
"subcategory": "Microcontrollers (MCU/MPU/SOC)",
"datasheet": "https://www.infineon.com/dgdl/Infineon-PSoC_4_PSoC_4000S_Datasheet_Programmable_System-on-Chip_(PSoC_)-DataSheet-v15_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0eda97715cf1&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-file",
"parts": {
"symbol": "cy8c4024lqi-s402.kicad_sym",
"footprint": "cy8c4024lqi-s402.kicad_mod",
"model_3d": "cy8c4024lqi-s402-hero.glb",
"model_3d_plain": "cy8c4024lqi-s402.glb",
"model_3d_step": "cy8c4024lqi-s402-etched.step",
"model_3d_step_plain": "cy8c4024lqi-s402.step",
"lbr": "cy8c4024lqi-s402.lbr"
},
"distributor_links": {
"lcsc": "C5651646",
"digikey": "448-CY8C4024LQI-S402-ND",
"mouser": "727-CY8C4024LQI-S402"
},
"distributor_check": {
"checked_at": "2026-11-12T20:12:05Z",
"source": "Component Ocean /api/assign-pns",
"digikey": {
"pn": "448-CY8C4024LQI-S402-ND",
"status": "found"
},
"mouser": {
"pn": "727-CY8C4024LQI-S402",
"status": "found"
}
},
"pins": [
{
"number": "1",
"name": "P1.7",
"type": "bidirectional",
"description": "Port 1 GPIO bit 7 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and interrupt capability."
},
{
"number": "2",
"name": "P2.0",
"type": "bidirectional",
"description": "Port 2 GPIO bit 0 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2."
},
{
"number": "3",
"name": "P2.1",
"type": "bidirectional",
"description": "Port 2 GPIO bit 1 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2."
},
{
"number": "4",
"name": "P2.2",
"type": "bidirectional",
"description": "Port 2 GPIO bit 2 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O and SCB alternate functions listed in Table 2."
},
{
"number": "5",
"name": "P2.3",
"type": "bidirectional",
"description": "Port 2 GPIO bit 3 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O and SCB alternate functions listed in Table 2."
},
{
"number": "6",
"name": "P2.5",
"type": "bidirectional",
"description": "Port 2 GPIO bit 5 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2."
},
{
"number": "7",
"name": "P2.6",
"type": "bidirectional",
"description": "Port 2 GPIO bit 6 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2."
},
{
"number": "8",
"name": "P2.7",
"type": "bidirectional",
"description": "Port 2 GPIO bit 7 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM, LPCOMP and SCB alternate functions listed in Table 2."
},
{
"number": "9",
"name": "P3.0",
"type": "bidirectional",
"description": "Port 3 GPIO bit 0 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2."
},
{
"number": "10",
"name": "P3.1",
"type": "bidirectional",
"description": "Port 3 GPIO bit 1 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM and SCB alternate functions listed in Table 2."
},
{
"number": "11",
"name": "P3.2",
"type": "bidirectional",
"description": "Port 3 GPIO bit 2 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM, SCB and SWD data alternate functions listed in Table 2."
},
{
"number": "12",
"name": "P3.3",
"type": "bidirectional",
"description": "Port 3 GPIO bit 3 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the Smart I/O, TCPWM, SCB and SWD clock alternate functions listed in Table 2."
},
{
"number": "13",
"name": "P4.0",
"type": "bidirectional",
"description": "Port 4 GPIO bit 0 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the CSD VREF_EXT, TCPWM and SCB alternate functions listed in Table 2."
},
{
"number": "14",
"name": "P4.1",
"type": "bidirectional",
"description": "Port 4 GPIO bit 1 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the CSD CSHIELDPADS, TCPWM and SCB alternate functions listed in Table 2."
},
{
"number": "15",
"name": "P4.2",
"type": "bidirectional",
"description": "Port 4 GPIO bit 2 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the CSD CMODPAD, LPCOMP and SCB alternate functions listed in Table 2."
},
{
"number": "16",
"name": "P4.3",
"type": "bidirectional",
"description": "Port 4 GPIO bit 3 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the CSD CSH_TANK, LPCOMP and SCB alternate functions listed in Table 2."
},
{
"number": "17",
"name": "P0.0",
"type": "bidirectional",
"description": "Port 0 GPIO bit 0 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the LPCOMP positive input 0 and TCPWM/SCB alternate functions listed in Table 2."
},
{
"number": "18",
"name": "P0.1",
"type": "bidirectional",
"description": "Port 0 GPIO bit 1 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the LPCOMP negative input 0 and TCPWM/SCB alternate functions listed in Table 2."
},
{
"number": "19",
"name": "P0.2",
"type": "bidirectional",
"description": "Port 0 GPIO bit 2 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the LPCOMP positive input 1 and SCB alternate functions listed in Table 2."
},
{
"number": "20",
"name": "P0.3",
"type": "bidirectional",
"description": "Port 0 GPIO bit 3 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the LPCOMP negative input 1 alternate function listed in Table 2."
},
{
"number": "21",
"name": "P0.4",
"type": "bidirectional",
"description": "Port 0 GPIO bit 4 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the WCO input (wco_in) and SCB alternate functions listed in Table 2."
},
{
"number": "22",
"name": "P0.5",
"type": "bidirectional",
"description": "Port 0 GPIO bit 5 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the WCO output (wco_out) and SCB alternate functions listed in Table 2."
},
{
"number": "23",
"name": "P0.6",
"type": "bidirectional",
"description": "Port 0 GPIO bit 6 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the SRSS external clock and SCB alternate functions listed in Table 2."
},
{
"number": "24",
"name": "XRES",
"type": "input",
"description": "External reset pin listed in Table 1 of the 32-pin QFN column; the provided text gives no electrical limits or polarity for it."
},
{
"number": "25",
"name": "VCCD",
"type": "power_out",
"description": "Regulated digital supply output (1.8 V ± 5%) that must be bypassed to ground with an external 0.1 µF X5R ceramic or better capacitor and must not be connected to anything else in Mode 1."
},
{
"number": "26",
"name": "VSSD",
"type": "power_in",
"description": "Ground pin for the digital section of the chip."
},
{
"number": "27",
"name": "VDD",
"type": "power_in",
"description": "Power supply to all sections of the chip, specified at 1.8 V to 5.5 V in Mode 1 and 1.71 V to 1.89 V in Mode 2 where VDD and VCCD are shorted together."
},
{
"number": "28",
"name": "VSSA",
"type": "power_in",
"description": "Ground pin for the analog section of the chip."
},
{
"number": "29",
"name": "P1.0",
"type": "bidirectional",
"description": "Port 1 GPIO bit 0 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the TCPWM, SCB UART and I2C/SPI alternate functions listed in Table 2."
},
{
"number": "30",
"name": "P1.1",
"type": "bidirectional",
"description": "Port 1 GPIO bit 1 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the TCPWM, SCB UART and I2C/SPI alternate functions listed in Table 2."
},
{
"number": "31",
"name": "P1.2",
"type": "bidirectional",
"description": "Port 1 GPIO bit 2 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the TCPWM, SCB and TCPWM trigger alternate functions listed in Table 2."
},
{
"number": "32",
"name": "P1.3",
"type": "bidirectional",
"description": "Port 1 GPIO bit 3 with eight selectable drive modes, CMOS or LVTTL input threshold select, selectable slew rate, and the TCPWM, SCB and TCPWM trigger alternate functions listed in Table 2."
},
{
"number": "33",
"name": "EP",
"type": "passive",
"description": "Exposed pad (from the footprint; not named in the datasheet pin table)."
}
],
"provenance": {
"extractor": "extract_pins 0.3",
"factory_chain": {
"factory": "2.0.0",
"extractor": "extract_pins 0.3",
"primary_model": "claude-haiku-5-5",
"primary_mode": "text",
"consensus_model": "claude-sonnet-5-5",
"consensus": "agreed",
"guards": "pin_guards 0.1: passed",
"guard_notes": [
"extractor flagged: Table 1 lists VDDD and VDDA on pin 27 for the 32-pin QFN column, and the table shows VDD on that pin; The provided text gives no electrical limits, polarity or pin-level details for XRES; the descriptio; VCCD is classed as power_out because it is the output of the internal 1.8 V regulator in Mode 1 (Sec",
"1/33 pins cited to the wrong page (name found elsewhere): ['27:VDD@p19']"
],
"pages_sent": 19,
"cost_usd": 0.0075,
"at": "2026-11-12T20:11:52"
},
"datasheet": {
"url": "https://www.infineon.com/dgdl/Infineon-PSoC_4_PSoC_4000S_Datasheet_Programmable_System-on-Chip_(PSoC_)-DataSheet-v15_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0eda97715cf1&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integration-file",
"pages": 58,
"sha256": "493ab905a29a5d98",
"source_tier": "mfr"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"model_3d_generated": {
"generator": "factory/gen_pkg3d.py",
"family": "QFN",
"height_mm": 0.55,
"height_basis": "datasheet A, nominal",
"standoff_mm": 0.0
},
"pins": {
"total": 33,
"described": 33,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"models_3d": [
{
"file": "cy8c4024lqi-s402.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
5.02,
5.02,
0.55
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "c6852b311a6407ec7d2c6376fe1cbabaee6ae9da6fbda3e0bd26a3e49573599d",
"checked": "2026-11-12",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "cy8c4024lqi-s402-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
5.02,
5.02,
0.55
],
"zmin_mm": 0.0,
"centre_offset_mm": 0.0,
"footprint_binding": "identity",
"sha256": "bfc230b8ae32f0f674167ffd26c9b2095656524bd6c22106b5f0985b6bcd440a",
"checked": "2026-11-12",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
],
"package_dims": {
"package_code": "LQ32 (32 LEAD QFN, drawing 001-42168, PG-VQFN-32)",
"source_page": 47,
"D": {
"nom_mm": 5.0,
"range_mm": [
4.9,
5.1
]
},
"E1": {
"nom_mm": 5.0,
"range_mm": [
4.9,
5.1
]
},
"e": {
"nom_mm": 0.5,
"range_mm": [
null,
null
]
},
"A": {
"nom_mm": 0.55,
"range_mm": [
0.5,
0.6
]
},
"source": "datasheet package drawing, every number found on its page (extract_pins --task dims)",
"model_check": {
"file": "cy8c4024lqi-s402.step",
"verdict": "PASS",
"reasons": [
"height within the datasheet's package drawing"
],
"by": "factory/package_fit.py"
}
}
}
}