CY8C4014SXI-421T from Cypress Semicon, in a SOIC-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P3.0/SDA/SWD_IO	bidirectional	Port 3 GPIO that also serves as I2C data (SDA) and SWD I/O; Port 3 pins are not available for CapSense.
2	P3.1/SCL/SWD_CLK	bidirectional	Port 3 GPIO that also serves as I2C clock (SCL) and SWD clock; Port 3 pins are not available for CapSense.
3	P0.1/TRIN1/CMPO_0	bidirectional	Port 0 GPIO usable as CapSense or AMUX bus pin, with TRIN1 trigger input and comparator output CMPO_0 alternate functions.
4	P0.2/TRIN2	bidirectional	Port 0 GPIO usable as CapSense or AMUX bus pin, with TRIN2 trigger input alternate function.
5	P0.4/TRIN4/CMPO_0/EXT_CLK	bidirectional	Port 0 GPIO usable as CapSense or AMUX bus pin, with TRIN4 trigger input, comparator output CMPO_0, external clock and CMOD capacitor alternate functions.
6	VCCD	power_out	Regulated digital supply output (1.8 V ±5%); in unregulated external supply mode it must be bypassed to ground with an external 0.1 µF X5R ceramic or better capacitor placed close to the pin.
7	VDD	power_in	Power supply for both analog and digital sections; 1.8 V to 5.5 V in unregulated external supply mode, or 1.71 V to 1.89 V in regulated external supply mode (VDD must not exceed 1.89 V in any condition).
8	VSS	power_in	Ground pin.
9	P0.5	bidirectional	Port 0 GPIO usable as CapSense or AMUX bus pin; no additional alternate function is listed for this pin on the 16-SOIC.
10	P0.6	bidirectional	Port 0 GPIO usable as CapSense or AMUX bus pin; no additional alternate function is listed for this pin on the 16-SOIC.
11	P1.1/OUT0	bidirectional	Port 1 GPIO usable as CapSense or AMUX bus pin, with TCPWM PWM output OUT0.
12	P1.2/SCL	bidirectional	Port 1 GPIO usable as CapSense or AMUX bus pin, used as I2C clock; I2C bus I/O is implemented in open-drain modes and GPIO cells are not overvoltage tolerant.
13	P1.3/SDA	bidirectional	Port 1 GPIO usable as CapSense or AMUX bus pin, used as I2C data; I2C bus I/O is implemented in open-drain modes and GPIO cells are not overvoltage tolerant.
14	P1.6/OVF0/UND0/nOUT0/CMPO_0	bidirectional	Port 1 GPIO usable as CapSense or AMUX bus pin, with TCPWM OVF0, UND0, nOUT0 and internal-reset comparator output CMPO_0 functions; it must not have a load to ground during POR (should be an output).
15	P1.7/MATCH/EXT_CLK	bidirectional	Port 1 GPIO usable as CapSense or AMUX bus pin, with MATCH output and external clock alternate functions.
16	P2.0	bidirectional	Port 2 GPIO usable as CapSense or AMUX bus pin; no additional alternate function is listed for this pin.

Key specifications

Parameter	Value
Manufacturer	Cypress Semicon
Package	SOIC-16
Category	Single Chip Microcomputer/Microcontroller
Pins	16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Digital supply relative to VSS	VDD_ABS	-0.5		6	V		14
Direct digital core voltage input relative to VSS	VCCD_ABS	-0.5		1.95	V		14
GPIO voltage	VGPIO_ABS	-0.5			V		14
Maximum current per GPIO	IGPIO_ABS	-25		25	mA		14
GPIO injection current, Max for VIH > VDD, and Min for VIL < VSS	IGPIO_injection	-0.5		0.5	mA	Current injected per pin	14
Electrostatic discharge human body model	ESD_HBM	2200			V		14
Electrostatic discharge charged device model	ESD_CDM	500			V		14
Pin current for latch-up	LU	-140		140	mA		14
Power supply input voltage	VDD	1.8		5.5	V	With regulator enabled	14
Power supply input voltage (VCCD = VDD)	VDD	1.71		1.89	V	Internally unregulated supply	14
VDDIO domain supply	VDDIO	1.71			V		14
Execute from flash; CPU at 6 MHz	IDD5		2	2.85	mA	Active Mode, VDD = 1.8 to 5.5 V; Execute from flash; CPU at 6 MHz	14
Execute from flash; CPU at 12 MHz	IDD8		3.2	3.75	mA	Active Mode, VDD = 1.8 to 5.5 V; Execute from flash; CPU at 12 MHz	14
Execute from flash; CPU at 16 MHz	IDD11		4	4.5	mA	Active Mode, VDD = 1.8 to 5.5 V; Execute from flash; CPU at 16 MHz	14
I2C wakeup and WDT on	IDD26		2.5	8.2	µA	Deep Sleep Mode, VDD = 1.8 to 3.6 V (Regulator on)	14
I2C wakeup and WDT on	IDD29		2.5	12	µA	Deep Sleep Mode, VDD = 3.6 to 5.5 V (Regulator on)	15
I2C wakeup and WDT on	IDD32		2.5	9.2	µA	Deep Sleep Mode, VDD = VCCD = 1.71 to 1.89 V (Regulator bypassed)	15
Supply current while XRES asserted	IDD_XR		2	5	mA		15
CPU frequency	FCPU			16	MHz	VDD 1.71 to 5.5 V (Details column as extracted)	15
Input voltage high threshold, LVTTL input	VIH	2			V	LVTTL input, VDD ≥ 2.7 V	15
Input voltage low threshold, LVTTL input	VIL			0.8	V	LVTTL input, VDD ≥ 2.7 V	15
Output voltage low level	VOL			0.6	V	IOL = 4 mA at 1.8 V VDD	15
Output voltage low level	VOL			0.4	V	IOL = 3 mA at 3 V VDD	15
Pull-up resistor	RPULLUP	3.5	5.6	8.5	kΩ		15
Pull-down resistor	RPULLDOWN	3.5	5.6	8.5	kΩ		15
Input leakage current (absolute value)	IIL			2	nA	25 °C, VDD = 3.0 V	15
Input capacitance	CIN		3	7	pF		15
Response Time High Bandwidth mode	TCOMP1			90	ns	High Bandwidth mode, 50-mV overdrive	18
Response Time Low Power mode	TCOMP2			110	ns	Low Power mode, 50-mV overdrive	18
Max allowed ripple on power supply, DC to 10 MHz	VDD_RIPPLE	-50		50	mV	VDD > 2 V (with ripple), 25 °C TA, Sensitivity = 0.1 pF	18
Max allowed ripple on power supply, DC to 10 MHz	VDD_RIPPLE_1.8	-25		25	mV	VDD > 1.75 V (with ripple), 25 °C TA, CP < 20 pF, Sensitivity ≥ 0.4 pF	18
Reference Buffer Output	VREFHI	1.1	1.2	1.3	V		18
IDAC1 (8-bits) block current	IDAC1IDD			1125	µA		18
IDAC2 (7-bits) block current	IDAC2IDD			1125	µA		18
Voltage range of operation	VCSD	1.71		5.5	V	1.8 V ±5% or 1.8 V to 5.5 V	18
Voltage compliance range of IDAC	VCOMPIDAC	0.8			V		18
DNL for 8-bit resolution	IDAC1DNL	-1		1	LSB		18
INL for 8-bit resolution	IDAC1INL	-3		3	LSB		18
DNL for 7-bit resolution	IDAC2DNL	-1		1	LSB		18
INL for 7-bit resolution	IDAC2INL	-3		3	LSB		18
Ratio of counts of finger to noise. Guaranteed by characterization	SNR	5			Ratio	Capacitance range of 9 to 35 pF, 0.1 pF sensitivity	18
IDACOFFSET	IDACOFFSET	-1		1	LSB	All zeroes input	18
Full-scale error less offset	IDACGAIN	-10		10	%		18
Mismatch between IDACs	IDACMISMATCH			7	LSB		18
ADC resolution	ADCRes	1			mV		19
ADC gain error	ADCError			1	%	For 0 to 5-V range, 0.1% accurate Rin/Rbleed, 1% accurate Internal Vref, Temp range of 0 to 70 °C	19
ADC offset error	ADCOffset			50	mV		19
ADC input voltage range	ADCINMAX	0			V		19
ADC integral non-linearity	ADCINL			18	mV	0 to 5-V input and 0 to 70 °C	19
ADC differential non-linearity	ADCDNL			12	mV	0 to 5-V input and 0 to 70 °C	19
ADC Sample rate	ADCSamp			58	sps		19
Block current consumption at 16 MHz	ITCPWM3			160	µA	All modes (TCPWM)	20
Block current consumption at 400 kHz	II2C2			135	µA		20
External clock input frequency	ExtClkFreq	0		16	MHz		23
Duty cycle; measured at VDD/2	ExtClkDuty	45		55	%	Measured at VDD/2	23
Operating ambient temperature	TA	-40	25	85	°C		26
Operating junction temperature	TJ	-40		100	°C		26
Package θJA (16-pin SOIC)	TJA		142		°C/Watt		26
Package θJC (16-pin SOIC)	TJC		49.8		°C/Watt		26

CAD (KiCad official)

Symbol: CY8C4014SXI-421T
Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
3D model: SOIC-16 (KiCad packages3D, STEP)
3D model files: cy8c4014sxi-421t-etched.step / cy8c4014sxi-421t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4014sxi-421t.step / cy8c4014sxi-421t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Cypress Semicon datasheet (36 pp, sha256 6c7edf8ac0f0328f, retrieved 2026-10-31, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

CY8C4014SXI-421T

Changed since verified CY8C4014SXI-421T

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

README