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CY8C4014PVI-422

Public Made by Adom

by adom

Cypress Semicon CYPRESS, SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY8C4014PVI-422

Cypress Semicon · CYPRESS · SSOP-28-208mil

CY8C4014PVI-422 from Cypress Semicon, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0.5 bidirectional GPIO on Port 0 that can also be a CSD sense or shield pin on AMUXBUS A or B.
2 P0.6 bidirectional GPIO on Port 0 that can also be a CSD sense or shield pin on AMUXBUS A or B.
3 P0.7 bidirectional GPIO on Port 0 that can also be a CSD sense or shield pin on AMUXBUS A or B.
4 P1.0 bidirectional GPIO on Port 1 that can also be a CSD sense or shield pin on AMUXBUS A or B.
5 P1.1/OUT0 bidirectional GPIO on Port 1 with OUT0 alternate function (TCPWM PWM output 0).
6 P1.2/SCL bidirectional GPIO on Port 1 with I2C clock (SCL) alternate function, implemented in open-drain mode.
7 P1.3/SDA bidirectional GPIO on Port 1 with I2C data (SDA) alternate function, implemented in open-drain mode.
8 P1.4/UND0 bidirectional GPIO on Port 1 with UND0 alternate function (TCPWM underflow output).
9 P1.5/OVF0 bidirectional GPIO on Port 1 with OVF0 alternate function (TCPWM overflow output).
10 P1.6/OVF0/UND0/nOUT0/CMPO_0 bidirectional GPIO on Port 1 with OVF0, UND0, nOUT0 and CMPO_0 alternate functions; it must not have a load to ground during POR and should be an output.
11 VSS power_in Ground pin.
12 NC unconnected This pin is not to be used and must be left floating.
13 P1.7/MATCH/EXT_CLK bidirectional GPIO on Port 1 with MATCH (match output) and EXT_CLK alternate functions.
14 P2.0 bidirectional GPIO on Port 2 that can also be a CSD sense or shield pin on AMUXBUS A or B.
15 VSS power_in Ground pin.
16 P3.0/SDA/SWD_IO bidirectional GPIO on Port 3 with I2C data (SDA) and SWD I/O alternate functions.
17 P3.1/SCL/SWD_CLK bidirectional GPIO on Port 3 with I2C clock (SCL) and SWD clock alternate functions.
18 P3.2 bidirectional GPIO on Port 3 with OUT0 alternate function (TCPWM PWM output 0).
19 XRES input External reset input.
20 VSS power_in Ground pin.
21 P0.0/TRIN0 bidirectional GPIO on Port 0 with TRIN0 alternate function (TCPWM trigger input 0).
22 P0.1/TRIN1/CMPO_0 bidirectional GPIO on Port 0 with TRIN1 trigger input and CMPO_0 sense comparator output alternate functions.
23 P0.2/TRIN2 bidirectional GPIO on Port 0 with TRIN2 alternate function (TCPWM trigger input 2).
24 P0.3/TRIN3 bidirectional GPIO on Port 0 with TRIN3 alternate function (TCPWM trigger input 3).
25 P0.4/TRIN4/CMPO_0/EXT_CLK bidirectional GPIO on Port 0 with TRIN4, CMPO_0, EXT_CLK and CMOD cap alternate functions.
26 VCCD power_out Regulated digital supply at 1.8 V +/-5%.
27 VDD power_in Power supply for both analog and digital sections.
28 VSS power_in Ground pin.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SSOP-28-208mil
Category Embedded Processors & Controllers
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Digital supply relative to VSS VDD_ABS -0.5 6 V 14
Direct digital core voltage input relative to VSS VCCD_ABS -0.5 1.95 V 14
GPIO voltage VGPIO_ABS -0.5 V 14
Maximum current per GPIO IGPIO_ABS -25 25 mA 14
GPIO injection current, Max for VIH > VDD, and Min for VIL < VSS IGPIO_injection -0.5 0.5 mA Current injected per pin 14
Electrostatic discharge human body model ESD_HBM 2200 V 14
Pin current for latch-up LU -140 140 mA 14
Power supply input voltage VDD 1.8 5.5 V With regulator enabled 14
Power supply input voltage (VCCD = VDD) VDD 1.71 1.89 V Internally unregulated supply 14
VDDIO domain supply VDDIO 1.71 V 14
Active mode current, execute from flash IDD5 2 2.85 mA Active Mode, VDD = 1.8 to 5.5 V; Execute from flash; CPU at 6 MHz 14
Active mode current, execute from flash IDD8 3.2 3.75 mA Active Mode, VDD = 1.8 to 5.5 V; Execute from flash; CPU at 12 MHz 14
Active mode current, execute from flash IDD11 4 4.5 mA Active Mode, VDD = 1.8 to 5.5 V; Execute from flash; CPU at 16 MHz 14
Deep Sleep current, I2C wakeup and WDT on IDD26 2.5 8.2 µA Deep Sleep Mode, VDD = 1.8 to 3.6 V (Regulator on) 14
Deep Sleep current, I2C wakeup and WDT on IDD32 2.5 9.2 µA Deep Sleep Mode, VDD = VCCD = 1.71 to 1.89 V (Regulator bypassed) 15
Supply current while XRES asserted IDD_XR 2 5 mA 15
CPU frequency FCPU 16 MHz VDD 1.71 to 5.5 V 15
Input voltage high threshold, LVTTL input, VDD >= 2.7 V VIH 2 V LVTTL input, VDD >= 2.7 V 15
Input voltage low threshold, LVTTL input, VDD >= 2.7 V VIL 0.8 V LVTTL input, VDD >= 2.7 V 15
Output voltage low level VOL 0.6 V IOL = 4 mA at 1.8 V VDD 15
Output voltage low level VOL 0.4 V IOL = 3 mA at 3 V VDD 15
Pull-up resistor RPULLUP 3.5 5.6 8.5 kΩ 15
Pull-down resistor RPULLDOWN 3.5 5.6 8.5 kΩ 15
Input leakage current (absolute value) IIL 2 nA 25 °C, VDD = 3.0 V 15
Input capacitance CIN 3 7 pF 15
Response Time High Bandwidth mode TCOMP1 90 ns High Bandwidth mode, 50-mV overdrive 18
Response Time Low Power mode TCOMP2 110 ns Low Power mode, 50-mV overdrive 18
Max allowed ripple on power supply, DC to 10 MHz VDD_RIPPLE -50 50 mV VDD > 2V (with ripple), 25 °C TA, Sensitivity = 0.1 pF 18
Max allowed ripple on power supply, DC to 10 MHz VDD_RIPPLE_1.8 -25 25 mV VDD > 1.75V (with ripple), 25 °C TA, Parasitic Capacitance (CP) < 20 pF, Sensitivity >= 0.4 pF 18
Reference Buffer Output VREFHI 1.1 1.2 1.3 V 18
IDAC1 (8-bits) block current IDAC1IDD 1125 µA 18
IDAC2 (7-bits) block current IDAC2IDD 1125 µA 18
Voltage range of operation VCSD 1.71 5.5 V 1.8 V ±5% or 1.8 V to 5.5 V 18
Voltage compliance range of IDAC VCOMPIDAC 0.8 V 18
DNL for 8-bit resolution IDAC1DNL -1 1 LSB 18
INL for 8-bit resolution IDAC1INL -3 3 LSB 18
DNL for 7-bit resolution IDAC2DNL -1 1 LSB 18
INL for 7-bit resolution IDAC2INL -3 3 LSB 18
Ratio of counts of finger to noise SNR 5 Ratio Capacitance range of 9 to 35 pF, 0.1 pF sensitivity 18
All zeroes input offset IDACOFFSET -1 1 LSB 18
Full-scale error less offset IDACGAIN -10 10 % 18
Mismatch between IDACs IDACMISMATCH 7 LSB 18
Settling time to 0.5 LSB for 8-bit IDAC IDACSET8 10 µs Full-scale transition. No external load. 18
Settling time to 0.5 LSB for 7-bit IDAC IDACSET7 10 µs Full-scale transition. No external load. 18
ADC resolution ADCRes 1 mV 19
ADC gain error ADCError 1 % For 0 to 5-V range, 0.1% accurate Rin / Rbleed, 1% accurate Internal Vref and Temp range of 0 to 70 °C 19
ADC offset error ADCOffset 50 mV 19
ADC ADC input voltage range minimum ADCINMAX 0 V 19
ADC integral non-linearity ADCINL 18 mV 0 to 5-V input and 0 to 70 °C 19
ADC differential non-linearity ADCDNL 12 mV 0 to 5-V input and 0 to 70 °C 19
Block current consumption at 3 MHz ITCPWM1 45 µA All modes (TCPWM) 20
Block current consumption at 8 MHz ITCPWM2 145 µA All modes (TCPWM) 20
Block current consumption at 100 kHz II2C1 25 µA 20
Block current consumption at 400 kHz II2C2 135 µA 20
I2C enabled in Deep Sleep mode ISBI2C 2.5 µA I2C enabled in Deep Sleep mode 20
Bit rate FI2C1 400 Kbps 20
External clock input frequency ExtClkFreq 0 16 MHz 23
Operating ambient temperature TA -40 25 85 °C 26
Operating junction temperature TJ -40 100 °C 26
Package thermal resistance junction to ambient (28-pin SSOP) TJA 66.6 °C/Watt 28-pin SSOP 26
Package thermal resistance junction to case (28-pin SSOP) TJC 34 °C/Watt 28-pin SSOP 26

CAD (KiCad official)

  • Symbol: CY8C4014PVI-422
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
  • 3D model files: cy8c4014pvi-422-etched.step / cy8c4014pvi-422-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c4014pvi-422.step / cy8c4014pvi-422.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (36 pp, sha256 6c7edf8ac0f0328f, retrieved 2026-10-28, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF