component
CY8C4014LQI-422T
Public Made by Adomby adom
Infineon Cypress Semicon Microcontrollers (MCU/MPU/SOC), QFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownCY8C4014LQI-422T
Infineon Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · QFN-24-EP(4x4)
CY8C4014LQI-422T from Infineon Cypress Semicon, in a QFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0.0/TRIN0 | bidirectional | Port 0 bit 0 GPIO (CapSense/analog mux capable) with TCPWM trigger input 0 (TRIN0). |
| 2 | P0.1/TRIN1/CMPO_0 | bidirectional | Port 0 bit 1 GPIO with TCPWM trigger input 1 (TRIN1) and sense comparator output CMPO_0. |
| 3 | P0.2/TRIN2 | bidirectional | Port 0 bit 2 GPIO with TCPWM trigger input 2 (TRIN2). |
| 4 | P0.3/TRIN3 | bidirectional | Port 0 bit 3 GPIO with TCPWM trigger input 3 (TRIN3). |
| 5 | P0.4/TRIN4/CMPO_0/EXT_CLK | bidirectional | Port 0 bit 4 GPIO with trigger input 4 (TRIN4), sense comparator output CMPO_0, external clock EXT_CLK and CMOD capacitor connection. |
| 6 | VCCD | power_out | Regulated digital supply (1.8 V ±5%) that must be bypassed to ground with a 0.1 µF X5R or better ceramic capacitor (printed as VCC in Table 1). |
| 7 | VDD | power_in | Power supply for both analog and digital sections, 1.8 V to 5.5 V unregulated or 1.71 V to 1.89 V regulated. |
| 8 | VSS | power_in | Ground pin. |
| 9 | P0.5 | bidirectional | Port 0 bit 5 GPIO (CapSense/analog mux capable). |
| 10 | P0.6 | bidirectional | Port 0 bit 6 GPIO (CapSense/analog mux capable). |
| 11 | P0.7 | bidirectional | Port 0 bit 7 GPIO (CapSense/analog mux capable). |
| 12 | P1.0 | bidirectional | Port 1 bit 0 GPIO (CapSense/analog mux capable). |
| 13 | P1.1/OUT0 | bidirectional | Port 1 bit 1 GPIO with TCPWM PWM output OUT0. |
| 14 | P1.2/SCL | bidirectional | Port 1 bit 2 GPIO with I2C clock (SCL), implemented in open-drain mode. |
| 15 | P1.3/SDA | bidirectional | Port 1 bit 3 GPIO with I2C data (SDA), implemented in open-drain mode. |
| 16 | P1.4/UND0 | bidirectional | Port 1 bit 4 GPIO with TCPWM underflow output UND0. |
| 17 | P1.5/OVF0 | bidirectional | Port 1 bit 5 GPIO with TCPWM overflow output OVF0. |
| 18 | P1.6/OVF0/UND0/nOUT0/CMPO_0 | bidirectional | Port 1 bit 6 GPIO with OVF0, UND0, complementary PWM output nOUT0 and CMPO_0 internal reset function, which must not have a load to ground during POR (should be an output). |
| 19 | P1.7/MATCH/EXT_CLK | bidirectional | Port 1 bit 7 GPIO with TCPWM match output MATCH and external clock EXT_CLK. |
| 20 | P2.0 | bidirectional | Port 2 bit 0 GPIO (CapSense/analog mux capable). |
| 21 | P3.0/SDA/SWD_IO | bidirectional | Port 3 bit 0 GPIO with I2C data (SDA) and SWD I/O (SWD_IO) for programming and debug. |
| 22 | P3.1/SCL/SWD_CLK | bidirectional | Port 3 bit 1 GPIO with I2C clock (SCL) and SWD clock (SWD_CLK) for programming and debug. |
| 23 | P3.2 | bidirectional | Port 3 bit 2 GPIO, which is also listed with PWM output OUT0 in the Table 1 alternate-function column. |
| 24 | XRES | input | External reset input. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Cypress Semicon |
| Package | QFN-24-EP(4x4) |
| Category | Embedded Processors & Controllers |
| Pins | 25 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Absolute maximum digital supply voltage relative to VSS | VDD_ABS | -0.5 | 6 | V | 14 | ||
| Direct digital core voltage input relative to VSS | VCCD_ABS | -0.5 | 1.95 | V | 14 | ||
| GPIO voltage | VGPIO_ABS | -0.5 | V | 14 | |||
| Maximum current per GPIO | IGPIO_ABS | -25 | 25 | mA | 14 | ||
| GPIO injection current | IGPIO_injection | -0.5 | 0.5 | mA | Current injected per pin | 14 | |
| Electrostatic discharge human body model | ESD_HBM | 2200 | V | 14 | |||
| Electrostatic discharge charged device model | ESD_CDM | 500 | V | 14 | |||
| Pin current for latch-up | LU | -140 | 140 | mA | 14 | ||
| Power supply input voltage (regulator enabled) | VDD | 1.8 | 5.5 | V | With regulator enabled | 14 | |
| Power supply input voltage (VCCD = VDD, internally unregulated supply) | VDD | 1.71 | 1.89 | V | Internally unregulated supply | 14 | |
| VDDIO domain supply | VDDIO | 1.71 | V | 14 | |||
| Active mode supply current, execute from flash, CPU at 6 MHz | IDD5 | 2 | 2.85 | mA | Active mode, VDD = 1.8 to 5.5 V; execute from flash; CPU at 6 MHz | 14 | |
| Active mode supply current, execute from flash, CPU at 12 MHz | IDD8 | 3.2 | 3.75 | mA | Active mode, VDD = 1.8 to 5.5 V; execute from flash; CPU at 12 MHz | 14 | |
| Active mode supply current, execute from flash, CPU at 16 MHz | IDD11 | 4 | 4.5 | mA | Active mode, VDD = 1.8 to 5.5 V; execute from flash; CPU at 16 MHz | 14 | |
| Deep Sleep supply current, I2C wakeup and WDT on | IDD26 | 2.5 | 8.2 | µA | Deep Sleep mode, VDD = 1.8 to 3.6 V (Regulator on); I2C wakeup and WDT on | 14 | |
| Deep Sleep supply current, I2C wakeup and WDT on | IDD29 | 2.5 | 12 | µA | Deep Sleep mode, VDD = 3.6 to 5.5 V (Regulator on); I2C wakeup and WDT on | 15 | |
| Deep Sleep supply current, I2C wakeup and WDT on | IDD32 | 2.5 | 9.2 | µA | Deep Sleep mode, VDD = VCCD = 1.71 to 1.89 V (Regulator bypassed); I2C wakeup and WDT on | 15 | |
| Supply current while XRES asserted | IDD_XR | 2 | 5 | mA | 15 | ||
| CPU frequency | FCPU | 16 | MHz | VDD 1.71 to 5.5 V | 15 | ||
| Logic high input voltage threshold, LVTTL input | VIH | 2 | V | LVTTL input, VDD ≥ 2.7 V | 15 | ||
| Logic low input voltage threshold, LVTTL input | VIL | 0.8 | V | LVTTL input, VDD ≥ 2.7 V | 15 | ||
| Output voltage low level | VOL | 0.6 | V | IOL = 4 mA at 1.8 V VDD | 15 | ||
| Output voltage low level | VOL | 0.4 | V | IOL = 3 mA at 3 V VDD | 15 | ||
| Pull-up resistor | RPULLUP | 3.5 | 5.6 | 8.5 | kΩ | 15 | |
| Pull-down resistor | RPULLDOWN | 3.5 | 5.6 | 8.5 | kΩ | 15 | |
| Input leakage current (absolute value) | IIL | 2 | nA | 25 °C, VDD = 3.0 V | 15 | ||
| Input capacitance | CIN | 3 | 7 | pF | 15 | ||
| External clock input frequency | ExtClkFreq | 0 | 16 | MHz | 22 | ||
| External clock duty cycle | ExtClkDuty | 45 | 55 | % | measured at VDD/2 | 22 | |
| System clock source switching time | TCLKSWITCH | 3 | 4 | Periods | 22 | ||
| Operating ambient temperature | TA | -40 | 25 | 85 | °C | 25 | |
| Operating junction temperature | TJ | -40 | 100 | °C | 25 | ||
| Package θJA (24-pin QFN) | TJA | 38 | °C/Watt | 24-pin QFN | 25 | ||
| Package θJC (24-pin QFN) | TJC | 5.6 | °C/Watt | 24-pin QFN | 25 |
CAD (KiCad official)
- Symbol:
CY8C4014LQI-422T - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm - 3D model: QFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
cy8c4014lqi-422t-etched.step/cy8c4014lqi-422t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy8c4014lqi-422t.step/cy8c4014lqi-422t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Cypress Semicon datasheet (35 pp, sha256
d8f010e7d78eade9, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).