component
CY8C29466-24PVXI
Public Made by Adomby adom
Cypress Semicon Pre-ordered Products, SSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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CY8C29466-24PVXI
Cypress Semicon · Pre-ordered Products · SSOP-28
CY8C29466-24PVXI from Cypress Semicon, in a SSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0[7] | bidirectional | Digital I/O with analog input; analog column mux input. |
| 2 | P0[5] | bidirectional | Digital I/O with analog I/O; analog column mux input and column output. |
| 3 | P0[3] | bidirectional | Digital I/O with analog I/O; analog column mux input and column output. |
| 4 | P0[1] | bidirectional | Digital I/O with analog input; analog column mux input. |
| 5 | P2[7] | bidirectional | General-purpose digital I/O port 2 bit 7. |
| 6 | P2[5] | bidirectional | General-purpose digital I/O port 2 bit 5. |
| 7 | P2[3] | bidirectional | Digital I/O with analog input; direct switched capacitor block input. |
| 8 | P2[1] | bidirectional | Digital I/O with analog input; direct switched capacitor block input. |
| 9 | SMP | passive | Switch mode pump (SMP) connection to external components required. |
| 10 | P1[7] | bidirectional | Digital I/O; I2C serial clock (SCL). |
| 11 | P1[5] | bidirectional | Digital I/O; I2C serial data (SDA). |
| 12 | P1[3] | bidirectional | General-purpose digital I/O port 1 bit 3. |
| 13 | P1[1] | bidirectional | Digital I/O; crystal (XTALin), I2C serial clock (SCL), ISSP-SCLK, not High Z at POR. |
| 14 | VSS | power_in | Ground connection. |
| 15 | P1[0] | bidirectional | Digital I/O; crystal (XTALout), I2C serial data (SDA), ISSP-SDATA, not High Z at POR. |
| 16 | P1[2] | bidirectional | General-purpose digital I/O port 1 bit 2. |
| 17 | P1[4] | bidirectional | Digital I/O; optional external clock input (EXTCLK). |
| 18 | P1[6] | bidirectional | General-purpose digital I/O port 1 bit 6. |
| 19 | XRES | input | Active high external reset with internal pull-down. |
| 20 | P2[0] | bidirectional | Digital I/O with analog input; direct switched capacitor block input. |
| 21 | P2[2] | bidirectional | Digital I/O with analog input; direct switched capacitor block input. |
| 22 | P2[4] | bidirectional | Digital I/O; external analog ground (AGND). |
| 23 | P2[6] | bidirectional | Digital I/O; external voltage reference (VREF). |
| 24 | P0[0] | bidirectional | Digital I/O with analog input; analog column mux input. |
| 25 | P0[2] | bidirectional | Digital I/O with analog I/O; analog column mux input and column output. |
| 26 | P0[4] | bidirectional | Digital I/O with analog I/O; analog column mux input and column output. |
| 27 | P0[6] | bidirectional | Digital I/O with analog input; analog column mux input. |
| 28 | VDD | power_in | Supply voltage. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | SSOP-28 |
| Category | Electronic Tools/Instruments/Consumables |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TSTG | -55 | 25 | 100 | °C | 22 | |
| Bake temperature | TBAKETEMP | 125 | °C | 22 | |||
| Bake time | TBAKETIME | 72 | Hours | 22 | |||
| Ambient temperature with power applied | TA | -40 | 85 | °C | 22 | ||
| Supply voltage on VDD relative to VSS | VDD | -0.5 | 6 | V | 22 | ||
| Maximum current into any port pin | IMIO | -25 | 50 | mA | 22 | ||
| Maximum current into any port pin configured as analog driver | IMAIO | -50 | 50 | mA | 22 | ||
| Electrostatic discharge voltage | ESD | 2000 | V | Human body model ESD | 22 | ||
| Latch-up current | LU | 200 | mA | 22 | |||
| Junction temperature | TJ | -40 | 100 | °C | 23 | ||
| Supply voltage | VDD | 3 | 5.25 | V | 23 | ||
| Supply current | IDD | 8 | 14 | mA | 5.0 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz | 23 | |
| Supply current | IDD3 | 5 | 9 | mA | VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz | 23 | |
| Supply current when IMO = 6 MHz using SLIMO mode | IDDP | 2 | 3 | mA | VDD = 3.3 V, TA = 25 °C, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz | 23 | |
| Sleep current | ISB | 3 | 10 | µA | internal slow speed oscillator, VDD = 3.3 V, -40 °C ≤ TA ≤ 55 °C | 23 | |
| Sleep current, high temperature | ISBH | 4 | 25 | µA | internal slow speed oscillator, VDD = 3.3 V, 55 °C < TA ≤ 85 °C | 23 | |
| Sleep current with 32 kHz crystal | ISBXTL | 4 | 12 | µA | 1 µW max 32.768 kHz crystal, VDD = 3.3 V, -40 °C ≤ TA ≤ 55 °C | 23 | |
| Sleep current with 32 kHz crystal, high temperature | ISBXTLH | 5 | 27 | µA | 1 µW max 32.768 kHz crystal, VDD = 3.3 V, 55 °C < TA ≤ 85 °C | 23 | |
| Reference voltage (Bandgap) | VREF | 1.28 | 1.3 | 1.32 | V | Trimmed for appropriate VDD | 23 |
| Pull-up resistor | RPU | 4 | 5.6 | 8 | kΩ | 24 | |
| Pull-down resistor | RPD | 4 | 5.6 | 8 | kΩ | 24 | |
| Low output level | VOL | 0.75 | V | IOL = 25 mA, VDD = 4.75 to 5.25 V | 24 | ||
| High level source current | IOH | 10 | mA | VOH = VDD, 1.0 V | 24 | ||
| Low level sink current | IOL | 25 | mA | VOL = 0.75 V | 24 | ||
| Input low level | VIL | 0.8 | V | VDD = 3.0 to 5.25 | 24 | ||
| Input high level | VIH | 2.1 | V | VDD = 3.0 to 5.25 | 24 | ||
| Input hysteresis | VH | 60 | mV | 24 | |||
| Input leakage (absolute value) | IIL | 1 | nA | Gross tested to 1 µA | 24 | ||
| Capacitive load on pins as input | CIN | 3.5 | 10 | pF | Temp = 25 °C | 24 | |
| Capacitive load on pins as output | COUT | 3.5 | 10 | pF | Temp = 25 °C | 24 | |
| Opamp input offset voltage (absolute value), 5 V | VOSOA | 1.6 | 10 | mV | all Power/Opamp bias settings | 25 | |
| Opamp average input offset voltage drift, 5 V | TCVOSOA | 4 | 23 | µV/°C | 25 | ||
| Opamp common mode rejection ratio, 5 V | CMRROA | 60 | dB | 25 | |||
| Opamp open loop gain, 5 V | GOLOA | 80 | dB | 25 | |||
| Opamp low output voltage swing, 5 V | VOLOWOA | 0.1 | V | internal signals | 25 | ||
| Opamp supply voltage rejection ratio, 5 V | PSRROA | 67 | 80 | dB | VSS ≤ VIN ≤ (VDD, 2.25) or (VDD, 1.25 V) ≤ VIN ≤ VDD | 25 | |
| LPC reference voltage range | VREFLPC | 0.2 | V | 26 | |||
| LPC supply current | ISLPC | 10 | 40 | µA | 26 | ||
| LPC voltage offset | VOSLPC | 2.5 | 30 | mV | 26 | ||
| Output buffer input offset voltage (absolute value), 5 V | VOSOB | 3.2 | 18 | mV | all Power/Opamp bias settings | 27 | |
| Output buffer average input offset voltage drift, 5 V | TCVOSOB | 5.5 | 26 | µV/°C | 27 | ||
| Output buffer output resistance, 5 V | ROUTOB | 1 | Ω | Power = Low or High | 27 | ||
| Output buffer supply current incl. bias cell, 5 V | ISOB | 1.1 | 2 | mA | no load, Power = Low | 27 | |
| Output buffer supply voltage rejection ratio, 5 V | PSRROB | 40 | 64 | dB | 27 | ||
| Output buffer load capacitance | CL | 200 | pF | external circuit driven by the analog output buffer | 27 | ||
| VDD for programming and erase | VDDP | 4.5 | 5 | 5.5 | V | 40 | |
| Low VDD for verify | VDDLV | 3 | 3.1 | 3.2 | V | 40 | |
| High VDD for verify | VDDHV | 5.1 | 5.2 | 5.3 | V | 40 | |
| Supply voltage for flash write operation | VDDIWRITE | 3.15 | 5.25 | V | 40 | ||
| Supply current during programming or verify | IDDP | 10 | 30 | mA | 40 | ||
| Input low voltage during programming or verify | VILP | 0.8 | V | 40 | |||
| Input high voltage during programming or verify | VIHP | 2.2 | V | 40 | |||
| Flash endurance (per block) | FlashENPB | 50000 | Erase/write cycles per block | 40 | |||
| Flash data retention | FlashDR | 10 | Years | 40 | |||
| I2C output low level | VOLI2C | 0.4 | V | at sink current of 3 mA | 40 | ||
| Internal main oscillator frequency for 24 MHz | FIMO24 | 22.8 | 24 | 25.2 | MHz | Trimmed for 5 V or 3.3 V operation using factory trim values; SLIMO Mode = 0 | 41 |
| IMO frequency for 6 MHz | FIMO6 | 5.5 | 6 | 6.5 | MHz | Trimmed for 5 V or 3.3 V operation using factory trim values; SLIMO Mode = 1 | 41 |
| CPU frequency (5 V Nominal) | FCPU1 | 0.0914 | 24 | 25.2 | MHz | SLIMO Mode = 0 | 41 |
| Internal low speed oscillator frequency | F32K1 | 15 | 32 | 64 | kHz | 41 | |
| Time from end of POR to CPU executing code | TPOWERUP | 16 | 100 | ms | Power-up from 0 V | 42 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | The emulator consists of a base unit that connects to the PC | 8 |
CAD (KiCad official)
- Symbol:
CY8C29466-24PVXI - Footprint:
Package_SO:SSOP-28_5.3x10.2mm_P0.65mm - 3D model: SSOP-28 (KiCad packages3D, STEP)
- 3D model files:
cy8c29466-24pvxi-etched.step/cy8c29466-24pvxi-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy8c29466-24pvxi.step/cy8c29466-24pvxi.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Cypress Semicon datasheet (70 pp, sha256
35cb0170a5a6db6c, retrieved 2026-11-02, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# CY8C29466-24PVXI
**Cypress Semicon** · Pre-ordered Products · SSOP-28
CY8C29466-24PVXI from Cypress Semicon, in a SSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0[7] | bidirectional | Digital I/O with analog input; analog column mux input. |
| 2 | P0[5] | bidirectional | Digital I/O with analog I/O; analog column mux input and column output. |
| 3 | P0[3] | bidirectional | Digital I/O with analog I/O; analog column mux input and column output. |
| 4 | P0[1] | bidirectional | Digital I/O with analog input; analog column mux input. |
| 5 | P2[7] | bidirectional | General-purpose digital I/O port 2 bit 7. |
| 6 | P2[5] | bidirectional | General-purpose digital I/O port 2 bit 5. |
| 7 | P2[3] | bidirectional | Digital I/O with analog input; direct switched capacitor block input. |
| 8 | P2[1] | bidirectional | Digital I/O with analog input; direct switched capacitor block input. |
| 9 | SMP | passive | Switch mode pump (SMP) connection to external components required. |
| 10 | P1[7] | bidirectional | Digital I/O; I2C serial clock (SCL). |
| 11 | P1[5] | bidirectional | Digital I/O; I2C serial data (SDA). |
| 12 | P1[3] | bidirectional | General-purpose digital I/O port 1 bit 3. |
| 13 | P1[1] | bidirectional | Digital I/O; crystal (XTALin), I2C serial clock (SCL), ISSP-SCLK, not High Z at POR. |
| 14 | VSS | power_in | Ground connection. |
| 15 | P1[0] | bidirectional | Digital I/O; crystal (XTALout), I2C serial data (SDA), ISSP-SDATA, not High Z at POR. |
| 16 | P1[2] | bidirectional | General-purpose digital I/O port 1 bit 2. |
| 17 | P1[4] | bidirectional | Digital I/O; optional external clock input (EXTCLK). |
| 18 | P1[6] | bidirectional | General-purpose digital I/O port 1 bit 6. |
| 19 | XRES | input | Active high external reset with internal pull-down. |
| 20 | P2[0] | bidirectional | Digital I/O with analog input; direct switched capacitor block input. |
| 21 | P2[2] | bidirectional | Digital I/O with analog input; direct switched capacitor block input. |
| 22 | P2[4] | bidirectional | Digital I/O; external analog ground (AGND). |
| 23 | P2[6] | bidirectional | Digital I/O; external voltage reference (VREF). |
| 24 | P0[0] | bidirectional | Digital I/O with analog input; analog column mux input. |
| 25 | P0[2] | bidirectional | Digital I/O with analog I/O; analog column mux input and column output. |
| 26 | P0[4] | bidirectional | Digital I/O with analog I/O; analog column mux input and column output. |
| 27 | P0[6] | bidirectional | Digital I/O with analog input; analog column mux input. |
| 28 | VDD | power_in | Supply voltage. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Cypress Semicon |
| Package | SSOP-28 |
| Category | Electronic Tools/Instruments/Consumables |
| Pins | 28 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TSTG | -55 | 25 | 100 | °C | | 22 |
| Bake temperature | TBAKETEMP | | 125 | | °C | | 22 |
| Bake time | TBAKETIME | | | 72 | Hours | | 22 |
| Ambient temperature with power applied | TA | -40 | | 85 | °C | | 22 |
| Supply voltage on VDD relative to VSS | VDD | -0.5 | | 6 | V | | 22 |
| Maximum current into any port pin | IMIO | -25 | | 50 | mA | | 22 |
| Maximum current into any port pin configured as analog driver | IMAIO | -50 | | 50 | mA | | 22 |
| Electrostatic discharge voltage | ESD | 2000 | | | V | Human body model ESD | 22 |
| Latch-up current | LU | | | 200 | mA | | 22 |
| Junction temperature | TJ | -40 | | 100 | °C | | 23 |
| Supply voltage | VDD | 3 | | 5.25 | V | | 23 |
| Supply current | IDD | | 8 | 14 | mA | 5.0 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz | 23 |
| Supply current | IDD3 | | 5 | 9 | mA | VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz | 23 |
| Supply current when IMO = 6 MHz using SLIMO mode | IDDP | | 2 | 3 | mA | VDD = 3.3 V, TA = 25 °C, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz | 23 |
| Sleep current | ISB | | 3 | 10 | µA | internal slow speed oscillator, VDD = 3.3 V, -40 °C ≤ TA ≤ 55 °C | 23 |
| Sleep current, high temperature | ISBH | | 4 | 25 | µA | internal slow speed oscillator, VDD = 3.3 V, 55 °C < TA ≤ 85 °C | 23 |
| Sleep current with 32 kHz crystal | ISBXTL | | 4 | 12 | µA | 1 µW max 32.768 kHz crystal, VDD = 3.3 V, -40 °C ≤ TA ≤ 55 °C | 23 |
| Sleep current with 32 kHz crystal, high temperature | ISBXTLH | | 5 | 27 | µA | 1 µW max 32.768 kHz crystal, VDD = 3.3 V, 55 °C < TA ≤ 85 °C | 23 |
| Reference voltage (Bandgap) | VREF | 1.28 | 1.3 | 1.32 | V | Trimmed for appropriate VDD | 23 |
| Pull-up resistor | RPU | 4 | 5.6 | 8 | kΩ | | 24 |
| Pull-down resistor | RPD | 4 | 5.6 | 8 | kΩ | | 24 |
| Low output level | VOL | | | 0.75 | V | IOL = 25 mA, VDD = 4.75 to 5.25 V | 24 |
| High level source current | IOH | 10 | | | mA | VOH = VDD, 1.0 V | 24 |
| Low level sink current | IOL | 25 | | | mA | VOL = 0.75 V | 24 |
| Input low level | VIL | | | 0.8 | V | VDD = 3.0 to 5.25 | 24 |
| Input high level | VIH | 2.1 | | | V | VDD = 3.0 to 5.25 | 24 |
| Input hysteresis | VH | | 60 | | mV | | 24 |
| Input leakage (absolute value) | IIL | | 1 | | nA | Gross tested to 1 µA | 24 |
| Capacitive load on pins as input | CIN | | 3.5 | 10 | pF | Temp = 25 °C | 24 |
| Capacitive load on pins as output | COUT | | 3.5 | 10 | pF | Temp = 25 °C | 24 |
| Opamp input offset voltage (absolute value), 5 V | VOSOA | | 1.6 | 10 | mV | all Power/Opamp bias settings | 25 |
| Opamp average input offset voltage drift, 5 V | TCVOSOA | | 4 | 23 | µV/°C | | 25 |
| Opamp common mode rejection ratio, 5 V | CMRROA | 60 | | | dB | | 25 |
| Opamp open loop gain, 5 V | GOLOA | 80 | | | dB | | 25 |
| Opamp low output voltage swing, 5 V | VOLOWOA | | | 0.1 | V | internal signals | 25 |
| Opamp supply voltage rejection ratio, 5 V | PSRROA | 67 | 80 | | dB | VSS ≤ VIN ≤ (VDD, 2.25) or (VDD, 1.25 V) ≤ VIN ≤ VDD | 25 |
| LPC reference voltage range | VREFLPC | 0.2 | | | V | | 26 |
| LPC supply current | ISLPC | | 10 | 40 | µA | | 26 |
| LPC voltage offset | VOSLPC | | 2.5 | 30 | mV | | 26 |
| Output buffer input offset voltage (absolute value), 5 V | VOSOB | | 3.2 | 18 | mV | all Power/Opamp bias settings | 27 |
| Output buffer average input offset voltage drift, 5 V | TCVOSOB | | 5.5 | 26 | µV/°C | | 27 |
| Output buffer output resistance, 5 V | ROUTOB | | 1 | | Ω | Power = Low or High | 27 |
| Output buffer supply current incl. bias cell, 5 V | ISOB | | 1.1 | 2 | mA | no load, Power = Low | 27 |
| Output buffer supply voltage rejection ratio, 5 V | PSRROB | 40 | 64 | | dB | | 27 |
| Output buffer load capacitance | CL | | | 200 | pF | external circuit driven by the analog output buffer | 27 |
| VDD for programming and erase | VDDP | 4.5 | 5 | 5.5 | V | | 40 |
| Low VDD for verify | VDDLV | 3 | 3.1 | 3.2 | V | | 40 |
| High VDD for verify | VDDHV | 5.1 | 5.2 | 5.3 | V | | 40 |
| Supply voltage for flash write operation | VDDIWRITE | 3.15 | | 5.25 | V | | 40 |
| Supply current during programming or verify | IDDP | | 10 | 30 | mA | | 40 |
| Input low voltage during programming or verify | VILP | | | 0.8 | V | | 40 |
| Input high voltage during programming or verify | VIHP | 2.2 | | | V | | 40 |
| Flash endurance (per block) | FlashENPB | 50000 | | | Erase/write cycles per block | | 40 |
| Flash data retention | FlashDR | 10 | | | Years | | 40 |
| I2C output low level | VOLI2C | | | 0.4 | V | at sink current of 3 mA | 40 |
| Internal main oscillator frequency for 24 MHz | FIMO24 | 22.8 | 24 | 25.2 | MHz | Trimmed for 5 V or 3.3 V operation using factory trim values; SLIMO Mode = 0 | 41 |
| IMO frequency for 6 MHz | FIMO6 | 5.5 | 6 | 6.5 | MHz | Trimmed for 5 V or 3.3 V operation using factory trim values; SLIMO Mode = 1 | 41 |
| CPU frequency (5 V Nominal) | FCPU1 | 0.0914 | 24 | 25.2 | MHz | SLIMO Mode = 0 | 41 |
| Internal low speed oscillator frequency | F32K1 | 15 | 32 | 64 | kHz | | 41 |
| Time from end of POR to CPU executing code | TPOWERUP | | 16 | 100 | ms | Power-up from 0 V | 42 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | | The emulator consists of a base unit that connects to the PC | 8 |
## CAD (KiCad official)
- Symbol: `CY8C29466-24PVXI`
- Footprint: `Package_SO:SSOP-28_5.3x10.2mm_P0.65mm`
- 3D model: SSOP-28 (KiCad packages3D, STEP)
- 3D model files: `cy8c29466-24pvxi-etched.step` / `cy8c29466-24pvxi-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `cy8c29466-24pvxi.step` / `cy8c29466-24pvxi.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Cypress Semicon datasheet](https://www.infineon.com/dgdl/Infineon-CY8C29466_CY8C29566_CY8C29666_CY8C29866_PSoC_Programmable_System-on-Chip-DataSheet-v31_00-EN.pdf?fileId=8ac78c8c7d0d8da4017d0ec690c03ce1&utm_source=cypress&utm_medium=referral&utm_campaign=202110_globe_en_all_integra) (70 pp, sha256 `35cb0170a5a6db6c`, retrieved 2026-11-02, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/cy8c29466-24pvxi-datasheet.pdf)