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CY8C24423A-24PVXIT

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Cypress Semicon Pre-ordered Products, SSOP-28. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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CY8C24423A-24PVXIT

Cypress Semicon · Pre-ordered Products · SSOP-28

CY8C24423A-24PVXIT from Cypress Semicon, in a SSOP-28. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P0[7] bidirectional Analog column mux input; the port pin is capable of digital I/O.
2 P0[5] bidirectional Analog column mux input and column output; the port pin is capable of digital I/O.
3 P0[3] bidirectional Analog column mux input and column output; the port pin is capable of digital I/O.
4 P0[1] bidirectional Analog column mux input; the port pin is capable of digital I/O.
5 P2[7] bidirectional General-purpose I/O pin; the pinout table lists no analog or alternate function for this pin.
6 P2[5] bidirectional General-purpose I/O pin; the pinout table lists no analog or alternate function for this pin.
7 P2[3] bidirectional Direct switched capacitor block input; the port pin is capable of digital I/O.
8 P2[1] bidirectional Direct switched capacitor block input; the port pin is capable of digital I/O.
9 SMP passive SMP connection to external components required by the on-chip switch mode pump.
10 P1[7] bidirectional I2C SCL function; the port pin is capable of digital I/O.
11 P1[5] bidirectional I2C SDA function; the port pin is capable of digital I/O.
12 P1[3] bidirectional General-purpose I/O pin; the pinout table lists no alternate function for this pin.
13 P1[1] bidirectional Crystal input (XTALin), I2C SCL, and ISSP-SCLK; the ISSP pin is not high Z at POR.
14 VSS power_in Ground connection.
15 P1[0] bidirectional Crystal output (XTALout), I2C SDA, and ISSP-SDATA; the ISSP pin is not high Z at POR.
16 P1[2] bidirectional General-purpose I/O pin; the pinout table lists no alternate function for this pin.
17 P1[4] bidirectional Optional external clock input (EXTCLK); the port pin is capable of digital I/O.
18 P1[6] bidirectional General-purpose I/O pin; the pinout table lists no alternate function for this pin.
19 XRES input Active high external reset with internal pull-down.
20 P2[0] bidirectional Direct switched capacitor block input; the port pin is capable of digital I/O.
21 P2[2] bidirectional Direct switched capacitor block input; the port pin is capable of digital I/O.
22 P2[4] bidirectional External analog ground (AGND).
23 P2[6] bidirectional External voltage reference (VREF).
24 P0[0] bidirectional Analog column mux input; the port pin is capable of digital I/O.
25 P0[2] bidirectional Analog column mux input; the port pin is capable of digital I/O.
26 P0[4] bidirectional Analog column mux input; the port pin is capable of digital I/O.
27 P0[6] bidirectional Analog column mux input; the port pin is capable of digital I/O.
28 VDD power_in Supply voltage; the Features list gives the operating voltage range as 2.4 V to 5.25 V.

Key specifications

Parameter Value
Manufacturer Cypress Semicon
Package SSOP-28
Category Electronic Tools/Instruments/Consumables
Pins 28

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature TSTG -55 25 100 °C Higher storage temperatures reduce data retention time 18
Bake time tBAKETIME 72 Hours 18
Ambient temperature with power applied TA -40 85 °C 18
Supply voltage on VDD relative to VSS VDD -0.5 6 V 18
Maximum current into any port pin IMIO -25 50 mA 18
Electrostatic discharge voltage ESD 2000 V Human body model ESD 18
Latch up current LU 200 mA 18
Ambient temperature TA -40 85 °C 19
Junction temperature TJ -40 100 °C Temperature rise from ambient to junction is package specific 19
Supply voltage VDD 2.4 5.25 V See DC POR and LVD specifications 19
Supply current IDD 5 8 mA VDD = 5.0 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, analog power = off, SLIMO mode = 0, IMO = 24 MHz 19
Supply current IDD3 3.3 6 mA VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, analog power = off, SLIMO mode = 0, IMO = 24 MHz 19
Supply current IDD27 2 4 mA VDD = 2.7 V, TA = 25 °C, CPU = 0.75 MHz, SYSCLK doubler disabled, analog power = off, SLIMO mode = 1, IMO = 6 MHz 19
Sleep (mode) current with POR, LVD, sleep timer, and WDT ISB 3 6.5 µA Internal slow speed oscillator, VDD = 3.3 V, -40 °C ≤ TA ≤ 55 °C, analog power = off 19
Sleep (mode) current at high temperature ISBH 4 25 µA Internal slow speed oscillator, VDD = 3.3 V, 55 °C < TA ≤ 85 °C, analog power = off 19
Sleep (mode) current with external crystal ISBXTL 4 7.5 µA Properly loaded 1 µW max, 32.768 kHz crystal, VDD = 3.3 V, -40 °C ≤ TA ≤ 55 °C, analog power = off 19
Sleep (mode) current with external crystal at high temperature ISBXTLH 5 26 µA Properly loaded 1 µW max, 32.768 kHz crystal, VDD = 3.3 V, 55 °C < TA ≤ 85 °C, analog power = off 19
Reference voltage (Bandgap) VREF 1.28 1.3 1.32 V Trimmed for appropriate VDD, VDD > 3.0 V 19
Reference voltage (Bandgap) VREF27 1.16 1.3 1.32 V Trimmed for appropriate VDD, VDD = 2.4 V to 3.0 V 19
Pull-up resistor RPU 4 5.6 8 k 20
Pull-down resistor RPD 4 5.6 8 k 20
Low output level VOL 0.75 V IOL = 25 mA, VDD = 4.75 to 5.25 V 20
High level source current IOH 10 mA VOH = VDD, 1.0 V 20
Low level sink current IOL 25 mA VOL = 0.75 V 20
Input low level VIL 0.8 V VDD = 3.0 to 5.25 20
Input high level VIH 2.1 V VDD = 3.0 to 5.25 20
Capacitive load on pins as input CIN 3.5 10 pF Package and pin dependent, Temp = 25 °C 20
Capacitive load on pins as output COUT 3.5 10 pF Package and pin dependent, Temp = 25 °C 20
Input offset voltage (absolute value) VOSOA 1.6 10 mV Power = low, Opamp bias = high 21
Input offset voltage (absolute value) VOSOA 1.3 8 mV Power = medium, Opamp bias = high 21
Input offset voltage (absolute value) VOSOA 1.2 7.5 mV Power = high, Opamp bias = high 21
Average input offset voltage drift TCVOSOA 7 35 µV/°C 21
Input capacitance (port 0 analog pins) CINOA 4.5 9.5 pF Package and pin dependent, Temp = 25 °C 21
Open loop gain GOLOA 60 dB Power = low, Opamp bias = high 21
Open loop gain GOLOA 80 dB Power = high, Opamp bias = high 21
Low output voltage swing (internal signals) VOLOWOA 0.2 V Power = low, Opamp bias = high 21
Low output voltage swing (internal signals) VOLOWOA 0.5 V Power = high, Opamp bias = high 21
Supply voltage rejection ratio PSRROA 64 80 dB VSS ≤ VIN ≤ (VDD, 2.25) or (VDD, 1.25 V) ≤ VIN ≤ VDD 21
Supply current (including associated AGND buffer) ISOA 150 200 µA Power = low, Opamp bias = low 21
Supply current (including associated AGND buffer) ISOA 300 400 µA Power = low, Opamp bias = high 21
Supply current (including associated AGND buffer) ISOA 600 800 µA Power = medium, Opamp bias = low 21
Supply current (including associated AGND buffer) ISOA 1200 1600 µA Power = medium, Opamp bias = high 21
Supply current (including associated AGND buffer) ISOA 2400 3200 µA Power = high, Opamp bias = low 21
Supply current (including associated AGND buffer) ISOA 4600 6400 µA Power = high, Opamp bias = high 21
Internal main oscillator (IMO) frequency for 24 MHz FIMO24 22.8 24 25.2 MHz Trimmed for 5 V or 3.3 V operation using factory trim values, SLIMO mode = 0 37
IMO frequency for 6 MHz FIMO6 5.5 6 6.5 MHz Trimmed for 5 V or 3.3 V operation using factory trim values, SLIMO mode = 1 37
CPU frequency (5 V nominal) FCPU1 0.937 24 24.6 MHz SLIMO mode = 0 37
CPU frequency (3.3 V nominal) FCPU2 0.937 12 12.3 MHz SLIMO mode = 0 37
Digital PSoC block frequency F48M 0 48 49.2 MHz Refer to the AC Digital Block Specifications 37
ILO frequency F32K1 15 32 64 kHz 37
External crystal oscillator startup to 100 ppm TOSACC 2800 3800 ms 3.0 V ≤ VDD ≤ 5.5 V, -40 °C ≤ TA ≤ 85 °C 37
24 MHz duty cycle DC24M 40 50 60 % 38
ILO duty cycle DCILO 20 50 80 % 38
48 MHz output frequency Fout48M 46.8 48 49.2 MHz Trimmed using factory trim values 38
Time from end of POR to CPU executing code tPOWERUP 16 100 ms Power-up from 0 V 38
DC programming supply voltage (programming and erase) VDDP 4.5 5 5.5 V Applies to functional requirements of external programmer tools 36
Supply voltage for flash write operation VDDIWRITE 2.7 5.25 V Applies when executing internal flash writes 36
Flash endurance (per block) FlashENPB 50000 Erase/write cycles per block Only guaranteed if flash operates within one voltage range 36
Flash data retention FlashDR 10 Years 36

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
housing PC The emulator consists of a base unit that connects to the PC 8

CAD (KiCad official)

  • Symbol: CY8C24423A-24PVXIT
  • Footprint: Package_SO:SSOP-28_5.3x10.2mm_P0.65mm
  • 3D model: SSOP-28 (KiCad packages3D, STEP)
  • 3D model files: cy8c24423a-24pvxit-etched.step / cy8c24423a-24pvxit-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); cy8c24423a-24pvxit.step / cy8c24423a-24pvxit.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Cypress Semicon datasheet (71 pp, sha256 96046f32dbd7d49d, retrieved 2026-10-25, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF