component
CY8C21534-24PVXIT
Public Made by Adomby adom
Infineon Cypress Semicon Microcontrollers (MCU/MPU/SOC), SSOP-28-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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Contents
README
markdownCY8C21534-24PVXIT
Infineon Cypress Semicon · Microcontrollers (MCU/MPU/SOC) · SSOP-28-208mil
CY8C21534-24PVXIT from Infineon Cypress Semicon, in a SSOP-28-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0[7] | bidirectional | Analog column mux input; every port pin is capable of digital I/O and connection to the common analog bus. |
| 2 | P0[5] | bidirectional | Analog column mux input and column output; every port pin is capable of digital I/O and connection to the common analog bus. |
| 3 | P0[3] | bidirectional | Analog column mux input and column output, with integrating input; every port pin is capable of digital I/O and connection to the common analog bus. |
| 4 | P0[1] | bidirectional | Analog column mux input with integrating input; every port pin is capable of digital I/O and connection to the common analog bus. |
| 5 | P2[7] | bidirectional | General-purpose port pin with analog mux connection; every port pin is capable of digital I/O and connection to the common analog bus. |
| 6 | P2[5] | bidirectional | General-purpose port pin with analog mux connection; every port pin is capable of digital I/O and connection to the common analog bus. |
| 7 | P2[3] | bidirectional | Direct switched capacitor block input; every port pin is capable of digital I/O and connection to the common analog bus. |
| 8 | P2[1] | bidirectional | Direct switched capacitor block input; every port pin is capable of digital I/O and connection to the common analog bus. |
| 9 | VSS | power_in | Ground connection; all VSS pins should be brought out to one common GND plane. |
| 10 | P1[7] | bidirectional | I2C SCL function on a digital I/O pin that is also connected to the analog mux bus. |
| 11 | P1[5] | bidirectional | I2C SDA function on a digital I/O pin that is also connected to the analog mux bus. |
| 12 | P1[3] | bidirectional | General-purpose digital I/O pin that is also connected to the analog mux bus. |
| 13 | P1[1] | bidirectional | I2C SCL and ISSP-SCLK pin; ISSP pins are not High Z at POR per the PSoC Technical Reference Manual. |
| 14 | VSS | power_in | Ground connection; all VSS pins should be brought out to one common GND plane. |
| 15 | P1[0] | bidirectional | I2C SDA and ISSP-SDATA pin; ISSP pins are not High Z at POR per the PSoC Technical Reference Manual. |
| 16 | P1[2] | bidirectional | General-purpose digital I/O pin that is also connected to the analog mux bus. |
| 17 | P1[4] | bidirectional | Optional external clock input (EXTCLK) on a digital I/O pin that is also connected to the analog mux bus. |
| 18 | P1[6] | bidirectional | General-purpose digital I/O pin that is also connected to the analog mux bus. |
| 19 | XRES | input | Active high external reset with internal pull-down. |
| 20 | P2[0] | bidirectional | Direct switched capacitor block input; every port pin is capable of digital I/O and connection to the common analog bus. |
| 21 | P2[2] | bidirectional | Direct switched capacitor block input; every port pin is capable of digital I/O and connection to the common analog bus. |
| 22 | P2[4] | bidirectional | General-purpose port pin with analog mux connection; every port pin is capable of digital I/O and connection to the common analog bus. |
| 23 | P2[6] | bidirectional | General-purpose port pin with analog mux connection; every port pin is capable of digital I/O and connection to the common analog bus. |
| 24 | P0[0] | bidirectional | Analog column mux input; every port pin is capable of digital I/O and connection to the common analog bus. |
| 25 | P0[2] | bidirectional | Analog column mux input; every port pin is capable of digital I/O and connection to the common analog bus. |
| 26 | P0[4] | bidirectional | Analog column mux input; every port pin is capable of digital I/O and connection to the common analog bus. |
| 27 | P0[6] | bidirectional | Analog column mux input; every port pin is capable of digital I/O and connection to the common analog bus. |
| 28 | VDD | power_in | Supply voltage pin. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Infineon Cypress Semicon |
| Package | SSOP-28-208mil |
| Category | Embedded Processors & Controllers |
| Pins | 28 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | TSTG | -55 | 25 | 100 | °C | 20 | |
| Bake time | tBAKETIME | 72 | Hours | 20 | |||
| Ambient temperature with power applied | TA | -40 | 85 | °C | 20 | ||
| Supply voltage on VDD relative to VSS | VDD | -0.5 | 6 | V | 20 | ||
| Maximum current into any port pin | IMIO | -25 | 50 | mA | 20 | ||
| Electrostatic discharge voltage | ESD | 2000 | V | Human body model ESD. | 20 | ||
| Latch-up current | LU | 200 | mA | 20 | |||
| Ambient temperature | TA | -40 | 85 | °C | 20 | ||
| Junction temperature | TJ | -40 | 100 | °C | 20 | ||
| Supply voltage | VDD | 2.4 | 5.25 | V | 21 | ||
| Supply current, IMO = 24 MHz | IDD | 3 | 4 | mA | Conditions are VDD = 5.0 V, TA = 25 °C, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz | 21 | |
| Supply current, IMO = 6 MHz using SLIMO mode | IDD3 | 1.2 | 2 | mA | Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz | 21 | |
| Supply current, IMO = 6 MHz using SLIMO mode (2.7 V) | IDD27 | 1.1 | 1.5 | mA | Conditions are VDD = 2.55 V, TA = 25 °C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz | 21 | |
| Sleep (mode) current with POR, LVD, sleep timer, WDT, and internal slow oscillator active, mid temperature range | ISB27 | 2.6 | 4 | µA | VDD = 2.55 V, 0 °C TA 40 °C | 21 | |
| Sleep (mode) current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active | ISB | 2.8 | 5 | µA | VDD = 3.3 V, -40 °C TA 85 °C | 21 | |
| Reference voltage (Bandgap) | VREF | 1.28 | 1.3 | 1.32 | V | Trimmed for appropriate VDD, VDD = 3.0 V to 5.25 V | 21 |
| Reference voltage (Bandgap), 2.4 V to 3.0 V | VREF27 | 1.16 | 1.3 | 1.33 | V | Trimmed for appropriate VDD, VDD = 2.4 V to 3.0 V | 21 |
| Pull-up resistor (5 V and 3.3 V GPIO) | RPU | 4 | 5.6 | 8 | k | 22 | |
| Pull-down resistor (5 V and 3.3 V GPIO) | RPD | 4 | 5.6 | 8 | k | 22 | |
| Low output level (5 V and 3.3 V GPIO) | VOL | 0.75 | V | IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total loads) | 22 | ||
| High level source current (5 V and 3.3 V GPIO) | IOH | 10 | mA | VOH = VDD, 1.0 V | 22 | ||
| Low level sink current (5 V and 3.3 V GPIO) | IOL | 25 | mA | VOL = 0.75 V | 22 | ||
| Input low level (5 V and 3.3 V GPIO) | VIL | 0.8 | V | VDD = 3.0 to 5.25 | 22 | ||
| Input high level (5 V and 3.3 V GPIO) | VIH | 2.1 | V | VDD = 3.0 to 5.25 | 22 | ||
| Capacitive load on pins as input (5 V and 3.3 V GPIO) | CIN | 3.5 | 10 | pF | Package and pin dependent, Temp = 25 °C | 22 | |
| Capacitive load on pins as output (5 V and 3.3 V GPIO) | COUT | 3.5 | 10 | pF | Package and pin dependent, Temp = 25 °C | 22 | |
| Pull-up resistor (2.7 V GPIO) | RPU | 4 | 5.6 | 8 | k | 22 | |
| Pull-down resistor (2.7 V GPIO) | RPD | 4 | 5.6 | 8 | k | 22 | |
| Low output level (2.7 V GPIO) | VOL | 0.75 | V | IOL = 10 mA, VDD = 2.4 to 3.0 V (90 mA maximum combined IOL budget) | 22 | ||
| High level source current (2.7 V GPIO) | IOH | 2.5 | mA | VOH = VDD, 0.4 V | 22 | ||
| Low level sink current (2.7 V GPIO) | IOL | 10 | mA | VOL = 0.75 V | 22 | ||
| Input low level (2.7 V GPIO) | VIL | 0.75 | V | VDD = 2.4 to 3.0 | 22 | ||
| Input high level (2.7 V GPIO) | VIH | 2 | V | VDD = 2.4 to 3.0 | 22 | ||
| Capacitive load on pins as input (2.7 V GPIO) | CIN | 3.5 | 10 | pF | Package and pin dependent, Temp = 25 °C | 22 | |
| Capacitive load on pins as output (2.7 V GPIO) | COUT | 3.5 | 10 | pF | Package and pin dependent, Temp = 25 °C | 22 | |
| IMO frequency for 24 MHz | FIMO24 | 23.4 | 24 | 24.6 | MHz | Trimmed for 5 V or 3.3 V operation using factory trim values. SLIMO mode = 0 | 27 |
| IMO frequency for 6 MHz (5 V and 3.3 V) | FIMO6 | 5.52 | 6 | 6.48 | MHz | Trimmed for 5 V or 3.3 V operation using factory trim values. SLIMO mode = 1 | 27 |
| CPU frequency (5 V nominal) | FCPU1 | 0.091 | 24 | 24.6 | MHz | 27 | |
| CPU frequency (3.3 V nominal) | FCPU2 | 0.091 | 12 | 12.3 | MHz | SLIMO mode = 0 | 27 |
| Digital PSoC block frequency (5 V nominal) | FBLK5 | 0 | 48 | 49.2 | MHz | 27 | |
| Digital PSoC block frequency (3.3 V nominal) | FBLK33 | 0 | 24 | 24.6 | MHz | 27 | |
| ILO frequency | F32K1 | 15 | 32 | 64 | kHz | 27 | |
| ILO untrimmed frequency | F32K_U | 5 | 100 | kHz | After a reset and before the M8C starts to run, the ILO is not trimmed | 27 | |
| External reset pulse width | tXRST | 10 | s | 27 | |||
| 24 MHz duty cycle | DC24M | 40 | 50 | 60 | % | 27 | |
| ILO duty cycle (5 V and 3.3 V) | DCILO | 20 | 50 | 80 | % | 27 | |
| 48 MHz output frequency | Fout48M | 46.8 | 48 | 49.2 | MHz | Trimmed. Using factory trim values | 27 |
| Maximum frequency of signal on row input or row output | FMAX | 12.3 | MHz | 27 | |||
| Power supply slew rate | SRPOWER_UP | 250 | V/ms | VDD slew rate during power-up | 27 | ||
| Time from end of POR to CPU executing code | tPOWERUP | 16 | 100 | ms | Power-up from 0 V | 27 | |
| Frequency with CPU clock divide by 1 (3.3 V) | FOSCEXT | 0.093 | 12.3 | MHz | 32 | ||
| Frequency with CPU clock divide by 2 or greater (3.3 V) | FOSCEXT | 0.186 | 24.6 | MHz | 32 | ||
| High period with CPU clock divide by 1 (3.3 V) | 41.7 | 5300 | ns | 32 | |||
| Low period with CPU clock divide by 1 (3.3 V) | 41.7 | ns | 32 | ||||
| Power-up IMO to switch (3.3 V) | 150 | µs | 32 | ||||
| IMO frequency for 12 MHz | FIMO12 | 11.04 | 120 | 12.96 | MHz | Trimmed for 2.7 V operation using factory trim values. SLIMO mode = 1 | 28 |
| CPU frequency (2.7 V nominal) | FCPU1 | 0.093 | 3 | 3.15 | MHz | 28 | |
| Digital PSoC block frequency (2.7 V nominal) | FBLK27 | 0 | 12 | 12.5 | MHz | 28 | |
| SCL clock frequency (Standard Mode, 2.7 V) | FSCLI2C | 0 | 100 | kHz | Standard Mode, 2.4 V to 3.0 V (Fast Mode not supported) | 34 | |
| SCL clock frequency (Fast Mode, 3.0 V) | FSCLI2C | 0 | 400 | kHz | Fast Mode, VDD 3.0 V | 33 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | PC | The emulator consists of a base unit that connects to the PC | 7 |
CAD (KiCad official)
- Symbol:
CY8C21534-24PVXIT - Footprint:
Package_SO:SSOP-28_5.3x10.2mm_P0.65mm - 3D model: SSOP-28-208mil (KiCad packages3D, STEP)
- 3D model files:
cy8c21534-24pvxit-etched.step/cy8c21534-24pvxit-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);cy8c21534-24pvxit.step/cy8c21534-24pvxit.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Infineon Cypress Semicon datasheet (60 pp, sha256
7db3409733a84c2e, retrieved 2026-10-17, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).